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authorAseda Aboagye <aaboagye@google.com>2017-07-07 15:28:52 -0700
committerchrome-bot <chrome-bot@chromium.org>2017-07-11 13:13:03 -0700
commit7903342436bfef4941b20a3c839f14b5398b9119 (patch)
treea216e4418dc3607c5a49e205436a189da0fbed39
parent143d175d633a7c7bcbea0b18e8f594dba8342569 (diff)
downloadchrome-ec-7903342436bfef4941b20a3c839f14b5398b9119.tar.gz
power: Add Cannonlake chipset support.
BUG=b:63508740 BRANCH=None TEST=`make -j buildall` Change-Id: I66e0e229c61c85af8f1f1c263e107e9990399e6a Signed-off-by: Aseda Aboagye <aaboagye@google.com> Reviewed-on: https://chromium-review.googlesource.com/564798 Commit-Ready: Aseda Aboagye <aaboagye@chromium.org> Tested-by: Aseda Aboagye <aaboagye@chromium.org> Reviewed-by: Randall Spangler <rspangler@chromium.org>
-rw-r--r--include/config.h1
-rw-r--r--power/build.mk1
-rw-r--r--power/cannonlake.c118
-rw-r--r--power/cannonlake.h30
-rw-r--r--power/intel_x86.c4
5 files changed, 153 insertions, 1 deletions
diff --git a/include/config.h b/include/config.h
index b306792619..f6dc9ec5a8 100644
--- a/include/config.h
+++ b/include/config.h
@@ -592,6 +592,7 @@
/* AP chipset support; pick at most one */
#undef CONFIG_CHIPSET_APOLLOLAKE/* Intel Apollolake (x86) */
#undef CONFIG_CHIPSET_BRASWELL /* Intel Braswell (x86) */
+#undef CONFIG_CHIPSET_CANNONLAKE /* Intel Cannonlake (x86) */
#undef CONFIG_CHIPSET_ECDRIVEN /* Dummy power module */
#undef CONFIG_CHIPSET_MEDIATEK /* MediaTek MT81xx */
#undef CONFIG_CHIPSET_RK3399 /* Rockchip rk3399 */
diff --git a/power/build.mk b/power/build.mk
index 5fea627667..eaca94c9ef 100644
--- a/power/build.mk
+++ b/power/build.mk
@@ -8,6 +8,7 @@
power-$(CONFIG_CHIPSET_APOLLOLAKE)+=apollolake.o intel_x86.o
power-$(CONFIG_CHIPSET_BRASWELL)+=braswell.o
+power-$(CONFIG_CHIPSET_CANNONLAKE)+=cannonlake.o intel_x86.o
power-$(CONFIG_CHIPSET_ECDRIVEN)+=ec_driven.o
power-$(CONFIG_CHIPSET_MEDIATEK)+=mediatek.o
power-$(CONFIG_CHIPSET_RK3399)+=rk3399.o
diff --git a/power/cannonlake.c b/power/cannonlake.c
new file mode 100644
index 0000000000..49a38051c3
--- /dev/null
+++ b/power/cannonlake.c
@@ -0,0 +1,118 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Cannonlake chipset power control module for Chrome EC */
+
+#include "cannonlake.h"
+#include "chipset.h"
+#include "console.h"
+#include "gpio.h"
+#include "intel_x86.h"
+#include "power.h"
+#include "power_button.h"
+#include "timer.h"
+
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_CHIPSET, format, ## args)
+
+static int forcing_shutdown; /* Forced shutdown in progress? */
+
+void chipset_force_shutdown(void)
+{
+ CPRINTS("%s()", __func__);
+
+ /*
+ * Force off. Sending a reset command to the PMIC will power off
+ * the EC, so simulate a long power button press instead. This
+ * condition will reset once the state machine transitions to G3.
+ * Consider reducing the latency here by changing the power off
+ * hold time on the PMIC.
+ */
+ if (!chipset_in_state(CHIPSET_STATE_HARD_OFF)) {
+ forcing_shutdown = 1;
+ power_button_pch_press();
+ }
+}
+
+void chipset_handle_espi_reset_assert(void)
+{
+ /*
+ * If eSPI_Reset# pin is asserted without SLP_SUS# being asserted, then
+ * it means that there is an unexpected power loss (global reset
+ * event). In this case, check if shutdown was being forced by pressing
+ * power button. If yes, release power button.
+ */
+ if ((power_get_signals() & IN_PCH_SLP_SUS_DEASSERTED) &&
+ forcing_shutdown) {
+ power_button_pch_release();
+ forcing_shutdown = 0;
+ }
+}
+
+void chipset_reset(int cold_reset)
+{
+ CPRINTS("%s(%d)", __func__, cold_reset);
+
+ if (cold_reset) {
+ if (gpio_get_level(GPIO_SYS_RESET_L) == 0)
+ return;
+ gpio_set_level(GPIO_SYS_RESET_L, 0);
+ /* Debounce time for SYS_RESET_L is 16 ms */
+ udelay(20 * MSEC);
+ gpio_set_level(GPIO_SYS_RESET_L, 1);
+ } else {
+ /* Warm reset. */
+ /*
+ * TODO(aaboagye): something about platform reset?? But we
+ * don't have that...
+ */
+ }
+}
+
+enum power_state chipset_force_g3(void)
+{
+ CPRINTS("Faking G3. (NOOP for now.)");
+ /* TODO(aaboagye): Do the right thing for real. */
+ return POWER_G3;
+}
+
+enum power_state power_handle_state(enum power_state state)
+{
+ enum power_state new_state;
+ int dswpwrok_in = gpio_get_level(GPIO_PMIC_DPWROK);
+
+ /* Pass-through DSW_PWROK to CNL. */
+ gpio_set_level(GPIO_PCH_DSW_PWROK, dswpwrok_in);
+ CPRINTS("Pass thru GPIO_DSW_PWROK: %d", dswpwrok_in);
+
+ common_intel_x86_handle_rsmrst(state);
+
+ if (state == POWER_S5 && forcing_shutdown) {
+ power_button_pch_release();
+ forcing_shutdown = 0;
+ }
+
+ /* TODO(aaboagye): Enable 3300_DSW in Deep Sx only. */
+ switch (state) {
+ case POWER_S5S3:
+ /*
+ * In S3, enable 5V rail. Wireless rails are handled by common
+ * x86 chipset code.
+ */
+ gpio_set_level(GPIO_EN_PP5000, 1);
+ break;
+
+ case POWER_S3S5:
+ gpio_set_level(GPIO_EN_PP5000, 0);
+ break;
+
+ default:
+ break;
+ };
+
+ new_state = common_intel_x86_power_handle_state(state);
+
+ return new_state;
+}
diff --git a/power/cannonlake.h b/power/cannonlake.h
new file mode 100644
index 0000000000..da67c7cbb8
--- /dev/null
+++ b/power/cannonlake.h
@@ -0,0 +1,30 @@
+/* Copyright 2017 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Cannonlake chipset power control module for Chrome EC */
+
+#ifndef __CROS_EC_CANNONLAKE_H
+#define __CROS_EC_CANNONLAKE_H
+
+/* Input state flags. */
+#define IN_PCH_SLP_S3_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S3_DEASSERTED)
+#define IN_PCH_SLP_S4_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_S4_DEASSERTED)
+#define IN_PCH_SLP_SUS_DEASSERTED POWER_SIGNAL_MASK(X86_SLP_SUS_DEASSERTED)
+
+#define IN_ALL_PM_SLP_DEASSERTED (IN_PCH_SLP_S3_DEASSERTED | \
+ IN_PCH_SLP_S4_DEASSERTED | \
+ IN_PCH_SLP_SUS_DEASSERTED)
+
+/* TODO(aaboagye): Should this be PMIC_DPWROK ? */
+#define IN_PGOOD_ALL_CORE 0
+
+#define IN_ALL_S0 (IN_PGOOD_ALL_CORE | IN_ALL_PM_SLP_DEASSERTED)
+
+#define CHIPSET_G3S5_POWERUP_SIGNAL IN_PCH_SLP_SUS_DEASSERTED
+
+#define CHARGER_INITIALIZED_DELAY_MS 100
+#define CHARGER_INITIALIZED_TRIES 40
+
+#endif /* __CROS_EC_CANNONLAKE_H */
diff --git a/power/intel_x86.c b/power/intel_x86.c
index cb3dc93e0e..5d08397912 100644
--- a/power/intel_x86.c
+++ b/power/intel_x86.c
@@ -26,6 +26,8 @@
/* Chipset specific header files */
#ifdef CONFIG_CHIPSET_APOLLOLAKE
#include "apollolake.h"
+#elif defined(CONFIG_CHIPSET_CANNONLAKE)
+#include "cannonlake.h"
#elif defined(CONFIG_CHIPSET_SKYLAKE)
#include "skylake.h"
#endif
@@ -431,7 +433,7 @@ void common_intel_x86_handle_rsmrst(enum power_state state)
/* Only passthrough RSMRST_L de-assertion on power up */
if (rsmrst_in && !power_s5_up)
return;
-#elif defined(CONFIG_CHIPSET_SKYLAKE)
+#elif defined(CONFIG_CHIPSET_SKYLAKE) || defined(CONFIG_CHIPSET_CANNONLAKE)
/*
* Wait at least 10ms between power signals going high
* and deasserting RSMRST to PCH.