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authorDaisuke Nojiri <dnojiri@chromium.org>2017-08-24 18:15:19 -0700
committerchrome-bot <chrome-bot@chromium.org>2017-08-29 19:37:05 -0700
commit3dc0eae365305c84947fff5d1976e74d950b04e3 (patch)
tree83989b68c1ea28041199c6e0e5f0f2e5babaced0
parentff87bfac4e4883dff6076887f28358e2ea51b11e (diff)
downloadchrome-ec-3dc0eae365305c84947fff5d1976e74d950b04e3.tar.gz
EFS: Rename CONFIG_VBOOT_EC to _EFS
This patch renames CONFIG_VBOOT_ET to CONFIG_VBOOT_EFS. It also adds the macro to config.h. BUG=none BRANCH=none TEST=make buidlall Change-Id: I7cb9f4c73da635b36119db74bac6fe26e77a07d2 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/639955 Reviewed-by: Randall Spangler <rspangler@chromium.org>
-rw-r--r--board/fizz/board.h2
-rw-r--r--chip/npcx/system.c2
-rw-r--r--common/build.mk2
-rw-r--r--common/main.c7
-rw-r--r--common/vboot/vboot.c6
-rw-r--r--include/config.h3
-rw-r--r--power/intel_x86.c2
7 files changed, 13 insertions, 11 deletions
diff --git a/board/fizz/board.h b/board/fizz/board.h
index ba7c9e819c..75ff25b5da 100644
--- a/board/fizz/board.h
+++ b/board/fizz/board.h
@@ -135,7 +135,7 @@
#define I2C_ADDR_TCPC0 0x16
/* Verify and jump to RW image on boot */
-#define CONFIG_VBOOT_EC
+#define CONFIG_VBOOT_EFS
#define CONFIG_VBOOT_HASH
#define CONFIG_VSTORE
#define CONFIG_VSTORE_SLOT_COUNT 1
diff --git a/chip/npcx/system.c b/chip/npcx/system.c
index 4326333295..a81c3cd383 100644
--- a/chip/npcx/system.c
+++ b/chip/npcx/system.c
@@ -182,7 +182,7 @@ static int bbram_idx_lookup(enum system_bbram_idx idx)
if (idx == SYSTEM_BBRAM_IDX_PD1)
return BBRM_DATA_INDEX_PD1;
#endif
-#ifdef CONFIG_VBOOT_EC
+#ifdef CONFIG_VBOOT_EFS
if (idx == SYSTEM_BBRAM_IDX_TRY_SLOT)
return BBRM_DATA_INDEX_TRY_SLOT;
#endif
diff --git a/common/build.mk b/common/build.mk
index 81cc8b76ea..fe751979f8 100644
--- a/common/build.mk
+++ b/common/build.mk
@@ -117,7 +117,7 @@ common-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_protocol.o usb_pd_policy.o
common-$(CONFIG_USB_PD_LOGGING)+=event_log.o pd_log.o
common-$(CONFIG_USB_PD_TCPC)+=usb_pd_tcpc.o
common-$(CONFIG_USB_UPDATE)+=usb_update.o update_fw.o
-common-$(CONFIG_VBOOT_EC)+=vboot/vboot.o
+common-$(CONFIG_VBOOT_EFS)+=vboot/vboot.o
common-$(CONFIG_VBOOT_HASH)+=sha256.o vboot_hash.o
common-$(CONFIG_VSTORE)+=vstore.o
common-$(CONFIG_WIRELESS)+=wireless.o
diff --git a/common/main.c b/common/main.c
index b2eb2eebe4..8a1c1dabb1 100644
--- a/common/main.c
+++ b/common/main.c
@@ -170,8 +170,8 @@ test_mockable __keep int main(void)
button_init();
#endif
-#ifndef CONFIG_VBOOT_EC
-#if defined(CONFIG_RWSIG) && !defined(HAS_TASK_RWSIG)
+#if !defined(CONFIG_VBOOT_EFS) && \
+ defined(CONFIG_RWSIG) && !defined(HAS_TASK_RWSIG)
/*
* Check the RW firmware signature and jump to it if it is good.
*
@@ -192,8 +192,7 @@ test_mockable __keep int main(void)
rwsig_jump_now();
}
}
-#endif
-#endif /* !CONFIG_VBOOT_EC */
+#endif /* !CONFIG_VBOOT_EFS && CONFIG_RWSIG && !HAS_TASK_RWSIG */
/*
* Print the init time. Not completely accurate because it can't take
diff --git a/common/vboot/vboot.c b/common/vboot/vboot.c
index 9affcf4592..84e278fc1b 100644
--- a/common/vboot/vboot.c
+++ b/common/vboot/vboot.c
@@ -35,9 +35,9 @@ static int has_matrix_keyboard(void)
return 0;
}
-static int is_vboot_ec_supported(void)
+static int is_efs_supported(void)
{
-#ifdef CONFIG_VBOOT_EC
+#ifdef CONFIG_VBOOT_EFS
return 1;
#else
return 0;
@@ -230,7 +230,7 @@ static void vboot_main(void)
return;
}
- if (!is_vboot_ec_supported()) {
+ if (!is_efs_supported()) {
if (is_low_power_ap_boot_supported())
/* If a device supports this feature, AP's boot power
* threshold should be set low. That will let EC-RO
diff --git a/include/config.h b/include/config.h
index e4d40ae16f..6d7c8439d3 100644
--- a/include/config.h
+++ b/include/config.h
@@ -2814,6 +2814,9 @@
/*****************************************************************************/
+/* Support early firmware selection */
+#undef CONFIG_VBOOT_EFS
+
/* Support computing hash of code for verified boot */
#undef CONFIG_VBOOT_HASH
diff --git a/power/intel_x86.c b/power/intel_x86.c
index f73e00d700..8e285559d4 100644
--- a/power/intel_x86.c
+++ b/power/intel_x86.c
@@ -285,7 +285,7 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
return POWER_G3;
}
-#ifdef CONFIG_VBOOT_EC
+#ifdef CONFIG_VBOOT_EFS
/*
* We have to test power readiness here (instead of S5->S3)
* because when entering S5, EC enables EC_ROP_SLP_SUS pin