Move core-specific toolchain configuration to core/ directory

This is preparatory work to introduce a second core architecture.

Signed-off-by: Vincent Palatin <vpalatin@chromium.org>

BRANCH=none
BUG=chrome-os-partner:23574
TEST=./util/make_all.sh

Change-Id: Icae8a7e475a4ba2a13f0d8f95629e8498a5a61da
Reviewed-on: https://chromium-review.googlesource.com/175419
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
Commit-Queue: Vincent Palatin <vpalatin@chromium.org>

7 files changed, 26 insertions, 5 deletions

diff --git a/Makefile.toolchain b/Makefile.toolchain
index bee4b4a864..caa306ca51 100644
--- a/Makefile.toolchain
+++ b/Makefile.toolchain
@@ -7,7 +7,6 @@
 #
 
 # Toolchain configuration
-CROSS_COMPILE ?= arm-none-eabi-
 HOST_CROSS_COMPILE ?= x86_64-pc-linux-gnu-
 
 CC=$(CROSS_COMPILE)gcc
diff --git a/chip/lm4/config_chip.h b/chip/lm4/config_chip.h
index 81ceed1b09..419d4b9a6d 100644
--- a/chip/lm4/config_chip.h
+++ b/chip/lm4/config_chip.h
@@ -6,6 +6,9 @@
 #ifndef __CROS_EC_CONFIG_CHIP_H
 #define __CROS_EC_CONFIG_CHIP_H
 
+/* CPU core BFD configuration */
+#include "core/cortex-m/config_core.h"
+
 /* 16.000 Mhz internal oscillator frequency (PIOSC) */
 #define INTERNAL_CLOCK 16000000
 
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index ea5017842d..5126870d11 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -6,6 +6,9 @@
 #ifndef __CROS_EC_CONFIG_CHIP_H
 #define __CROS_EC_CONFIG_CHIP_H
 
+/* CPU core BFD configuration */
+#include "core/cortex-m/config_core.h"
+
 /* Default to UART 1 for EC console */
 #define CONFIG_UART_CONSOLE 1
 
diff --git a/common/firmware_image.lds.S b/common/firmware_image.lds.S
index 08e2138ad0..c655b4856d 100644
--- a/common/firmware_image.lds.S
+++ b/common/firmware_image.lds.S
@@ -5,8 +5,8 @@
 
 #include "config.h"
 
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
+OUTPUT_FORMAT(BFD_FORMAT, BFD_FORMAT, BFD_FORMAT)
+OUTPUT_ARCH(BFD_ARCH)
 MEMORY
 {
     FLASH (rx) : ORIGIN = CONFIG_FLASH_BASE, LENGTH = CONFIG_FLASH_SIZE
diff --git a/core/cortex-m/build.mk b/core/cortex-m/build.mk
index c3ae55a521..d90b36f9ab 100644
--- a/core/cortex-m/build.mk
+++ b/core/cortex-m/build.mk
@@ -6,6 +6,9 @@
 # Cortex-M4 core OS files build
 #
 
+# Select ARMv7-m bare-metal toolchain
+CROSS_COMPILE?=arm-none-eabi-
+
 # FPU compilation flags
 CFLAGS_FPU-$(CONFIG_FPU)=-mfpu=fpv4-sp-d16 -mfloat-abi=hard
 
diff --git a/core/cortex-m/config_core.h b/core/cortex-m/config_core.h
new file mode 100644
index 0000000000..7f3d253427
--- /dev/null
+++ b/core/cortex-m/config_core.h
@@ -0,0 +1,13 @@
+/* Copyright (c) 2013 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CONFIG_CORE_H
+#define __CONFIG_CORE_H
+
+/* Linker binary architecture and format */
+#define BFD_ARCH arm
+#define BFD_FORMAT "elf32-littlearm"
+
+#endif /* __CONFIG_CORE_H */
diff --git a/core/cortex-m/ec.lds.S b/core/cortex-m/ec.lds.S
index 6d858abd15..093b47bb20 100644
--- a/core/cortex-m/ec.lds.S
+++ b/core/cortex-m/ec.lds.S
@@ -11,8 +11,8 @@
 #define FW_SIZE(section) FW_SIZE_(section)
 
 
-OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm")
-OUTPUT_ARCH(arm)
+OUTPUT_FORMAT(BFD_FORMAT, BFD_FORMAT, BFD_FORMAT)
+OUTPUT_ARCH(BFD_ARCH)
 ENTRY(reset)
 MEMORY
 {