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authorTzung-Bi Shih <tzungbi@chromium.org>2021-06-24 15:05:32 +0800
committerCommit Bot <commit-bot@chromium.org>2021-06-25 03:42:23 +0000
commitd18d88b3576bd159e26753321d8fb5e2e280d42a (patch)
treecc6d37c5a8b5eede4adbfda7bb9826a158eed88e
parentfd85931c6db4d236917d6fadcff2ccfd48109ab0 (diff)
downloadchrome-ec-d18d88b3576bd159e26753321d8fb5e2e280d42a.tar.gz
chip/mt_scp: move mt8183 specific to sub-folder
BRANCH=none BUG=b:191835814 TEST=make BOARD=kukui_scp Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org> Change-Id: Ic8387200a741a4e7ef99e13772231a0ec0bc1fc1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2984255 Reviewed-by: Eric Yilun Lin <yllin@google.com>
-rw-r--r--chip/mt_scp/build.mk28
-rw-r--r--chip/mt_scp/config_chip.h64
-rw-r--r--chip/mt_scp/mt8183/audio_codec_wov.c (renamed from chip/mt_scp/audio_codec_wov.c)0
-rw-r--r--chip/mt_scp/mt8183/build.mk35
-rw-r--r--chip/mt_scp/mt8183/clock.c (renamed from chip/mt_scp/clock.c)0
-rw-r--r--chip/mt_scp/mt8183/clock_chip.h (renamed from chip/mt_scp/clock_chip.h)0
-rw-r--r--chip/mt_scp/mt8183/config_chip.h64
-rw-r--r--chip/mt_scp/mt8183/gpio.c (renamed from chip/mt_scp/gpio.c)0
-rw-r--r--chip/mt_scp/mt8183/hrtimer.c (renamed from chip/mt_scp/hrtimer.c)0
-rw-r--r--chip/mt_scp/mt8183/ipi.c (renamed from chip/mt_scp/ipi.c)0
-rw-r--r--chip/mt_scp/mt8183/ipi_chip.h (renamed from chip/mt_scp/ipi_chip.h)0
-rw-r--r--chip/mt_scp/mt8183/ipi_table.c (renamed from chip/mt_scp/ipi_table.c)0
-rw-r--r--chip/mt_scp/mt8183/memmap.c (renamed from chip/mt_scp/memmap.c)0
-rw-r--r--chip/mt_scp/mt8183/memmap.h (renamed from chip/mt_scp/memmap.h)0
-rw-r--r--chip/mt_scp/mt8183/registers.h (renamed from chip/mt_scp/registers.h)0
-rw-r--r--chip/mt_scp/mt8183/serial_reg.h (renamed from chip/mt_scp/serial_reg.h)0
-rw-r--r--chip/mt_scp/mt8183/system.c (renamed from chip/mt_scp/system.c)0
-rw-r--r--chip/mt_scp/mt8183/uart.c (renamed from chip/mt_scp/uart.c)0
-rw-r--r--chip/mt_scp/mt8183/watchdog.c (renamed from chip/mt_scp/watchdog.c)0
19 files changed, 108 insertions, 83 deletions
diff --git a/chip/mt_scp/build.mk b/chip/mt_scp/build.mk
index fa6164056e..2f791a5476 100644
--- a/chip/mt_scp/build.mk
+++ b/chip/mt_scp/build.mk
@@ -6,29 +6,11 @@
# SCP specific files build
#
-CORE:=cortex-m
-CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
-
# Required chip modules
-chip-y=clock.o gpio.o memmap.o system.o uart.o
-
-ifeq ($(CONFIG_IPI),y)
-$(out)/RO/chip/$(CHIP)/ipi_table.o: $(out)/ipi_table_gen.inc
-$(out)/RW/chip/$(CHIP)/ipi_table.o: $(out)/ipi_table_gen.inc
-endif
+chip-y=
-ifeq ($(CONFIG_AUDIO_CODEC_WOV),y)
-HOTWORD_PRIVATE_LIB:=private/libkukui_scp_google_hotword_dsp_api.a
-ifneq ($(wildcard $(HOTWORD_PRIVATE_LIB)),)
-LDFLAGS_EXTRA+=$(HOTWORD_PRIVATE_LIB)
-HAVE_PRIVATE_AUDIO_CODEC_WOV_LIBS:=y
+ifeq ($(CHIP_VARIANT),mt8183)
+CPPFLAGS+=-Ichip/$(CHIP)/$(CHIP_VARIANT)
+dirs-y+=chip/$(CHIP)/$(CHIP_VARIANT)
+include chip/$(CHIP)/$(CHIP_VARIANT)/build.mk
endif
-endif
-
-# Optional chip modules
-chip-$(CONFIG_AUDIO_CODEC_WOV)+=audio_codec_wov.o
-chip-$(CONFIG_COMMON_TIMER)+=hrtimer.o
-chip-$(CONFIG_I2C)+=i2c.o
-chip-$(CONFIG_IPI)+=ipi.o ipi_table.o
-chip-$(CONFIG_SPI)+=spi.o
-chip-$(CONFIG_WATCHDOG)+=watchdog.o
diff --git a/chip/mt_scp/config_chip.h b/chip/mt_scp/config_chip.h
index e0710a908b..91be11dff2 100644
--- a/chip/mt_scp/config_chip.h
+++ b/chip/mt_scp/config_chip.h
@@ -1,64 +1,8 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
* Use of this source code is governed by a BSD-style license that can be
* found in the LICENSE file.
*/
-#ifndef __CROS_EC_CONFIG_CHIP_H
-#define __CROS_EC_CONFIG_CHIP_H
-
-#include "core/cortex-m/config_core.h"
-
-/* Interval between HOOK_TICK notifications */
-#define HOOK_TICK_INTERVAL_MS 500
-#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
-
-/* Default to UART 2 (AP UART) for EC console */
-#define CONFIG_UART_CONSOLE 2
-
-/* Number of IRQ vectors */
-#define CONFIG_IRQ_COUNT 56
-
-/*
- * Number of EINT can be 0 ~ 160. Change this to conditional macro
- * on adding other variants.
- */
-#define MAX_NUM_EINT 8
-#define MAX_EINT_PORT (MAX_NUM_EINT / 32)
-
-/* RW only, no flash */
-#undef CONFIG_FW_INCLUDE_RO
-#define CONFIG_RO_MEM_OFF 0
-#define CONFIG_RO_SIZE 0
-#define CONFIG_RW_MEM_OFF 0
-#define CONFIG_RW_SIZE 0x40000 /* 256KB */
-#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
-#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
-#define CONFIG_RO_STORAGE_OFF 0
-#define CONFIG_RW_STORAGE_OFF 0
-#define CONFIG_PROGRAM_MEMORY_BASE 0
-#define CONFIG_MAPPED_STORAGE_BASE 0
-/* Enable MPU to protect code RAM from writing, and data RAM from execution.*/
-#define CONFIG_MPU
-
-/* Unsupported features/commands */
-#undef CONFIG_CMD_FLASHINFO
-#undef CONFIG_CMD_POWER_AP
-#undef CONFIG_FLASH_CROS
-#undef CONFIG_FLASH_PHYSICAL
-#undef CONFIG_FMAP
-#undef CONFIG_HIBERNATE
-
-/* Task stack size */
-#define CONFIG_STACK_SIZE 1024
-#define IDLE_TASK_STACK_SIZE 256
-#define SMALLER_TASK_STACK_SIZE 384
-#define TASK_STACK_SIZE 512
-#define LARGER_TASK_STACK_SIZE 640
-#define VENTI_TASK_STACK_SIZE 768
-
-#define CONFIG_CHIP_PRE_INIT
-
-#define GPIO_PIN(num) ((num) / 32), ((num) % 32)
-#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
-
-#endif /* __CROS_EC_CONFIG_CHIP_H */
+#ifdef CHIP_VARIANT_MT8183
+#include "mt8183/config_chip.h"
+#endif
diff --git a/chip/mt_scp/audio_codec_wov.c b/chip/mt_scp/mt8183/audio_codec_wov.c
index 0a4684f909..0a4684f909 100644
--- a/chip/mt_scp/audio_codec_wov.c
+++ b/chip/mt_scp/mt8183/audio_codec_wov.c
diff --git a/chip/mt_scp/mt8183/build.mk b/chip/mt_scp/mt8183/build.mk
new file mode 100644
index 0000000000..206563a7c5
--- /dev/null
+++ b/chip/mt_scp/mt8183/build.mk
@@ -0,0 +1,35 @@
+# -*- makefile -*-
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+CORE:=cortex-m
+CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
+
+# Required chip modules
+chip-y+=$(CHIP_VARIANT)/clock.o
+chip-y+=$(CHIP_VARIANT)/gpio.o
+chip-y+=$(CHIP_VARIANT)/memmap.o
+chip-y+=$(CHIP_VARIANT)/system.o
+chip-y+=$(CHIP_VARIANT)/uart.o
+
+# Optional chip modules
+chip-$(CONFIG_AUDIO_CODEC_WOV)+=$(CHIP_VARIANT)/audio_codec_wov.o
+chip-$(CONFIG_COMMON_TIMER)+=$(CHIP_VARIANT)/hrtimer.o
+chip-$(CONFIG_I2C)+=$(CHIP_VARIANT)/i2c.o
+chip-$(CONFIG_IPI)+=$(CHIP_VARIANT)/ipi.o $(CHIP_VARIANT)/ipi_table.o
+chip-$(CONFIG_SPI)+=$(CHIP_VARIANT)/spi.o
+chip-$(CONFIG_WATCHDOG)+=$(CHIP_VARIANT)/watchdog.o
+
+ifeq ($(CONFIG_IPI),y)
+$(out)/RO/chip/$(CHIP)/$(CHIP_VARIANT)/ipi_table.o: $(out)/ipi_table_gen.inc
+$(out)/RW/chip/$(CHIP)/$(CHIP_VARIANT)/ipi_table.o: $(out)/ipi_table_gen.inc
+endif
+
+ifeq ($(CONFIG_AUDIO_CODEC_WOV),y)
+HOTWORD_PRIVATE_LIB:=private/libkukui_scp_google_hotword_dsp_api.a
+ifneq ($(wildcard $(HOTWORD_PRIVATE_LIB)),)
+LDFLAGS_EXTRA+=$(HOTWORD_PRIVATE_LIB)
+HAVE_PRIVATE_AUDIO_CODEC_WOV_LIBS:=y
+endif
+endif
diff --git a/chip/mt_scp/clock.c b/chip/mt_scp/mt8183/clock.c
index a6f1883d31..a6f1883d31 100644
--- a/chip/mt_scp/clock.c
+++ b/chip/mt_scp/mt8183/clock.c
diff --git a/chip/mt_scp/clock_chip.h b/chip/mt_scp/mt8183/clock_chip.h
index a16bf2e54e..a16bf2e54e 100644
--- a/chip/mt_scp/clock_chip.h
+++ b/chip/mt_scp/mt8183/clock_chip.h
diff --git a/chip/mt_scp/mt8183/config_chip.h b/chip/mt_scp/mt8183/config_chip.h
new file mode 100644
index 0000000000..e0710a908b
--- /dev/null
+++ b/chip/mt_scp/mt8183/config_chip.h
@@ -0,0 +1,64 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_CONFIG_CHIP_H
+#define __CROS_EC_CONFIG_CHIP_H
+
+#include "core/cortex-m/config_core.h"
+
+/* Interval between HOOK_TICK notifications */
+#define HOOK_TICK_INTERVAL_MS 500
+#define HOOK_TICK_INTERVAL (HOOK_TICK_INTERVAL_MS * MSEC)
+
+/* Default to UART 2 (AP UART) for EC console */
+#define CONFIG_UART_CONSOLE 2
+
+/* Number of IRQ vectors */
+#define CONFIG_IRQ_COUNT 56
+
+/*
+ * Number of EINT can be 0 ~ 160. Change this to conditional macro
+ * on adding other variants.
+ */
+#define MAX_NUM_EINT 8
+#define MAX_EINT_PORT (MAX_NUM_EINT / 32)
+
+/* RW only, no flash */
+#undef CONFIG_FW_INCLUDE_RO
+#define CONFIG_RO_MEM_OFF 0
+#define CONFIG_RO_SIZE 0
+#define CONFIG_RW_MEM_OFF 0
+#define CONFIG_RW_SIZE 0x40000 /* 256KB */
+#define CONFIG_EC_WRITABLE_STORAGE_OFF 0
+#define CONFIG_EC_PROTECTED_STORAGE_OFF 0
+#define CONFIG_RO_STORAGE_OFF 0
+#define CONFIG_RW_STORAGE_OFF 0
+#define CONFIG_PROGRAM_MEMORY_BASE 0
+#define CONFIG_MAPPED_STORAGE_BASE 0
+/* Enable MPU to protect code RAM from writing, and data RAM from execution.*/
+#define CONFIG_MPU
+
+/* Unsupported features/commands */
+#undef CONFIG_CMD_FLASHINFO
+#undef CONFIG_CMD_POWER_AP
+#undef CONFIG_FLASH_CROS
+#undef CONFIG_FLASH_PHYSICAL
+#undef CONFIG_FMAP
+#undef CONFIG_HIBERNATE
+
+/* Task stack size */
+#define CONFIG_STACK_SIZE 1024
+#define IDLE_TASK_STACK_SIZE 256
+#define SMALLER_TASK_STACK_SIZE 384
+#define TASK_STACK_SIZE 512
+#define LARGER_TASK_STACK_SIZE 640
+#define VENTI_TASK_STACK_SIZE 768
+
+#define CONFIG_CHIP_PRE_INIT
+
+#define GPIO_PIN(num) ((num) / 32), ((num) % 32)
+#define GPIO_PIN_MASK(p, m) .port = (p), .mask = (m)
+
+#endif /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/chip/mt_scp/gpio.c b/chip/mt_scp/mt8183/gpio.c
index a4896aae72..a4896aae72 100644
--- a/chip/mt_scp/gpio.c
+++ b/chip/mt_scp/mt8183/gpio.c
diff --git a/chip/mt_scp/hrtimer.c b/chip/mt_scp/mt8183/hrtimer.c
index f970af6eb5..f970af6eb5 100644
--- a/chip/mt_scp/hrtimer.c
+++ b/chip/mt_scp/mt8183/hrtimer.c
diff --git a/chip/mt_scp/ipi.c b/chip/mt_scp/mt8183/ipi.c
index db371f02b4..db371f02b4 100644
--- a/chip/mt_scp/ipi.c
+++ b/chip/mt_scp/mt8183/ipi.c
diff --git a/chip/mt_scp/ipi_chip.h b/chip/mt_scp/mt8183/ipi_chip.h
index 758047951f..758047951f 100644
--- a/chip/mt_scp/ipi_chip.h
+++ b/chip/mt_scp/mt8183/ipi_chip.h
diff --git a/chip/mt_scp/ipi_table.c b/chip/mt_scp/mt8183/ipi_table.c
index 8569ab24a7..8569ab24a7 100644
--- a/chip/mt_scp/ipi_table.c
+++ b/chip/mt_scp/mt8183/ipi_table.c
diff --git a/chip/mt_scp/memmap.c b/chip/mt_scp/mt8183/memmap.c
index 6d8f2b0c87..6d8f2b0c87 100644
--- a/chip/mt_scp/memmap.c
+++ b/chip/mt_scp/mt8183/memmap.c
diff --git a/chip/mt_scp/memmap.h b/chip/mt_scp/mt8183/memmap.h
index fbecb5e8cf..fbecb5e8cf 100644
--- a/chip/mt_scp/memmap.h
+++ b/chip/mt_scp/mt8183/memmap.h
diff --git a/chip/mt_scp/registers.h b/chip/mt_scp/mt8183/registers.h
index 21270b452d..21270b452d 100644
--- a/chip/mt_scp/registers.h
+++ b/chip/mt_scp/mt8183/registers.h
diff --git a/chip/mt_scp/serial_reg.h b/chip/mt_scp/mt8183/serial_reg.h
index 5344566272..5344566272 100644
--- a/chip/mt_scp/serial_reg.h
+++ b/chip/mt_scp/mt8183/serial_reg.h
diff --git a/chip/mt_scp/system.c b/chip/mt_scp/mt8183/system.c
index dc822e47d5..dc822e47d5 100644
--- a/chip/mt_scp/system.c
+++ b/chip/mt_scp/mt8183/system.c
diff --git a/chip/mt_scp/uart.c b/chip/mt_scp/mt8183/uart.c
index 78ea594c6b..78ea594c6b 100644
--- a/chip/mt_scp/uart.c
+++ b/chip/mt_scp/mt8183/uart.c
diff --git a/chip/mt_scp/watchdog.c b/chip/mt_scp/mt8183/watchdog.c
index 74e2cad8e5..74e2cad8e5 100644
--- a/chip/mt_scp/watchdog.c
+++ b/chip/mt_scp/mt8183/watchdog.c