chip/ish: replace CONFIG_ISH_xx flags with CHIP_FAMILY and CHIP_VARIANT

Replace all CONFIG_ISH_xx flags in chip/ish/* files with CHIP_FAMILY and
CHIP_VARIANT. Which provides more structural defines between ISH generations.

BRANCH=none
BUG=b:120295222 b:112385410
TEST=Test host FW loading for main ISH FW.

Change-Id: Ica92eee11034447c9f0828aa986fb1736d20cf27
Signed-off-by: Shine Liu <shine.liu@intel.com>
Signed-off-by: li feng <li1.feng@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/1367010
Commit-Ready: Caveh Jalali <caveh@google.com>
Tested-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>

4 files changed, 17 insertions, 19 deletions

diff --git a/chip/ish/gpio.c b/chip/ish/gpio.c
index ce27165d57..ca0f8250c0 100644
--- a/chip/ish/gpio.c
+++ b/chip/ish/gpio.c
@@ -45,7 +45,7 @@ void gpio_set_flags_by_mask(uint32_t port, uint32_t mask, uint32_t flags)
 		ISH_GPIO_GPDR &= ~mask;
 
 	/* GRER/GFER interrupt trigger */
-#ifdef CONFIG_ISH_30
+#ifdef CHIP_FAMILY_ISH3
 	/* ISH 3 can't support both rising and falling edge */
 	if (((flags & GPIO_INT_F_RISING) && (flags & GPIO_INT_F_FALLING)) ||
 		((flags & GPIO_INT_F_HIGH) && (flags & GPIO_INT_F_LOW))) {
diff --git a/chip/ish/hpet.h b/chip/ish/hpet.h
index 0ad374350e..0f30bfda41 100644
--- a/chip/ish/hpet.h
+++ b/chip/ish/hpet.h
@@ -45,7 +45,7 @@
 #define HPET_Tn_INT_ROUTE_CNF_MASK	(0x1f << 9)
 
 #define HPET_GENERAL_CONFIG	REG32(ISH_HPET_BASE + GENERAL_CONFIG_REG)
-#if defined CONFIG_ISH_30
+#ifdef CHIP_FAMILY_ISH3
 #define HPET_MAIN_COUNTER_64	REG64(ISH_HPET_BASE + MAIN_COUNTER_REG)
 #else
 #define HPET_MAIN_COUNTER	REG32(ISH_HPET_BASE + MAIN_COUNTER_REG)
@@ -59,19 +59,17 @@
  * HPET_TIMER_CONFIG_CAP(0) */
 #define HPET_TIMER_COMP(x) \
 	REG32(ISH_HPET_BASE + TIMER0_COMP_VAL_REG + ((x) * 0x20))
-#if defined CONFIG_ISH_30
+#ifdef CHIP_FAMILY_ISH3
 #define HPET_TIMER_COMP_64(x) \
 	REG64(ISH_HPET_BASE + TIMER0_COMP_VAL_REG + ((x) * 0x20))
 #endif
 
-#if defined CONFIG_ISH_20
-#define ISH_HPET_CLK_FREQ		1000000		/* 1 MHz clock */
-
-#elif defined CONFIG_ISH_30
+#if defined(CHIP_FAMILY_ISH3)
 #define ISH_HPET_CLK_FREQ		12000000	/* 12 MHz clock */
-
-#elif defined CONFIG_ISH_40
+#elif defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5)
 #define ISH_HPET_CLK_FREQ		32768		/* 32.768 KHz clock */
+#else
+#define ISH_HPET_CLK_FREQ               1000000         /* 1 MHz clock */
 #endif
 
 /* HPET timer 0 period of 10ms (100 ticks per second) */
diff --git a/chip/ish/hwtimer.c b/chip/ish/hwtimer.c
index 1ba08f048f..960a4218ff 100644
--- a/chip/ish/hwtimer.c
+++ b/chip/ish/hwtimer.c
@@ -12,7 +12,7 @@
 #include "task.h"
 #include "util.h"
 
-#ifdef CONFIG_ISH_30
+#if defined(CHIP_FAMILY_ISH3)
 #define CLOCK_FACTOR 12
 #endif
 
@@ -31,7 +31,7 @@ static uint32_t last_deadline;
 void __hw_clock_event_set(uint32_t deadline)
 {
 	last_deadline = deadline;
-#ifdef CONFIG_ISH_30
+#if defined(CHIP_FAMILY_ISH3)
 	HPET_TIMER_COMP(1) = deadline * CLOCK_FACTOR;
 #else
 	HPET_TIMER_COMP(1) = deadline;
@@ -51,7 +51,7 @@ void __hw_clock_event_clear(void)
 
 uint32_t __hw_clock_source_read(void)
 {
-#ifdef CONFIG_ISH_30
+#if defined(CHIP_FAMILY_ISH3)
 	uint64_t tmp = HPET_MAIN_COUNTER_64;
 	uint32_t hi = tmp >> 32;
 	uint32_t lo = tmp;
@@ -67,7 +67,7 @@ uint32_t __hw_clock_source_read(void)
 void __hw_clock_source_set(uint32_t ts)
 {
 	HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
-#ifdef CONFIG_ISH_30
+#if defined(CHIP_FAMILY_ISH3)
 	HPET_MAIN_COUNTER_64 = (uint64_t)ts * CLOCK_FACTOR;
 #else
 	HPET_MAIN_COUNTER = ts;
@@ -111,13 +111,13 @@ int __hw_clock_source_init(uint32_t start_t)
 
 	/* Disable HPET */
 	HPET_GENERAL_CONFIG &= ~HPET_ENABLE_CNF;
-#ifdef CONFIG_ISH_30
+#if defined(CHIP_FAMILY_ISH3)
 	HPET_MAIN_COUNTER_64 = (uint64_t)start_t * CLOCK_FACTOR;
 #else
 	HPET_MAIN_COUNTER = start_t;
 #endif
 
-#ifdef CONFIG_ISH_30
+#if defined(CHIP_FAMILY_ISH3)
 	/*
 	 * Set comparator value. HMC will operate in 64 bit mode.
 	 * HMC is 12MHz, Hence set COMP to 12x of 1MHz.
@@ -129,7 +129,7 @@ int __hw_clock_source_init(uint32_t start_t)
 #endif
 	/* Timer 0 - enable periodic mode */
 	timer0_config |= HPET_Tn_TYPE_CNF;
-#ifdef CONFIG_ISH_30
+#if defined(CHIP_FAMILY_ISH3)
 	/* TIMER0 in 64-bit mode */
 	timer0_config &= ~HPET_Tn_32MODE_CNF;
 #else
@@ -162,7 +162,7 @@ int __hw_clock_source_init(uint32_t start_t)
 	HPET_TIMER_CONF_CAP(0) |= timer0_config;
 	HPET_TIMER_CONF_CAP(1) |= timer1_config;
 
-#ifdef CONFIG_ISH_40
+#if defined(CHIP_FAMILY_ISH4) || defined(CHIP_FAMILY_ISH5)
 	/* Wait for timer to settle. required for ISH 4 */
 	while (HPET_CTRL_STATUS & HPET_T_CONF_CAP_BIT)
 		;
diff --git a/chip/ish/uart_defs.h b/chip/ish/uart_defs.h
index 9890faeb7c..ba682ccc50 100644
--- a/chip/ish/uart_defs.h
+++ b/chip/ish/uart_defs.h
@@ -185,9 +185,9 @@
 /* KHZ, MHZ */
 #define KHZ(x)				((x) * 1000)
 #define MHZ(x)				(KHZ(x) * 1000)
-#if (defined CONFIG_ISH_30 || defined CONFIG_ISH_20)
+#if defined(CHIP_FAMILY_ISH3) || defined(CHIP_FAMILY_ISH5)
 #define UART_ISH_INPUT_FREQ		MHZ(120)
-#elif defined CONFIG_ISH_40
+#elif defined(CHIP_FAMILY_ISH4)
 #define UART_ISH_INPUT_FREQ		MHZ(100)
 #endif
 #define UART_DEFAULT_BAUD_RATE		115200