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authorRong Chang <rongchang@chromium.org>2018-09-05 16:47:42 -0400
committerchrome-bot <chrome-bot@chromium.org>2018-12-20 13:49:39 -0800
commit7bc69df9cdedd661389a3505dba7e377cb3e1e2f (patch)
tree1246d2fbfebed9126e398cad6e864e489140a68a
parentb437f03578e7e19a0ff369fe7ac574ab4414d588 (diff)
downloadchrome-ec-7bc69df9cdedd661389a3505dba7e377cb3e1e2f.tar.gz
kukui: Add initial kukui_scp board for SCP development
Kukui is the first project with Chromium OS EC based SCP. This is an base board to develop SCP functionalities. BRANCH=none BUG=b:114326670 TEST=manual make BOARD=kukui_scp -j Change-Id: I65897d5439e88cebdc6543e5a8e07cd5657303e7 Signed-off-by: Rong Chang <rongchang@chromium.org> Signed-off-by: Yilun Lin <yllin@google.com> Reviewed-on: https://chromium-review.googlesource.com/1208772 Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com> Tested-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Yilun Lin <yllin@chromium.org> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
-rw-r--r--board/kukui_scp/board.c35
-rw-r--r--board/kukui_scp/board.h41
-rw-r--r--board/kukui_scp/build.mk11
-rw-r--r--board/kukui_scp/ec.tasklist31
-rw-r--r--board/kukui_scp/gpio.inc36
-rw-r--r--chip/mt_scp/uart.c4
6 files changed, 156 insertions, 2 deletions
diff --git a/board/kukui_scp/board.c b/board/kukui_scp/board.c
new file mode 100644
index 0000000000..955f5e8595
--- /dev/null
+++ b/board/kukui_scp/board.c
@@ -0,0 +1,35 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+/* Kukui SCP configuration */
+
+#include "common.h"
+#include "console.h"
+#include "ec_version.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "task.h"
+#include "timer.h"
+#include "util.h"
+
+/* Build GPIO tables */
+void eint_event(enum gpio_signal signal);
+
+#include "gpio_list.h"
+
+
+void eint_event(enum gpio_signal signal)
+{
+ ccprintf("EINT event: %d\n", signal);
+}
+
+/* Initialize board. */
+static void board_init(void)
+{
+ gpio_enable_interrupt(GPIO_EINT5_TP);
+ gpio_enable_interrupt(GPIO_EINT6_TP);
+ gpio_enable_interrupt(GPIO_EINT7_TP);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/kukui_scp/board.h b/board/kukui_scp/board.h
new file mode 100644
index 0000000000..db456f9d9b
--- /dev/null
+++ b/board/kukui_scp/board.h
@@ -0,0 +1,41 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Kukui SCP configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+#define CONFIG_FLASH_SIZE 0x40000 /* Image file size: 256KB */
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_FW_INCLUDE_RO
+
+#undef CONFIG_UART_CONSOLE
+/*
+ * CONFIG_UART_CONSOLE
+ * 0 - SCP UART0
+ * 1 - SCP UART1
+ * 2 - share with AP UART0
+ */
+#define CONFIG_UART_CONSOLE 0
+#define UART0_PINMUX_11_12
+#undef UART0_PINMUX_110_112
+
+/*
+ * Allow dangerous commands all the time, since we don't have a write protect
+ * switch.
+ */
+#define CONFIG_SYSTEM_UNLOCKED
+/* Debugging features */
+#define CONFIG_DEBUG_EXCEPTIONS
+#define CONFIG_DEBUG_STACK_OVERFLOW
+#define CONFIG_CMD_GPIO_EXTENDED
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+
+#endif /* !__ASSEMBLER__ */
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/kukui_scp/build.mk b/board/kukui_scp/build.mk
new file mode 100644
index 0000000000..64262dfecc
--- /dev/null
+++ b/board/kukui_scp/build.mk
@@ -0,0 +1,11 @@
+# -*- makefile -*-
+# Copyright 2018 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+CHIP:=mt_scp
+CHIP_VARIANT:=mt8183
+
+board-y=board.o
diff --git a/board/kukui_scp/ec.tasklist b/board/kukui_scp/ec.tasklist
new file mode 100644
index 0000000000..e38dd10eb2
--- /dev/null
+++ b/board/kukui_scp/ec.tasklist
@@ -0,0 +1,31 @@
+/* Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * List of enabled tasks in the priority order
+ *
+ * The first one has the lowest priority.
+ *
+ * For each task, use the macro TASK_ALWAYS(n, r, d, s) for base tasks and
+ * TASK_NOTEST(n, r, d, s) for tasks that can be excluded in test binaries,
+ * where :
+ * 'n' is the name of the task
+ * 'r' is the main routine of the task
+ * 'd' is an opaque parameter passed to the routine at startup
+ * 's' is the stack size in bytes; must be a multiple of 8
+ */
+
+/* We don't need uart_task when using scp uart (uart0, uart1). */
+#if CONFIG_UART_CONSOLE == 2
+#define UART_TASK TASK_ALWAYS(APUART, uart_task, NULL, LARGER_TASK_STACK_SIZE)
+#else
+#define UART_TASK
+#endif
+
+#define CONFIG_TASK_LIST \
+ TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+ UART_TASK \
+ TASK_ALWAYS(CONSOLE, console_task, NULL, LARGER_TASK_STACK_SIZE)
+
diff --git a/board/kukui_scp/gpio.inc b/board/kukui_scp/gpio.inc
new file mode 100644
index 0000000000..b2ff55f0a0
--- /dev/null
+++ b/board/kukui_scp/gpio.inc
@@ -0,0 +1,36 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2018 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+GPIO_INT(EINT5_TP, PIN(5), GPIO_INT_FALLING, eint_event)
+GPIO_INT(EINT6_TP, PIN(6), GPIO_INT_FALLING, eint_event)
+GPIO_INT(EINT7_TP, PIN(7), GPIO_INT_FALLING, eint_event)
+
+/* Unimplemented signals which we need to emulate for now */
+UNIMPLEMENTED(ENTERING_RW)
+UNIMPLEMENTED(WP_L)
+
+/*
+ * GPIOn = port * 32 + bit
+ *
+ * EINT ALT function:
+ * GPIO[0-3]: Alt3
+ * GPIO[4-7]: Alt6
+ * UART0 ALT function:
+ * GPIO[110]: Alt3 TP_URXD1_AO
+ * GPIO[112]: Alt3 TP_UTXD1_AO
+ */
+ALTERNATE(PIN_MASK(0, 0x00000070), 6, MODULE_GPIO, 0) /* GPIO 5,6,7 as SCP EINT */
+#if CONFIG_UART_CONSOLE == 0
+#ifdef UART0_PINMUX_110_112
+/* Use SCP debug UART. */
+ALTERNATE(PIN_MASK(3, 0x00014000), 3, MODULE_UART, 0) /* GPIO 110,112 as UART0 */
+#endif /* UART0_PINMUX_110_112 */
+#ifdef UART0_PINMUX_11_12
+/* Use H1(AP->H1) rework UART. */
+ALTERNATE(PIN_MASK(0, 0x00001800), 1, MODULE_UART, 0) /* GPIO 11,12 as UART0 */
+#endif /* UART0_PINMUX_11_12 */
+#endif /* CONFIG_UART_CONSOLE == 0 */
diff --git a/chip/mt_scp/uart.c b/chip/mt_scp/uart.c
index 554a53cc1d..73a284319c 100644
--- a/chip/mt_scp/uart.c
+++ b/chip/mt_scp/uart.c
@@ -58,7 +58,7 @@ void uart_tx_stop(void)
void uart_tx_flush(void)
{
while (!(UART_LSR(UARTN) & UART_LSR_TEMT))
- usleep(uart_wait_us);
+ usleep(UART_WAIT_US);
}
int uart_tx_ready(void)
@@ -76,7 +76,7 @@ int uart_rx_available(void)
void uart_write_char(char c)
{
while (!uart_tx_ready())
- usleep(uart_wait_us);
+ usleep(UART_WAIT_US);
UART_DATA(UARTN) = c;
}