diff options
author | Mulin Chao <mlchao@nuvoton.com> | 2021-03-31 22:57:59 -0700 |
---|---|---|
committer | Commit Bot <commit-bot@chromium.org> | 2021-04-08 00:21:01 +0000 |
commit | 51cf9f6619f2979a43e7ef5c6e9824b4bd715966 (patch) | |
tree | b2a31bad982768e24bbb587158215a7e24e85a52 | |
parent | 3f8889741a207e54d1f111bbcd73a9f7efd8c7f8 (diff) | |
download | chrome-ec-51cf9f6619f2979a43e7ef5c6e9824b4bd715966.tar.gz |
zephyr: npcx: Add cros_system chip info implementation
Add NPCX chip_vendor(), chip_name(), and chip_revision implementation
for cros_system driver.
BUG=none
BRANCH=none
TEST=Build & boot ec on volteer.
TEST=Press 'version' in console and show related chip information:
```
21-04-06 17:53:00.681 uart:~$ version
21-04-06 17:53:01.795 Chip: Nuvoton NPCX796FC 02
21-04-06 17:53:01.795 Board: 2
21-04-06 17:53:01.795 RO: _v2.0.8287+db38ffd6d
21-04-06 17:53:01.795 RW: _v2.0.8287+db38ffd6d
21-04-06 17:53:01.795 Build: _v2.0.8287+db38ffd6d
```
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Signed-off-by: Wealian Liao <whliao@nuvoton.corp-partner.google.com>
Change-Id: I73d016f5fa1da6c03e38b312eb4f1b0445a2c1d4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2807479
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Keith Short <keithshort@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Commit-Queue: Jack Rosenthal <jrosenth@chromium.org>
-rw-r--r-- | zephyr/drivers/cros_system/cros_system_npcx.c | 87 | ||||
-rw-r--r-- | zephyr/shim/chip/npcx/include/rom_chip.h | 3 |
2 files changed, 90 insertions, 0 deletions
diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c index 5b1c70fe1e..82d95427af 100644 --- a/zephyr/drivers/cros_system/cros_system_npcx.c +++ b/zephyr/drivers/cros_system/cros_system_npcx.c @@ -7,6 +7,7 @@ #include <drivers/watchdog.h> #include <logging/log.h> #include <soc.h> +#include "rom_chip.h" LOG_MODULE_REGISTER(cros_system, LOG_LEVEL_ERR); @@ -15,6 +16,7 @@ struct cros_system_npcx_config { /* hardware module base address */ uintptr_t base_scfg; uintptr_t base_twd; + uintptr_t base_mswc; }; /* Driver data */ @@ -27,9 +29,22 @@ struct cros_system_npcx_data { #define HAL_SCFG_INST(dev) (struct scfg_reg *)(DRV_CONFIG(dev)->base_scfg) #define HAL_TWD_INST(dev) (struct twd_reg *)(DRV_CONFIG(dev)->base_twd) +#define HAL_MSWC_INST(dev) (struct mswc_reg *)(DRV_CONFIG(dev)->base_mswc) #define DRV_DATA(dev) ((struct cros_system_npcx_data *)(dev)->data) +#define FAMILY_ID_NPCX 0x20 +#define CHIP_ID_NPCX79NXB_C 0x07 + +/* device ID for all variants in npcx family */ +enum npcx_chip_id { + DEVICE_ID_NPCX796F_B = 0x21, + DEVICE_ID_NPCX796F_C = 0x29, + DEVICE_ID_NPCX797F_C = 0x20, + DEVICE_ID_NPCX797W_B = 0x24, + DEVICE_ID_NPCX797W_C = 0x2C, +}; + /* * For cortex-m we cannot use irq_lock() for disabling all the interrupts * because it leaves some (NMI and faults) still enabled. Use "cpsid i" to @@ -40,6 +55,73 @@ static inline void interrupt_disable_all(void) __asm__("cpsid i"); } +static const char *cros_system_npcx_get_chip_vendor(const struct device *dev) +{ + struct mswc_reg *const inst_mswc = HAL_MSWC_INST(dev); + static char str[11] = "Unknown-XX"; + char *p = str + 8; + uint8_t fam_id = inst_mswc->SID_CR; + + if (fam_id == FAMILY_ID_NPCX) { + return "Nuvoton"; + } + + hex2char(fam_id >> 4, p++); + hex2char(fam_id & 0xf, p); + return str; +} + +static const char *cros_system_npcx_get_chip_name(const struct device *dev) +{ + struct mswc_reg *const inst_mswc = HAL_MSWC_INST(dev); + static char str[13] = "Unknown-XXXX"; + char *p = str + 8; + uint8_t chip_id = inst_mswc->SRID_CR; + uint8_t device_id = inst_mswc->DEVICE_ID_CR; + + if (chip_id == CHIP_ID_NPCX79NXB_C) { + switch (device_id) { + case DEVICE_ID_NPCX796F_B: + return "NPCX796FB"; + case DEVICE_ID_NPCX796F_C: + return "NPCX796FC"; + case DEVICE_ID_NPCX797F_C: + return "NPCX797FC"; + case DEVICE_ID_NPCX797W_B: + return "NPCX797WB"; + case DEVICE_ID_NPCX797W_C: + return "NPCX797WC"; + } + } + + hex2char(chip_id >> 4, p++); + hex2char(chip_id & 0xf, p++); + hex2char(device_id >> 4, p++); + hex2char(device_id & 0xf, p); + return str; +} + +static const char *cros_system_npcx_get_chip_revision(const struct device *dev) +{ + ARG_UNUSED(dev); + static char rev[NPCX_CHIP_REV_STR_SIZE]; + char *p = rev; + uint8_t rev_num = *((volatile uint8_t *)NPCX_CHIP_REV_ADDR); + + /* + * For NPCX7, the revision number is 1 byte. + * For NPCX9 and later chips, the revision number is 4 bytes. + */ + for (int s = sizeof(rev_num) - 1; s >= 0; s--) { + uint8_t r = rev_num >> (s * 8); + hex2char(r >> 4, p++); + hex2char(r & 0xf, p++); + } + *p = '\0'; + + return rev; +} + static int cros_system_npcx_get_reset_cause(const struct device *dev) { struct cros_system_npcx_data *data = DRV_DATA(dev); @@ -152,12 +234,17 @@ static struct cros_system_npcx_data cros_system_npcx_dev_data; static const struct cros_system_npcx_config cros_system_dev_cfg = { .base_scfg = DT_REG_ADDR(DT_INST(0, nuvoton_npcx_scfg)), .base_twd = DT_REG_ADDR(DT_INST(0, nuvoton_npcx_watchdog)), + .base_mswc = + DT_REG_ADDR_BY_NAME(DT_INST(0, nuvoton_npcx_host_sub), mswc), }; static const struct cros_system_driver_api cros_system_driver_npcx_api = { .get_reset_cause = cros_system_npcx_get_reset_cause, .soc_reset = cros_system_npcx_soc_reset, .hibernate = cros_system_npcx_hibernate, + .chip_vendor = cros_system_npcx_get_chip_vendor, + .chip_name = cros_system_npcx_get_chip_name, + .chip_revision = cros_system_npcx_get_chip_revision, }; /* diff --git a/zephyr/shim/chip/npcx/include/rom_chip.h b/zephyr/shim/chip/npcx/include/rom_chip.h index aab166e6f1..00b4c0b080 100644 --- a/zephyr/shim/chip/npcx/include/rom_chip.h +++ b/zephyr/shim/chip/npcx/include/rom_chip.h @@ -54,4 +54,7 @@ typedef void (*download_from_flash_ptr) ( enum API_RETURN_STATUS_T *status /* Status fo download */ ); +#define NPCX_CHIP_REV_ADDR 0x00007FFC +#define NPCX_CHIP_REV_STR_SIZE 3 + #endif /* __CROS_EC_ROM_CHIP_H */ |