mt_scp: Move ROM_BASE to 0x0.

Removes stepping_stone regions, and move ROM_BASE from 0x800 to 0x0.

stepping_stone region is to smooth SCP's bringing up stage for
being compatible with both original and new implementation.
Now that we have done the kernel side driver implementation,
we can earn more SRAM space by removing the stepping_stone.

TEST=run SCP on kukui, and see it boots.
BRANCH=None
BUG=b:120825336

Change-Id: I253904592fa0187f627b2eaa3f5d12a17db9960f
Signed-off-by: Yilun Lin <yllin@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1563871
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Tested-by: Yilun Lin <yllin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>

5 files changed, 2 insertions, 29 deletions

diff --git a/board/kukui_scp/board.h b/board/kukui_scp/board.h
index 85dbd49c66..ccde774faa 100644
--- a/board/kukui_scp/board.h
+++ b/board/kukui_scp/board.h
@@ -18,9 +18,6 @@
 /*
  * RW only, no flash
  * +-------------------- 0x0
- * | ptr to stack_top  0x0
- * | ptr to reset func 0x04
- * +-------------------- 0x00800
  * | ROM vectortable, .text, .rodata, .data LMA
  * +-------------------- 0x10000
  * | RAM .bss, .data
@@ -33,7 +30,7 @@
  * +-------------------- 0x80000
  */
 #define ICACHE_BASE 0x7C000
-#define CONFIG_ROM_BASE 0x00800
+#define CONFIG_ROM_BASE 0x0
 #define CONFIG_RAM_BASE 0x10000
 #define CONFIG_ROM_SIZE (CONFIG_RAM_BASE - CONFIG_ROM_BASE)
 #define CONFIG_RAM_SIZE (CONFIG_IPC_SHARED_OBJ_ADDR - CONFIG_RAM_BASE)
diff --git a/chip/mt_scp/build.mk b/chip/mt_scp/build.mk
index 03937f8591..af1ba08170 100644
--- a/chip/mt_scp/build.mk
+++ b/chip/mt_scp/build.mk
@@ -10,7 +10,7 @@ CORE:=cortex-m
 CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
 
 # Required chip modules
-chip-y=clock.o gpio.o memmap.o stepping_stone.o system.o uart.o
+chip-y=clock.o gpio.o memmap.o system.o uart.o
 
 # Optional chip modules
 chip-$(CONFIG_COMMON_TIMER)+=hrtimer.o
diff --git a/chip/mt_scp/config_chip.h b/chip/mt_scp/config_chip.h
index 91ee880985..d2e6ca3b9d 100644
--- a/chip/mt_scp/config_chip.h
+++ b/chip/mt_scp/config_chip.h
@@ -37,7 +37,6 @@
 #define CONFIG_RW_STORAGE_OFF 0
 #define CONFIG_PROGRAM_MEMORY_BASE 0
 #define CONFIG_MAPPED_STORAGE_BASE 0
-#define CONFIG_CHIP_MEMORY_REGIONS
 
 /* Unsupported features/commands */
 #undef CONFIG_CMD_FLASHINFO
diff --git a/chip/mt_scp/memory_regions.inc b/chip/mt_scp/memory_regions.inc
deleted file mode 100644
index e87df4c51d..0000000000
--- a/chip/mt_scp/memory_regions.inc
+++ /dev/null
@@ -1 +0,0 @@
-REGION_LOAD(stepping_stone, rwx, 0x00000, 0x8)
diff --git a/chip/mt_scp/stepping_stone.c b/chip/mt_scp/stepping_stone.c
deleted file mode 100644
index 0e880b1924..0000000000
--- a/chip/mt_scp/stepping_stone.c
+++ /dev/null
@@ -1,22 +0,0 @@
-/* Copyright 2018 The Chromium OS Authors. All rights reserved.
- * Use of this source code is governed by a BSD-style license that can be
- * found in the LICENSE file.
- *
- * mt_scp Stepping Stone functions on CPU reset.
- *
- * SCP assumes vector table at CONFIG_RAM_BASE. However, on cortex-m resetting,
- * it would load 0x0 to SP(r13) and load 0x04 to PC(r15).  Stepping stones copy
- * these two very special values from CONFIG_RAM_BASE, CONFIG_RAM_BASE + 0x04
- * to 0x0, 0x4 resepctively.
- */
-
-#include "common.h"
-#include "link_defs.h"
-
-extern void stack_end(void); /* not technically correct, it's just a pointer */
-extern void reset(void);
-
-__SECTION_KEEP(stepping_stone) const void *ss_header[2] = {
-	&stack_end,
-	&reset
-};