stm32: Re-enable spi transfers after a sysjump

If we sysjump to EC-RW, that sets enabled=0.  enabled is only set back
to 1 when the chipset resumes.  But on an AP-requested sysjump, the
chipset is already on, and so the resume hook never gets called.

So, in spi init, check if the AP is already on.  If it is, enable spi
transfers right away.

This probably also affects Pit/Pi.  That may need an additional fix in
power/gaia.c, if it returns an incorrect chipset state after a sysjump
(I didn't test that.)

BUG=chrome-os-partner:28249
BRANCH=nyan,pit
TEST=Power+Refresh boot system with RONormal disabled, so that the AP
     tells the EC to jump to EC-RW.  Confirm EC communication still works
     after that.

Change-Id: I588ef6d841040cf05d5527f645f122d5708b16ad
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/198869
Reviewed-by: Yung-chieh Lo <yjlou@chromium.org>
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Commit-Queue: Yung-chieh Lo <yjlou@chromium.org>
Tested-by: Yung-chieh Lo <yjlou@chromium.org>
Tested-by: Gabe Black <gabeblack@chromium.org>

1 files changed, 25 insertions, 20 deletions

diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c
index 8e2fc6fa90..c9e57cd5b2 100644
--- a/chip/stm32/spi.c
+++ b/chip/stm32/spi.c
@@ -8,6 +8,7 @@
  * This uses DMA to handle transmission and reception.
  */
 
+#include "chipset.h"
 #include "console.h"
 #include "dma.h"
 #include "gpio.h"
@@ -454,26 +455,6 @@ void spi_event(enum gpio_signal signal)
 	CPRINTF("[%T SPI rx bad data\n]");
 }
 
-static void spi_init(void)
-{
-	stm32_spi_regs_t *spi = STM32_SPI1_REGS;
-
-	/* 40 MHz pin speed */
-	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xff00;
-
-	/* Enable clocks to SPI1 module */
-	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
-
-	/* Enable rx DMA and get ready to receive our first transaction */
-	spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN;
-
-	/* Enable the SPI peripheral */
-	spi->cr1 |= STM32_SPI_CR1_SPE;
-
-	gpio_enable_interrupt(GPIO_SPI1_NSS);
-}
-DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_DEFAULT);
-
 static void spi_chipset_startup(void)
 {
 	/* Enable pullup and interrupts on NSS */
@@ -504,6 +485,30 @@ static void spi_chipset_shutdown(void)
 DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, spi_chipset_shutdown, HOOK_PRIO_DEFAULT);
 DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, spi_chipset_shutdown, HOOK_PRIO_DEFAULT);
 
+static void spi_init(void)
+{
+	stm32_spi_regs_t *spi = STM32_SPI1_REGS;
+
+	/* 40 MHz pin speed */
+	STM32_GPIO_OSPEEDR(GPIO_A) |= 0xff00;
+
+	/* Enable clocks to SPI1 module */
+	STM32_RCC_APB2ENR |= STM32_RCC_PB2_SPI1;
+
+	/* Enable rx DMA and get ready to receive our first transaction */
+	spi->cr2 = STM32_SPI_CR2_RXDMAEN | STM32_SPI_CR2_TXDMAEN;
+
+	/* Enable the SPI peripheral */
+	spi->cr1 |= STM32_SPI_CR1_SPE;
+
+	gpio_enable_interrupt(GPIO_SPI1_NSS);
+
+	/* If chipset is already on, prepare for transactions */
+	if (chipset_in_state(CHIPSET_STATE_ON))
+		spi_chipset_startup();
+}
+DECLARE_HOOK(HOOK_INIT, spi_init, HOOK_PRIO_DEFAULT);
+
 /**
  * Get protocol information
  */