ish: snowball linker cleanup

Change AON_ROM references to be AON_PERSISTENT, these are not readonly

Use the linker to set a snowball structure in the right place so we do
not have to maintain hardcoded addresses in the register file

BUG=b:132690500
BRANCH=none
TEST=make buildall -j and check map location of snowball to be correct

Change-Id: I4983a078fbd067b9c7ec9f0c49f962a4cb1581b7
Signed-off-by: Denis Brockus <dbrockus@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1664593
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>

7 files changed, 53 insertions, 36 deletions

diff --git a/chip/ish/aontaskfw/ish_aontask.c b/chip/ish/aontaskfw/ish_aontask.c
index 996827e8c9..bc8b2f6084 100644
--- a/chip/ish/aontaskfw/ish_aontask.c
+++ b/chip/ish/aontaskfw/ish_aontask.c
@@ -167,7 +167,7 @@ void ish_aon_main(void);
 static struct tss_entry aon_tss = {
 	.prev_task_link = 0,
 	.reserved1 = 0,
-	.esp0 = (uint8_t *)(CONFIG_AON_ROM_BASE - AON_SP_RESERVED),
+	.esp0 = (uint8_t *)(CONFIG_AON_PERSISTENT_BASE - AON_SP_RESERVED),
 	/* entry 1 in LDT for data segment */
 	.ss0 = 0xc,
 	.reserved2 = 0,
@@ -186,8 +186,8 @@ static struct tss_entry aon_tss = {
 	.edx = 0,
 	.ebx = 0,
 	/* set stack top pointer at the end of usable aon memory */
-	.esp = CONFIG_AON_ROM_BASE - AON_SP_RESERVED,
-	.ebp = CONFIG_AON_ROM_BASE - AON_SP_RESERVED,
+	.esp = CONFIG_AON_PERSISTENT_BASE - AON_SP_RESERVED,
+	.ebp = CONFIG_AON_PERSISTENT_BASE - AON_SP_RESERVED,
 	.esi = 0,
 	.edi = 0,
 	/* entry 1 in LDT for data segment */
@@ -269,6 +269,10 @@ struct ish_aon_share aon_share = {
 	.aon_ldt_size = sizeof(aon_ldt),
 };
 
+/* snowball structure */
+__attribute__((section(".data.snowball"))) volatile
+struct snowball_struct snowball;
+
 /* In IMR DDR, ISH FW image has a manifest header */
 #define ISH_FW_IMAGE_MANIFEST_HEADER_SIZE (0x1000)
 
@@ -285,10 +289,10 @@ static int store_main_fw(void)
 	uint64_t imr_fw_addr;
 	uint64_t imr_fw_rw_addr;
 
-	imr_fw_addr = ((uint64_t)SNOWBALL_UMA_BASE_HI << 32) +
-			SNOWBALL_UMA_BASE_LO +
-			SNOWBALL_FW_OFFSET +
-			ISH_FW_IMAGE_MANIFEST_HEADER_SIZE;
+	imr_fw_addr = (((uint64_t)snowball.uma_base_hi << 32) +
+		       snowball.uma_base_lo +
+		       snowball.fw_offset +
+		       ISH_FW_IMAGE_MANIFEST_HEADER_SIZE);
 
 	imr_fw_rw_addr = (imr_fw_addr
 			  + aon_share.main_fw_rw_addr
@@ -326,10 +330,10 @@ static int restore_main_fw(void)
 	uint64_t imr_fw_ro_addr;
 	uint64_t imr_fw_rw_addr;
 
-	imr_fw_addr = ((uint64_t)SNOWBALL_UMA_BASE_HI << 32) +
-			SNOWBALL_UMA_BASE_LO +
-			SNOWBALL_FW_OFFSET +
-			ISH_FW_IMAGE_MANIFEST_HEADER_SIZE;
+	imr_fw_addr = (((uint64_t)snowball.uma_base_hi << 32) +
+			snowball.uma_base_lo +
+			snowball.fw_offset +
+		       ISH_FW_IMAGE_MANIFEST_HEADER_SIZE);
 
 	imr_fw_ro_addr = (imr_fw_addr
 			  + aon_share.main_fw_ro_addr
diff --git a/chip/ish/aontaskfw/ish_aontask.ld.in b/chip/ish/aontaskfw/ish_aontask.ld.in
index a839146a92..b5361432a2 100644
--- a/chip/ish/aontaskfw/ish_aontask.ld.in
+++ b/chip/ish/aontaskfw/ish_aontask.ld.in
@@ -7,8 +7,8 @@
 
 ENTRY(ish_aon_main);
 
-#define SRAM_START		CONFIG_AON_RAM_BASE
-#define SRAM_RW_LEN		(CONFIG_AON_RAM_SIZE - CONFIG_AON_ROM_SIZE)
+#define SRAM_START	CONFIG_AON_RAM_BASE
+#define SRAM_RW_LEN	(CONFIG_AON_RAM_SIZE - CONFIG_AON_PERSISTENT_SIZE)
 
 /* reserved stack size */
 #define STACK_SIZE  (256)
@@ -32,10 +32,23 @@ ENTRY(ish_aon_main);
  * loader.
  */
 
+/**
+ * Snowball data
+ */
+#if defined(CHIP_FAMILY_ISH3)
+/* on ISH3, reused ISH2PMC IPC message registers */
+#define SNOWBALL_BASE	IPC_ISH2PMC_MSG_BASE
+#else
+/* from ISH4, used reserved rom part of AON memory */
+#define SNOWBALL_BASE	(CONFIG_AON_PERSISTENT_BASE + 256)
+#endif
+#define SNOWBALL_LEN	(4*32)
+
 MEMORY
 {
     /* leave STACK_SIZE bytes in the end of memory for stack */
     RAM : ORIGIN = SRAM_START, LENGTH = RAM_LEN
+    SNOWBALL : ORIGIN = SNOWBALL_BASE, LENGTH = SNOWBALL_LEN
 }
 
 SECTIONS
@@ -46,6 +59,11 @@ SECTIONS
 	KEEP(*(.data.aon_share))
     } > RAM
 
+    .data.snowball : AT(SNOWBALL_BASE)
+    {
+        KEEP(*(.data.snowball))
+    } > SNOWBALL
+
     .data :
     {
 	*(.data)
diff --git a/chip/ish/config_chip.h b/chip/ish/config_chip.h
index 3f3f3ee275..d27effdd72 100644
--- a/chip/ish/config_chip.h
+++ b/chip/ish/config_chip.h
@@ -54,10 +54,10 @@
 #endif
 
 /* The end of the AON memory is reserved for read-only use */
-#define CONFIG_AON_ROM_SIZE		0x180
-#define CONFIG_AON_ROM_BASE		(CONFIG_AON_RAM_BASE	\
+#define CONFIG_AON_PERSISTENT_SIZE	0x180
+#define CONFIG_AON_PERSISTENT_BASE	(CONFIG_AON_RAM_BASE	\
 					 + CONFIG_AON_RAM_SIZE	\
-					 - CONFIG_AON_ROM_SIZE)
+					 - CONFIG_AON_PERSISTENT_SIZE)
 
 /* Store persistent panic data in AON memory. */
 #define CONFIG_PANIC_DATA_BASE		(&(ish_persistent_data.panic_data))
diff --git a/chip/ish/ish_persistent_data.h b/chip/ish/ish_persistent_data.h
index 65a85203fb..e10e4d127c 100644
--- a/chip/ish/ish_persistent_data.h
+++ b/chip/ish/ish_persistent_data.h
@@ -38,4 +38,16 @@ void ish_persistent_data_init(void);
  */
 void ish_persistent_data_commit(void);
 
+/**
+ * SNOWBALL - registers about UMA/IMR DDR information and FW location
+ * in it.  ISH Bringup will set these register values at boot
+ */
+struct snowball_struct {
+	uint32_t reserved[28];
+	uint32_t uma_base_hi;
+	uint32_t uma_base_lo;
+	uint32_t uma_limit;
+	uint32_t fw_offset;
+};
+
 #endif /* __CROS_EC_ISH_PERSISTENT_DATA_H */
diff --git a/chip/ish/registers.h b/chip/ish/registers.h
index 42ccb44106..8f989fc647 100644
--- a/chip/ish/registers.h
+++ b/chip/ish/registers.h
@@ -331,21 +331,4 @@ enum ish_i2c_port {
 #define ISH_SRAM_CTRL_ERASE_ADDR	REG32(ISH_SRAM_CTRL_BASE + 0x10)
 #define ISH_SRAM_CTRL_BANK_STATUS	REG32(ISH_SRAM_CTRL_BASE + 0x2c)
 
-#if defined(CHIP_FAMILY_ISH3)
-/* on ISH3, reused ISH2PMC IPC message registers */
-#define SNOWBALL_BASE			IPC_ISH2PMC_MSG_BASE
-#else
-/* from ISH4, used reserved rom part of AON memory */
-#define SNOWBALL_BASE			(CONFIG_AON_ROM_BASE + 256)
-#endif
-
-/**
- * registers about UMA/IMR DDR information and FW location in it
- * ISH Bringup will set these registers' value at boot
- */
-#define SNOWBALL_UMA_BASE_HI  REG32(SNOWBALL_BASE + (4 * 28))
-#define SNOWBALL_UMA_BASE_LO  REG32(SNOWBALL_BASE + (4 * 29))
-#define SNOWBALL_UMA_LIMIT    REG32(SNOWBALL_BASE + (4 * 30))
-#define SNOWBALL_FW_OFFSET    REG32(SNOWBALL_BASE + (4 * 31))
-
 #endif /* __CROS_EC_REGISTERS_H */
diff --git a/core/minute-ia/ec.lds.S b/core/minute-ia/ec.lds.S
index 2a303a1f94..bf474130cc 100644
--- a/core/minute-ia/ec.lds.S
+++ b/core/minute-ia/ec.lds.S
@@ -208,6 +208,6 @@ SECTIONS
 	def_irq_high = ABSOLUTE(default_int_handler) >> 16;
 
 #ifdef CONFIG_ISH_PM_AONTASK
-	ish_persistent_data_aon = ABSOLUTE(CONFIG_AON_ROM_BASE);
+	ish_persistent_data_aon = ABSOLUTE(CONFIG_AON_PERSISTENT_BASE);
 #endif
 }
diff --git a/include/config.h b/include/config.h
index 08b9977dbf..a8ff3ea27b 100644
--- a/include/config.h
+++ b/include/config.h
@@ -99,10 +99,10 @@
  *
  * See chip/ish/ for an example implementation.
  */
+#undef CONFIG_AON_PERSISTENT_BASE
+#undef CONFIG_AON_PERSISTENT_SIZE
 #undef CONFIG_AON_RAM_BASE
 #undef CONFIG_AON_RAM_SIZE
-#undef CONFIG_AON_ROM_BASE
-#undef CONFIG_AON_ROM_SIZE
 
 /* Add sensorhub function for LSM6DSM, required if 2nd device attached. */
 #undef CONFIG_SENSORHUB_LSM6DSM