diff options
| author | Aseda Aboagye <aaboagye@google.com> | 2018-05-14 23:51:59 -0700 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2018-05-15 07:30:01 +0000 |
| commit | 39d125979dbe1d1f558aa511c63e56c9de9739fa (patch) | |
| tree | fa259e3a8053eee7424bf2f0c402175bbb6ecbaa | |
| parent | 6aef8f22b4dfc2a7427bc3d8a2c5375323ca03ed (diff) | |
| download | chrome-ec-39d125979dbe1d1f558aa511c63e56c9de9739fa.tar.gz | |
nocturne: Fix EC hibernate.
This commit adds the appropriate hibernate flags to the hibernate wake
pins. It additionally, adds a board specific hibernate function which
sets up the PSL pins for wake as well as writing to the ROP PMIC to
disable all the power rails.
BUG=b:79713379
BRANCH=master
TEST=Enter `hibernate` on EC console, verify that system can wake from
AC insertion, power button press, and lid switch.
Change-Id: I16e0e641ed3a7daaecd2661a9525d6653cbb1dc4
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1059088
Reviewed-by: Benson Leung <bleung@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
| -rw-r--r-- | board/nocturne/board.c | 26 | ||||
| -rw-r--r-- | board/nocturne/gpio.inc | 4 |
2 files changed, 28 insertions, 2 deletions
diff --git a/board/nocturne/board.c b/board/nocturne/board.c index 4c47af4267..1a96b9b629 100644 --- a/board/nocturne/board.c +++ b/board/nocturne/board.c @@ -31,6 +31,7 @@ #include "pwm_chip.h" #include "registers.h" #include "system.h" +#include "system_chip.h" #include "switch.h" #include "task.h" #include "tcpci.h" @@ -317,6 +318,31 @@ int board_get_version(void) return board_version; } +void board_hibernate(void) +{ + int p; + + /* Configure PSL pins */ + for (p = 0; p < hibernate_wake_pins_used; p++) + system_config_psl_mode(hibernate_wake_pins[p]); + gpio_config_module(MODULE_PMU, 1); + + /* + * Only PSL_IN events can pull PSL_OUT to high and reboot ec. + * We should treat it as wake-up pin reset. + */ + NPCX_BBRAM(BBRM_DATA_INDEX_WAKE) = HIBERNATE_WAKE_PIN; + + /* + * Set PSL_OUT (GPIO85) to low in order to enter PSL mode by + * setting bit 5 of PDOUT(8). + */ + SET_BIT(NPCX_PDOUT(GPIO_PORT_8), 5); + + /* Cut off DSW power via the ROP PMIC. */ + i2c_write8(I2C_PORT_PMIC, I2C_ADDR_BD99992, 0x49, 0x1); +} + static void board_pmic_init(void) { int pgmask1 = 0; diff --git a/board/nocturne/gpio.inc b/board/nocturne/gpio.inc index ede8871d20..125243018a 100644 --- a/board/nocturne/gpio.inc +++ b/board/nocturne/gpio.inc @@ -22,14 +22,14 @@ GPIO_INT(SLP_S0_L, PIN(A, 4), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SLP_S4_L, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SLP_S3_L, PIN(A, 6), GPIO_INT_BOTH, power_signal_interrupt) GPIO_INT(SLP_SUS_L_PCH, PIN(D, 4), GPIO_INT_BOTH, power_signal_interrupt) -GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH, extpower_interrupt) +GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) GPIO_INT(ROP_INT_L, PIN(D, 5), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) /* Misc. interrupts */ GPIO_INT(H1_EC_VOL_DOWN_ODL, PIN(6, 3), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(H1_EC_VOL_UP_ODL, PIN(7, 5), GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt) GPIO_INT(EC_WP_L, PIN(A, 1), GPIO_INT_BOTH, switch_interrupt) -GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH, lid_interrupt) +GPIO_INT(LID_OPEN, PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, lid_interrupt) GPIO_INT(ACCELGYRO3_INT_L, PIN(4, 1), GPIO_INT_FALLING, bmi160_interrupt) GPIO_INT(BASE_PWR_FAULT_ODL, PIN(2, 4), GPIO_INT_FALLING, base_pwr_fault_interrupt) GPIO_INT(RCAM_VSYNC, PIN(E, 4), GPIO_INT_FALLING, sync_interrupt) |