diff options
| author | Vincent Palatin <vpalatin@chromium.org> | 2018-04-13 15:09:01 +0200 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-04-22 01:21:45 -0700 |
| commit | 7bb91563e3ef6f0258810eb8c33c865d93268d95 (patch) | |
| tree | 2f8d2fec21be7d850ab76ae5c15e1c46c8fed71c | |
| parent | 07e19270f6946f68ef09891583ed73607fc322f7 (diff) | |
| download | chrome-ec-7bb91563e3ef6f0258810eb8c33c865d93268d95.tar.gz | |
stm32: more robust SPI slave on STM32H7
Try to ensure the SPI host protocol byte codes (aka EC_SPI_xxx) are
transmitted and at the right time despite the errata and other brokenness
of the SPI HW controller in the STM32H7 rev Y silicon.
Signed-off-by: Vincent Palatin <vpalatin@chromium.org>
BRANCH=poppy
BUG=b:73947203
TEST=on Meowth, run:
'while true; do ectool --name=cros_fp version || break ; done'
same thing with 'fpinfo', 'fptemplate', 'fpframe'.
Change-Id: Ia455dc0d4b2803a150122655460ef5c11afcda6c
Reviewed-on: https://chromium-review.googlesource.com/1012202
Commit-Ready: Vincent Palatin <vpalatin@chromium.org>
Tested-by: Vincent Palatin <vpalatin@chromium.org>
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | chip/stm32/spi.c | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/chip/stm32/spi.c b/chip/stm32/spi.c index 570f371d27..6cbb1a80e5 100644 --- a/chip/stm32/spi.c +++ b/chip/stm32/spi.c @@ -289,7 +289,7 @@ static void tx_status(uint8_t byte) spi->dr = byte; spi->dr = byte; #elif defined(CHIP_FAMILY_STM32H7) - spi->ifcr = STM32_SPI_SR_UDR; + spi->udrdr = byte; #endif } @@ -307,8 +307,10 @@ static void setup_for_transaction(void) /* clear this as soon as possible */ setup_transaction_later = 0; +#ifndef CHIP_FAMILY_STM32H7 /* H7 is not ready to set status here */ /* Not ready to receive yet */ tx_status(EC_SPI_NOT_READY); +#endif /* We are no longer actively processing a transaction */ state = SPI_STATE_PREPARE_RX; @@ -331,13 +333,13 @@ static void setup_for_transaction(void) /* Start DMA */ dma_start_rx(&dma_rx_option, sizeof(in_msg), in_msg); -#ifdef CHIP_FAMILY_STM32H7 - spi->cr1 |= STM32_SPI_CR1_SPE; -#endif - /* Ready to receive */ state = SPI_STATE_READY_TO_RX; tx_status(EC_SPI_OLD_READY); + +#ifdef CHIP_FAMILY_STM32H7 + spi->cr1 |= STM32_SPI_CR1_SPE; +#endif } /* Forward declaraction */ @@ -681,7 +683,7 @@ static void spi_init(void) spi->cfg1 = STM32_SPI_CFG1_DATASIZE(8) | STM32_SPI_CFG1_FTHLV(4) | STM32_SPI_CFG1_CRCSIZE(8) | STM32_SPI_CFG1_TXDMAEN | STM32_SPI_CFG1_RXDMAEN | - STM32_SPI_CFG1_UDRCFG_LAST_TX | + STM32_SPI_CFG1_UDRCFG_CONST | STM32_SPI_CFG1_UDRDET_BEGIN_FRM; spi->cr1 = 0; #else /* !CHIP_FAMILY_STM32H7 */ |