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| author | Scott Collyer <scollyer@google.com> | 2020-11-04 16:38:41 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-11-12 06:45:52 +0000 |
| commit | 90d57a15d96d6e65f9afb7826e1ee844c543afbe (patch) | |
| tree | 4305bdef15c6a6fb5c49c7eb9ab86af8886d66a7 | |
| parent | 6efb091912dd5ba1421e2717c56cf020b203687a (diff) | |
| download | chrome-ec-90d57a15d96d6e65f9afb7826e1ee844c543afbe.tar.gz | |
ucpd: Fix merge error with clock constants
This CL fixes an issue with a rebase merge, UCPD_IFRGAP_HBIT_CNT had
been changed to UCPD_IFRGAP_CNT in a previous CL. This CL removes
HBIT.
BUG=b:167601672
BRANCH=None
TEST=make BOARD=quiche
Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: Ideff65872d744bc7e3b3cdfa8c5af37f4725be36
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2522649
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>
| -rw-r--r-- | chip/stm32/ucpd-stm32gx.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/chip/stm32/ucpd-stm32gx.c b/chip/stm32/ucpd-stm32gx.c index 1355d9f042..96e907fad3 100644 --- a/chip/stm32/ucpd-stm32gx.c +++ b/chip/stm32/ucpd-stm32gx.c @@ -40,9 +40,9 @@ * tInterFrameGap = 1.625 uS * 17 = 27.625 uS */ #define UCPD_PSC_DIV 1 -#define UCPD_HBIT_DIV 26 -#define UCPD_TRANSWIN_HBIT_CNT 8 -#define UCPD_IFRGAP_HBIT_CNT 17 +#define UCPD_HBIT_DIV 27 +#define UCPD_TRANSWIN_CNT 8 +#define UCPD_IFRGAP_CNT 17 #define UCPD_ANASUB_TO_RP(r) ((r - 1) & 0x3) #define UCPD_RP_TO_ANASUB(r) ((r + 1) & 0x3) |