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| author | Shawn Nematbakhsh <shawnn@chromium.org> | 2015-09-16 22:25:33 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-09-17 19:00:54 -0700 |
| commit | 542a95c87b00b1cf733e033bf7bd77e440d17725 (patch) | |
| tree | 4d6dbf8ac271e7ac38cfce28afaa43ab0cbedc7a | |
| parent | 5717b3150c8a8d43e07ce2dc8065c3515d3651f7 (diff) | |
| download | chrome-ec-542a95c87b00b1cf733e033bf7bd77e440d17725.tar.gz | |
cleanup: Fix npcx build
The previous commits left npcx in a bad state. Change
CONFIG_PROGRAM_MEMORY_BASE to point to the actual start of code memory
and correct the linker file.
This still results in a non-working npcx image (more changes
forthcoming) but it does build.
BUG=chrome-os-partner:23796
TEST=make clean; make buildall -j
BRANCH=None
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Change-Id: Ia300c5d18695dccd8d9fd9a6122cd7d30353adfa
Reviewed-on: https://chromium-review.googlesource.com/300295
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Randall Spangler <rspangler@chromium.org>
| -rw-r--r-- | chip/npcx/config_chip.h | 2 | ||||
| -rw-r--r-- | common/firmware_image.lds.S | 8 |
2 files changed, 2 insertions, 8 deletions
diff --git a/chip/npcx/config_chip.h b/chip/npcx/config_chip.h index 2e99987a5f..7bf70c841e 100644 --- a/chip/npcx/config_chip.h +++ b/chip/npcx/config_chip.h @@ -47,7 +47,7 @@ /* Memory mapping */ #define CONFIG_RAM_BASE 0x200C0000 /* memory address of data ram */ #define CONFIG_RAM_SIZE (0x00008000 - 0x800) /* 30KB data ram */ -#define CONFIG_PROGRAM_MEMORY_BASE 0x64000000 /* program memory base address */ +#define CONFIG_PROGRAM_MEMORY_BASE 0x100A8000 /* program memory base address */ #define CONFIG_LPRAM_BASE 0x40001600 /* memory address of lpwr ram */ #define CONFIG_LPRAM_SIZE 0x00000620 /* 1568B low power ram */ diff --git a/common/firmware_image.lds.S b/common/firmware_image.lds.S index 546ad26c63..0ed3fd6563 100644 --- a/common/firmware_image.lds.S +++ b/common/firmware_image.lds.S @@ -14,13 +14,7 @@ MEMORY SECTIONS { . = ALIGN(CONFIG_FLASH_BANK_SIZE); -#if defined(NPCX_RO_HEADER) -/* Replace *_MEM_OFF with *_STORAGE_OFF to indicate flat file contains header - * or some struture which doesn't belong to FW */ - .image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_STORAGE_OFF) { -#else .image.RO : AT(CONFIG_PROGRAM_MEMORY_BASE + CONFIG_RO_MEM_OFF) { -#endif *(.image.RO) } > FLASH =0xff . = ALIGN(CONFIG_FLASH_BANK_SIZE); @@ -31,7 +25,7 @@ SECTIONS } > FLASH =0xff . = ALIGN(CONFIG_FLASH_BANK_SIZE); #endif -#if (CONFIG_RO_MEM_OFF == CONFIG_RW_MEM_OFF) +#ifdef CONFIG_EXTERNAL_STORAGE /* This is applicable to ECs in which RO and RW execution is mapped to the same location but we still have to generate an ec.bin with RO and RW images at different Flash offset */ |