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| author | Mulin Chao <mlchao@nuvoton.com> | 2021-06-08 03:12:10 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-06-10 22:11:28 +0000 |
| commit | b96da60a177950446fa3db6d538e6f32badaf7ff (patch) | |
| tree | 125adbcddad34f27f433f6b7dfc9661b891b6715 | |
| parent | 23cc1480e41507bc4331fef3ad069d6f0307d09e (diff) | |
| download | chrome-ec-b96da60a177950446fa3db6d538e6f32badaf7ff.tar.gz | |
zephyr: npcx: get valid bit-depth of RAM_PD registers via DT macro
Use DT macro to get valid bit-depth of RAM_PD registers instead of a
constant value. Since it is a general solution for saving power in
no-psl mode, this CL replaces the prefix 'NPCX7_' with 'NPCX_'.
BUG=b:188409672
BRANCH=none
TEST=Build and flash on lazor and npcx9 evb. Hibernate lazor platform
by typing 'hibernate' console command. Then, wake it up via lid open.
Signed-off-by: Mulin Chao <mlchao@nuvoton.com>
Change-Id: Iaf19761cc16f992cfcf06077ac222637e2544e5f
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2948708
Reviewed-by: Keith Short <keithshort@chromium.org>
Commit-Queue: Keith Short <keithshort@chromium.org>
| -rw-r--r-- | zephyr/drivers/cros_system/cros_system_npcx.c | 14 |
1 files changed, 9 insertions, 5 deletions
diff --git a/zephyr/drivers/cros_system/cros_system_npcx.c b/zephyr/drivers/cros_system/cros_system_npcx.c index 9fecde6116..74af8443a6 100644 --- a/zephyr/drivers/cros_system/cros_system_npcx.c +++ b/zephyr/drivers/cros_system/cros_system_npcx.c @@ -102,11 +102,15 @@ enum npcx_chip_id { */ #define DATA_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(sram0)) #define CODE_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(flash0)) -#define NPCX7_RAM_BLOCK_COUNT \ +#define NPCX_RAM_BLOCK_COUNT \ ((DATA_RAM_SIZE + CODE_RAM_SIZE + KB(2)) / NPCX_RAM_BLOCK_SIZE) -/* RAM block mask for power down in npcx7 series */ -#define NPCX7_RAM_BLOCK_PD_MASK (BIT(12) - 1) +/* Valid bit-depth of RAM block Power-Down control (RAM_PD) registers. Use its + * mask to power down all unnecessary RAM blocks before hibernating. + */ +#define NPCX_RAM_PD_DEPTH DT_PROP(DT_NODELABEL(pcc), ram_pd_depth) +#define NPCX_RAM_BLOCK_PD_MASK (BIT(NPCX_RAM_PD_DEPTH) - 1) + /* Get saved reset flag address in battery-backed ram */ #define BBRAM_SAVED_RESET_FLAG_ADDR \ (DT_REG_ADDR(DT_INST(0, nuvoton_npcx_cros_bbram)) + \ @@ -273,7 +277,7 @@ system_npcx_hibernate_by_lfw_in_last_ram(const struct device *dev, static inline int system_npcx_get_ram_blk_by_lfw_addr(char *address) { - return NPCX7_RAM_BLOCK_COUNT - + return NPCX_RAM_BLOCK_COUNT - ceiling_fraction((uint32_t)address - CONFIG_CROS_EC_PROGRAM_MEMORY_BASE, NPCX_RAM_BLOCK_SIZE); @@ -286,7 +290,7 @@ static void system_npcx_hibernate_by_disable_ram(const struct device *dev, /* Get 32kb ram block order of lfw function */ extern char __lfw_text_start[], __lfw_text_end[]; int lfw_block = system_npcx_get_ram_blk_by_lfw_addr(__lfw_text_start); - uint32_t pd_ram_mask = ~BIT(lfw_block) & NPCX7_RAM_BLOCK_PD_MASK; + uint32_t pd_ram_mask = ~BIT(lfw_block) & NPCX_RAM_BLOCK_PD_MASK; if (lfw_block != system_npcx_get_ram_blk_by_lfw_addr(__lfw_text_end)) { LOG_ERR("LFW cannot cross ram blocks!"); |