zephyr: npcx: update SHI driver for pinctrl

Update the Nuvoton cros_shi_npcx driver to use pinctrl instead of pinmux.

This introduces a SHI specific pinctrl state to switch the SHI pins back
to GPIO.

BUG=b:232543902
BRANCH=none
TEST=zmake testall
TEST=verify herobrine boots to AP.  Verify sysjump to RW works on
herobrine.

Signed-off-by: Keith Short <keithshort@chromium.org>
Change-Id: Ic66062d706738792ffffc5797637ae8a5d31593c
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3646964
Tested-by: Eric Yilun Lin <yllin@google.com>
Reviewed-by: Sam Hurst <shurst@google.com>

9 files changed, 71 insertions, 17 deletions

diff --git a/zephyr/boards/arm/npcx7/npcx7.dts b/zephyr/boards/arm/npcx7/npcx7.dts
index e615789e16..551c3fe3af 100644
--- a/zephyr/boards/arm/npcx7/npcx7.dts
+++ b/zephyr/boards/arm/npcx7/npcx7.dts
@@ -51,6 +51,17 @@
 	pinctrl-names = "default";
 };
 
+&pinctrl {
+	/*
+	 * TODO(b/232573074): Move pinctrl to set SHI pins to GPIO mode
+	 * upstream.
+	 */
+	/omit-if-no-ref/ shi_gpio_gp46_47_53_55: periph-shi-gpio {
+		pinmux = <&altc_shi_sl>;
+		pinmux-gpio;
+	};
+};
+
 &cros_kb_raw {
 	status = "okay";
 	/* No KSO2 (it's inverted and implemented by GPIO) */
diff --git a/zephyr/boards/arm/npcx9/npcx9.dtsi b/zephyr/boards/arm/npcx9/npcx9.dtsi
index 57a6422da7..4b43bda08a 100644
--- a/zephyr/boards/arm/npcx9/npcx9.dtsi
+++ b/zephyr/boards/arm/npcx9/npcx9.dtsi
@@ -46,6 +46,17 @@
 	pinctrl-names = "default";
 };
 
+&pinctrl {
+	/*
+	 * TODO(b/232573074): Move pinctrl to set SHI pins to GPIO mode
+	 * upstream.
+	 */
+	 /omit-if-no-ref/ shi_gpio_gp46_47_53_55: periph-shi-gpio {
+		pinmux = <&altc_shi_sl>;
+		pinmux-gpio;
+	};
+};
+
 &cros_kb_raw {
 	status = "okay";
 	/* No KSO2 (it's inverted and implemented by GPIO) */
diff --git a/zephyr/drivers/cros_shi/cros_shi_npcx.c b/zephyr/drivers/cros_shi/cros_shi_npcx.c
index 0c2ec964ea..b236980205 100644
--- a/zephyr/drivers/cros_shi/cros_shi_npcx.c
+++ b/zephyr/drivers/cros_shi/cros_shi_npcx.c
@@ -9,6 +9,7 @@
 #include <assert.h>
 #include <zephyr/dt-bindings/clock/npcx_clock.h>
 #include <zephyr/drivers/clock_control.h>
+#include <zephyr/drivers/pinctrl.h>
 #include <drivers/cros_shi.h>
 #include <zephyr/drivers/gpio.h>
 #include <zephyr/logging/log.h>
@@ -134,9 +135,8 @@ struct cros_shi_npcx_config {
 	uintptr_t base;
 	/* clock configuration */
 	struct npcx_clk_cfg clk_cfg;
-	/* pinmux configuration */
-	const uint8_t alts_size;
-	const struct npcx_alt *alts_list;
+	/* Pin control configuration */
+	const struct pinctrl_dev_config *pcfg;
 	/* SHI IRQ */
 	int irq;
 	struct npcx_wui shi_cs_wui;
@@ -155,13 +155,12 @@ struct shi_bus_parameters {
 	uint64_t rx_deadline; /* deadline of receiving            */
 } shi_params;
 
-static const struct npcx_alt cros_shi_alts[] = NPCX_DT_ALT_ITEMS_LIST(0);
+PINCTRL_DT_INST_DEFINE(0);
 
 static const struct cros_shi_npcx_config cros_shi_cfg = {
 	.base = DT_INST_REG_ADDR(0),
 	.clk_cfg = NPCX_DT_CLK_CFG_ITEM(0),
-	.alts_size = ARRAY_SIZE(cros_shi_alts),
-	.alts_list = cros_shi_alts,
+	.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(0),
 	.irq = DT_INST_IRQN(0),
 	.shi_cs_wui = NPCX_DT_WUI_ITEM_BY_NAME(0, shi_cs_wui),
 };
@@ -778,8 +777,12 @@ static int cros_shi_npcx_enable(const struct device *dev)
 	cros_shi_npcx_reset_prepare(inst);
 	npcx_miwu_irq_disable(&config->shi_cs_wui);
 
-	/* Configure pin-mux from GPIO to SHI. */
-	npcx_pinctrl_mux_configure(config->alts_list, config->alts_size, 1);
+	/* Configure pin control for SHI */
+	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_DEFAULT);
+	if (ret < 0) {
+		LOG_ERR("cros_shi_npcx pinctrl setup failed (%d)", ret);
+		return ret;
+	}
 
 	NVIC_ClearPendingIRQ(DT_INST_IRQN(0));
 	npcx_miwu_irq_enable(&config->shi_cs_wui);
@@ -799,8 +802,12 @@ static int cros_shi_npcx_disable(const struct device *dev)
 	irq_disable(DT_INST_IRQN(0));
 	npcx_miwu_irq_disable(&config->shi_cs_wui);
 
-	/* Configure pin-mux from SHI to GPIO. */
-	npcx_pinctrl_mux_configure(config->alts_list, config->alts_size, 0);
+	/* Configure pin control back to GPIO */
+	ret = pinctrl_apply_state(config->pcfg, PINCTRL_STATE_SLEEP);
+	if (ret < 0) {
+		LOG_ERR("KB Raw pinctrl setup failed (%d)", ret);
+		return ret;
+	}
 
 	ret = clock_control_off(clk_dev,
 			       (clock_control_subsys_t *)&config->clk_cfg);
diff --git a/zephyr/dts/bindings/cros_shi/nuvoton,npcx-cros-shi.yaml b/zephyr/dts/bindings/cros_shi/nuvoton,npcx-cros-shi.yaml
index c13f3e2b5a..0761ba3526 100644
--- a/zephyr/dts/bindings/cros_shi/nuvoton,npcx-cros-shi.yaml
+++ b/zephyr/dts/bindings/cros_shi/nuvoton,npcx-cros-shi.yaml
@@ -5,7 +5,7 @@ description: Nuvoton, NPCX Serial Host Interface (SHI) node
 
 compatible: "nuvoton,npcx-cros-shi"
 
-include: base.yaml
+include: [base.yaml, pinctrl-device.yaml]
 
 properties:
     reg:
@@ -17,9 +17,13 @@ properties:
         description: configurations of device source clock controller
 
     pinctrl-0:
-        type: phandles
         required: true
-        description: configurations of pinmux controllers
+
+    pinctrl-1:
+        required: false
+
+    pinctrl-names:
+        required: true
 
     shi-cs-wui:
         type: phandle
diff --git a/zephyr/include/cros/nuvoton/npcx.dtsi b/zephyr/include/cros/nuvoton/npcx.dtsi
index dbc4c3daaa..094f5ff901 100644
--- a/zephyr/include/cros/nuvoton/npcx.dtsi
+++ b/zephyr/include/cros/nuvoton/npcx.dtsi
@@ -97,9 +97,9 @@
 			reg = <0x4000f000 0x120>;
 			interrupts = <18 1>;
 			clocks = <&pcc NPCX_CLOCK_BUS_APB3 NPCX_PWDWN_CTL5 1>;
-			pinctrl-0 = <&altc_shi_sl>;
 			shi-cs-wui =<&wui_io53>;
 			label = "SHI";
+			status = "disabled";
 		};
 	};
 
diff --git a/zephyr/projects/corsola/host_interface_npcx.dts b/zephyr/projects/corsola/host_interface_npcx.dts
index ee3a350813..9c6a498940 100644
--- a/zephyr/projects/corsola/host_interface_npcx.dts
+++ b/zephyr/projects/corsola/host_interface_npcx.dts
@@ -4,8 +4,9 @@
  */
 
 /* host interface */
-&espi0 {
+&shi {
 	status = "okay";
-	pinctrl-0 = <&espi_lpc_gp46_47_51_52_53_54_55_57>;
-	pinctrl-names = "default";
+	pinctrl-0 = <&shi_gp46_47_53_55>;
+	pinctrl-1 = <&shi_gpio_gp46_47_53_55>;
+	pinctrl-names = "default", "sleep";
 };
diff --git a/zephyr/projects/herobrine/common.dts b/zephyr/projects/herobrine/common.dts
index dfe460d146..aeb99c5377 100644
--- a/zephyr/projects/herobrine/common.dts
+++ b/zephyr/projects/herobrine/common.dts
@@ -35,3 +35,10 @@
 				MKBP_EVENT_SENSOR_FIFO)>;
 	};
 };
+
+&shi {
+	status = "okay";
+	pinctrl-0 = <&shi_gp46_47_53_55>;
+	pinctrl-1 = <&shi_gpio_gp46_47_53_55>;
+	pinctrl-names = "default", "sleep";
+};
diff --git a/zephyr/projects/trogdor/lazor/BUILD.py b/zephyr/projects/trogdor/lazor/BUILD.py
index cde49bcc2b..8e7936f12f 100644
--- a/zephyr/projects/trogdor/lazor/BUILD.py
+++ b/zephyr/projects/trogdor/lazor/BUILD.py
@@ -13,6 +13,7 @@ register_npcx_project(
         "display.dts",
         "gpio.dts",
         "i2c.dts",
+        "host_interface_npcx.dts",
         "interrupts.dts",
         "keyboard.dts",
         "led.dts",
diff --git a/zephyr/projects/trogdor/lazor/host_interface_npcx.dts b/zephyr/projects/trogdor/lazor/host_interface_npcx.dts
new file mode 100644
index 0000000000..9c6a498940
--- /dev/null
+++ b/zephyr/projects/trogdor/lazor/host_interface_npcx.dts
@@ -0,0 +1,12 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* host interface */
+&shi {
+	status = "okay";
+	pinctrl-0 = <&shi_gp46_47_53_55>;
+	pinctrl-1 = <&shi_gpio_gp46_47_53_55>;
+	pinctrl-names = "default", "sleep";
+};