diff options
| author | Sam Hurst <shurst@google.com> | 2022-05-17 14:23:13 -0700 |
|---|---|---|
| committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-06-01 22:14:20 +0000 |
| commit | fc85f0c71f726e5e64bb04be452723d8fefa4064 (patch) | |
| tree | 3651bbd3d4c4640cdf963a2e51f60a0875626b9f | |
| parent | 882f058752e21b31d89b26026e30410583ec75a0 (diff) | |
| download | chrome-ec-fc85f0c71f726e5e64bb04be452723d8fefa4064.tar.gz | |
Zephyr: npcx: Add clock turbo mode for NPCX9
Add clock turbo mode for NPCX9
BUG=b:230663570
BRANCH=none
TEST=zmake testall
Signed-off-by: Sam Hurst <shurst@google.com>
Change-Id: If3e3161b83ddd47c2123511c8fd269de4d246e7a
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3652223
Reviewed-by: Wai-Hong Tam <waihong@google.com>
| -rw-r--r-- | zephyr/shim/chip/npcx/clock.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/zephyr/shim/chip/npcx/clock.c b/zephyr/shim/chip/npcx/clock.c index ca89c7a4be..4fc9bd12c0 100644 --- a/zephyr/shim/chip/npcx/clock.c +++ b/zephyr/shim/chip/npcx/clock.c @@ -41,11 +41,20 @@ void clock_turbo(void) { struct cdcg_reg *const cdcg_base = HAL_CDCG_REG_BASE_ADDR; +#if defined(CONFIG_SOC_SERIES_NPCX9) + /* For NPCX9: + * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since + * CORE_CLK > 66MHz, we also need to set FIUDIV as 1 but + * can keep AHB6DIV to 0. + */ + cdcg_base->HFCGP = 0x00; +#else /* For NPCX7: * Increase CORE_CLK (CPU) as the same as OSC_CLK. Since * CORE_CLK > 66MHz, we also need to set AHB6DIV and FIUDIV as 1. */ cdcg_base->HFCGP = 0x01; +#endif cdcg_base->HFCBCD = BIT(4); } |