diff options
author | Jes B. Klinke <jbk@chromium.org> | 2022-12-07 15:22:57 -0800 |
---|---|---|
committer | Chromeos LUCI <chromeos-scoped@luci-project-accounts.iam.gserviceaccount.com> | 2022-12-09 20:55:44 +0000 |
commit | 6dcc49905c3cc759dd43aee0f9fbfe3c00e7dd94 (patch) | |
tree | bf5bc01d8edaed69c3f17a8cac63e36aa7b9d92a | |
parent | 05b3cc74a66e59bf0eff0278423443ca6fe2535f (diff) | |
download | chrome-ec-6dcc49905c3cc759dd43aee0f9fbfe3c00e7dd94.tar.gz |
chip/stm32: Add register declarations for OctoSPI
The STM32L5 series of chips have a SPI controller capable of using up to
eight data lines for fast transfers, primarily with SPI flash chips.
This CL adds declarations of register addresses and bits.
BUG=b:192262089
TEST=Flashed OpenTitan FPGA via HyperDebug OctoSPI
Change-Id: I33d16ba493756cf338353a5f0952be97070720d6
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/4087327
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
Code-Coverage: Zoss <zoss-cl-coverage@prod.google.com>
Tested-by: Jes Klinke <jbk@chromium.org>
Commit-Queue: Jes Klinke <jbk@chromium.org>
-rw-r--r-- | chip/stm32/registers-stm32l5.h | 291 |
1 files changed, 291 insertions, 0 deletions
diff --git a/chip/stm32/registers-stm32l5.h b/chip/stm32/registers-stm32l5.h index 47f766e035..eec7413233 100644 --- a/chip/stm32/registers-stm32l5.h +++ b/chip/stm32/registers-stm32l5.h @@ -120,6 +120,7 @@ #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) #define AHB2PERIPH_BASE (PERIPH_BASE + 0x02000000UL) +#define AHB3PERIPH_BASE (PERIPH_BASE + 0x04000000UL) /*!< APB1 peripherals */ #define STM32_TIM2_BASE (APB1PERIPH_BASE + 0x0000UL) @@ -202,6 +203,9 @@ #define STM32_GPIOH_BASE (AHB2PERIPH_BASE + 0x21C00UL) #define STM32_RNG_BASE (AHB2PERIPH_BASE + 0xC4000UL) +/*!< AHB3 peripherals */ +#define STM32_OCTOSPI_BASE (AHB3PERIPH_BASE + 0x21000UL) + /* Debug MCU registers base address */ #define STM32_PACKAGE_BASE 0x0BFA0500UL #define STM32_UID_BASE 0x0BFA0590UL @@ -2455,4 +2459,291 @@ enum dmamux1_request { #define DMAMUX_REQ_UART9_RX DMAMUX_REQ_LPUART1_RX #define DMAMUX_REQ_UART9_TX DMAMUX_REQ_LPUART1_TX +/* --- OCTOSPI --- */ + +#define STM32_OCTOSPI_CR REG32(STM32_OCTOSPI_BASE + 0x00) +#define STM32_OCTOSPI_DCR1 REG32(STM32_OCTOSPI_BASE + 0x08) +#define STM32_OCTOSPI_DCR2 REG32(STM32_OCTOSPI_BASE + 0x0C) +#define STM32_OCTOSPI_DCR3 REG32(STM32_OCTOSPI_BASE + 0x10) +#define STM32_OCTOSPI_DCR4 REG32(STM32_OCTOSPI_BASE + 0x14) +#define STM32_OCTOSPI_SR REG32(STM32_OCTOSPI_BASE + 0x20) +#define STM32_OCTOSPI_FCR REG32(STM32_OCTOSPI_BASE + 0x24) +#define STM32_OCTOSPI_DLR REG32(STM32_OCTOSPI_BASE + 0x40) +#define STM32_OCTOSPI_AR REG32(STM32_OCTOSPI_BASE + 0x48) +#define STM32_OCTOSPI_DR REG32(STM32_OCTOSPI_BASE + 0x50) +#define STM32_OCTOSPI_PSMKR REG32(STM32_OCTOSPI_BASE + 0x80) +#define STM32_OCTOSPI_PSMAR REG32(STM32_OCTOSPI_BASE + 0x88) +#define STM32_OCTOSPI_PIR REG32(STM32_OCTOSPI_BASE + 0x90) +#define STM32_OCTOSPI_CCR REG32(STM32_OCTOSPI_BASE + 0x100) +#define STM32_OCTOSPI_TCR REG32(STM32_OCTOSPI_BASE + 0x108) +#define STM32_OCTOSPI_IR REG32(STM32_OCTOSPI_BASE + 0x110) +#define STM32_OCTOSPI_ABR REG32(STM32_OCTOSPI_BASE + 0x120) +#define STM32_OCTOSPI_LPTR REG32(STM32_OCTOSPI_BASE + 0x130) +#define STM32_OCTOSPI_WPCCR REG32(STM32_OCTOSPI_BASE + 0x140) +#define STM32_OCTOSPI_WPTCR REG32(STM32_OCTOSPI_BASE + 0x148) +#define STM32_OCTOSPI_WPIR REG32(STM32_OCTOSPI_BASE + 0x150) +#define STM32_OCTOSPI_WPABR REG32(STM32_OCTOSPI_BASE + 0x160) +#define STM32_OCTOSPI_WCCR REG32(STM32_OCTOSPI_BASE + 0x180) +#define STM32_OCTOSPI_WTCR REG32(STM32_OCTOSPI_BASE + 0x188) +#define STM32_OCTOSPI_WIR REG32(STM32_OCTOSPI_BASE + 0x190) +#define STM32_OCTOSPI_WABR REG32(STM32_OCTOSPI_BASE + 0x1A0) +#define STM32_OCTOSPI_HLCR REG32(STM32_OCTOSPI_BASE + 0x200) + +/* Bit values for STM32_OCTOSPI_CR */ +#define STM32_OCTOSPI_CR_FMODE_POS 28U +#define STM32_OCTOSPI_CR_FMODE_MSK (0x3UL << STM32_OCTOSPI_CR_FMODE_POS) +#define STM32_OCTOSPI_CR_FMODE STM32_OCTOSPI_FMODE_MSK +#define STM32_OCTOSPI_CR_FMODE_IND_WRITE (0x0UL << STM32_OCTOSPI_CR_FMODE_POS) +#define STM32_OCTOSPI_CR_FMODE_IND_READ (0x1UL << STM32_OCTOSPI_CR_FMODE_POS) +#define STM32_OCTOSPI_CR_FMODE_AUTO_POLL (0x2UL << STM32_OCTOSPI_CR_FMODE_POS) +#define STM32_OCTOSPI_CR_FMODE_MEM_MAPPED (0x3UL << STM32_OCTOSPI_CR_FMODE_POS) + +#define STM32_OCTOSPI_CR_PMM_POS 23U +#define STM32_OCTOSPI_CR_PMM_MSK (0x1UL << STM32_OCTOSPI_CR_PMM_POS) +#define STM32_OCTOSPI_CR_PMM_AND 0 +#define STM32_OCTOSPI_CR_PMM_OR STM32_OCTOSPI_CR_PMM_MSK + +#define STM32_OCTOSPI_CR_APMS_POS 22U +#define STM32_OCTOSPI_CR_APMS_MSK (0x1UL << STM32_OCTOSPI_CR_APMS_POS) +#define STM32_OCTOSPI_CR_APMS STM32_OCTOSPI_CR_APMS_MSK + +#define STM32_OCTOSPI_CR_TOIE_POS 20U +#define STM32_OCTOSPI_CR_TOIE_MSK (0x1UL << STM32_OCTOSPI_CR_TOIE_POS) +#define STM32_OCTOSPI_CR_TOIE STM32_OCTOSPI_CR_TOIE_MSK + +#define STM32_OCTOSPI_CR_SMIE_POS 19U +#define STM32_OCTOSPI_CR_SMIE_MSK (0x1UL << STM32_OCTOSPI_CR_SMIE_POS) +#define STM32_OCTOSPI_CR_SMIE STM32_OCTOSPI_CR_SMIE_MSK + +#define STM32_OCTOSPI_CR_FTIE_POS 18U +#define STM32_OCTOSPI_CR_FTIE_MSK (0x1UL << STM32_OCTOSPI_CR_FTIE_POS) +#define STM32_OCTOSPI_CR_FTIE STM32_OCTOSPI_CR_FTIE_MSK + +#define STM32_OCTOSPI_CR_TCIE_POS 17U +#define STM32_OCTOSPI_CR_TCIE_MSK (0x1UL << STM32_OCTOSPI_CR_TCIE_POS) +#define STM32_OCTOSPI_CR_TCIE STM32_OCTOSPI_CR_TCIE_MSK + +#define STM32_OCTOSPI_CR_TEIE_POS 16U +#define STM32_OCTOSPI_CR_TEIE_MSK (0x1UL << STM32_OCTOSPI_CR_TEIE_POS) +#define STM32_OCTOSPI_CR_TEIE STM32_OCTOSPI_CR_TEIE_MSK + +#define STM32_OCTOSPI_CR_FTHRES_POS 8U +#define STM32_OCTOSPI_CR_FTHRES_MSK (0x1FUL << STM32_OCTOSPI_CR_FTHRES_POS) + +#define STM32_OCTOSPI_CR_MSEL_POS 7U +#define STM32_OCTOSPI_CR_MSEL_MSK (0x1UL << STM32_OCTOSPI_CR_MSEL_POS) +#define STM32_OCTOSPI_CR_MSEL_FLASH1 0 +#define STM32_OCTOSPI_CR_MSEL_FLASH2 STM32_OCTOSPI_CR_MSEL_MSK + +#define STM32_OCTOSPI_CR_DMM_POS 6U +#define STM32_OCTOSPI_CR_DMM_MSK (0x1UL << STM32_OCTOSPI_CR_DMM_POS) +#define STM32_OCTOSPI_CR_DMM STM32_OCTOSPI_CR_DMM_MSK + +#define STM32_OCTOSPI_CR_TCEN_POS 3U +#define STM32_OCTOSPI_CR_TCEN_MSK (0x1UL << STM32_OCTOSPI_CR_TCEN_POS) +#define STM32_OCTOSPI_CR_TCEN STM32_OCTOSPI_CR_TCEN_MSK + +#define STM32_OCTOSPI_CR_DMAEN_POS 2U +#define STM32_OCTOSPI_CR_DMAEN_MSK (0x1UL << STM32_OCTOSPI_CR_DMAEN_POS) +#define STM32_OCTOSPI_CR_DMAEN STM32_OCTOSPI_CR_DMAEN_MSK + +#define STM32_OCTOSPI_CR_ABORT_POS 1U +#define STM32_OCTOSPI_CR_ABORT_MSK (0x1UL << STM32_OCTOSPI_CR_ABORT_POS) +#define STM32_OCTOSPI_CR_ABORT STM32_OCTOSPI_CR_ABORT_MSK + +#define STM32_OCTOSPI_CR_EN_POS 0U +#define STM32_OCTOSPI_CR_EN_MSK (0x1UL << STM32_OCTOSPI_CR_EN_POS) +#define STM32_OCTOSPI_CR_EN STM32_OCTOSPI_CR_EN_MSK + +/* Bit values for STM32_OCTOSPI_DCR1 */ +#define STM32_OCTOSPI_DCR1_MTYP_POS 24U +#define STM32_OCTOSPI_DCR1_MTYP_MSK (0x7UL << STM32_OCTOSPI_DCR1_MTYP_POS) +#define STM32_OCTOSPI_DCR1_MTYP_MICROS (0x0UL << STM32_OCTOSPI_DCR1_MTYP_POS) +#define STM32_OCTOSPI_DCR1_MTYP_MACRONIX (0x1UL << STM32_OCTOSPI_DCR1_MTYP_POS) +#define STM32_OCTOSPI_DCR1_MTYP_STANDARD (0x2UL << STM32_OCTOSPI_DCR1_MTYP_POS) +#define STM32_OCTOSPI_DCR1_MTYP_MACRONIX_RAM \ + (0x3UL << STM32_OCTOSPI_DCR1_MTYP_POS) +#define STM32_OCTOSPI_DCR1_MTYP_HYPERBUS_MEM \ + (0x4UL << STM32_OCTOSPI_DCR1_MTYP_POS) +#define STM32_OCTOSPI_DCR1_MTYP_HYPERBUS_REG \ + (0x5UL << STM32_OCTOSPI_DCR1_MTYP_POS) + +#define STM32_OCTOSPI_DCR1_DEVSIZE_POS 16U +#define STM32_OCTOSPI_DCR1_DEVSIZE_MSK \ + (0x1FUL << STM32_OCTOSPI_DCR1_DEVSIZE_POS) + +#define STM32_OCTOSPI_DCR1_CSHT_POS 8U +#define STM32_OCTOSPI_DCR1_CSHT_MSK (0x1UL << STM32_OCTOSPI_DCR1_CSHT_POS) +#define STM32_OCTOSPI_DCR1_CSHT_1 (0x0UL << STM32_OCTOSPI_DCR1_CSHT_POS) +#define STM32_OCTOSPI_DCR1_CSHT_2 (0x1UL << STM32_OCTOSPI_DCR1_CSHT_POS) +#define STM32_OCTOSPI_DCR1_CSHT_3 (0x2UL << STM32_OCTOSPI_DCR1_CSHT_POS) +#define STM32_OCTOSPI_DCR1_CSHT_4 (0x3UL << STM32_OCTOSPI_DCR1_CSHT_POS) +#define STM32_OCTOSPI_DCR1_CSHT_5 (0x4UL << STM32_OCTOSPI_DCR1_CSHT_POS) +#define STM32_OCTOSPI_DCR1_CSHT_6 (0x5UL << STM32_OCTOSPI_DCR1_CSHT_POS) +#define STM32_OCTOSPI_DCR1_CSHT_7 (0x6UL << STM32_OCTOSPI_DCR1_CSHT_POS) +#define STM32_OCTOSPI_DCR1_CSHT_8 (0x7UL << STM32_OCTOSPI_DCR1_CSHT_POS) + +#define STM32_OCTOSPI_DCR1_DLYBYP_POS 3U +#define STM32_OCTOSPI_DCR1_DLYBYP_MSK (0x1UL << STM32_OCTOSPI_DCR1_DLYBYP_POS) +#define STM32_OCTOSPI_DCR1_DLYBYP STM32_OCTOSPI_DCR1_DLYBYP_MSK + +#define STM32_OCTOSPI_DCR1_FRCK_POS 1U +#define STM32_OCTOSPI_DCR1_FRCK_MSK (0x1UL << STM32_OCTOSPI_DCR1_FRCK_POS) +#define STM32_OCTOSPI_DCR1_FRCK STM32_OCTOSPI_DCR1_FRCK_MSK + +#define STM32_OCTOSPI_DCR1_CKMODE_POS 0U +#define STM32_OCTOSPI_DCR1_CKMODE_MSK (0x1UL << STM32_OCTOSPI_DCR1_CKMODE_POS) +#define STM32_OCTOSPI_DCR1_CKMODE_LOW 0 +#define STM32_OCTOSPI_DCR1_CKMODE_HIGH STM32_OCTOSPI_DCR1_CKMODE_MSK + +/* Bit values for STM32_OCTOSPI_DCR2 */ +#define STM32_OCTOSPI_DCR2_WRAPSIZE_POS 16U +#define STM32_OCTOSPI_DCR2_WRAPSIZE_MSK \ + (0x7UL << STM32_OCTOSPI_DCR2_WRAPSIZE_POS) + +#define STM32_OCTOSPI_DCR2_PRESCALER_POS 0U +#define STM32_OCTOSPI_DCR2_PRESCALER_MSK \ + (0xFFUL << STM32_OCTOSPI_DCR2_PRESCALER_POS) + +/* Bit values for STM32_OCTOSPI_DCR3 */ +#define STM32_OCTOSPI_DCR3_CSBOUND_POS 16U +#define STM32_OCTOSPI_DCR3_CSBOUND_MSK \ + (0x1FUL << STM32_OCTOSPI_DCR3_CSBOUND_POS) +#define STM32_OCTOSPI_DCR3_CSBOUND_DISABLED 0 + +/* Bit values for STM32_OCTOSPI_SR */ +#define STM32_OCTOSPI_SR_FLEVEL_POS 8U +#define STM32_OCTOSPI_SR_FLEVEL_MSK (0x3FUL << STM32_OCTOSPI_SR_FLEVEL_POS) + +#define STM32_OCTOSPI_SR_BUSY_POS 5U +#define STM32_OCTOSPI_SR_BUSY_MSK (0x1UL << STM32_OCTOSPI_SR_BUSY_POS) +#define STM32_OCTOSPI_SR_BUSY STM32_OCTOSPI_SR_BUSY_MSK + +#define STM32_OCTOSPI_SR_TOF_POS 4U +#define STM32_OCTOSPI_SR_TOF_MSK (0x1UL << STM32_OCTOSPI_SR_TOF_POS) +#define STM32_OCTOSPI_SR_TOF STM32_OCTOSPI_SR_TOF_MSK + +#define STM32_OCTOSPI_SR_SMF_POS 3U +#define STM32_OCTOSPI_SR_SMF_MSK (0x1UL << STM32_OCTOSPI_SR_SMF_POS) +#define STM32_OCTOSPI_SR_SMF STM32_OCTOSPI_SR_SMF_MSK + +#define STM32_OCTOSPI_SR_FTF_POS 2U +#define STM32_OCTOSPI_SR_FTF_MSK (0x1UL << STM32_OCTOSPI_SR_FTF_POS) +#define STM32_OCTOSPI_SR_FTF STM32_OCTOSPI_SR_FTF_MSK + +#define STM32_OCTOSPI_SR_TCF_POS 1U +#define STM32_OCTOSPI_SR_TCF_MSK (0x1UL << STM32_OCTOSPI_SR_TCF_POS) +#define STM32_OCTOSPI_SR_TCF STM32_OCTOSPI_SR_TCF_MSK + +#define STM32_OCTOSPI_SR_TEF_POS 0U +#define STM32_OCTOSPI_SR_TEF_MSK (0x1UL << STM32_OCTOSPI_SR_TEF_POS) +#define STM32_OCTOSPI_SR_TEF STM32_OCTOSPI_SR_TEF_MSK + +/* Bit values for STM32_OCTOSPI_FCR */ +#define STM32_OCTOSPI_FCR_CTOF_POS 4U +#define STM32_OCTOSPI_FCR_CTOF_MSK (0x1UL << STM32_OCTOSPI_FCR_CTOF_POS) +#define STM32_OCTOSPI_FCR_CTOF STM32_OCTOSPI_FCR_CTOF_MSK + +#define STM32_OCTOSPI_FCR_CSMF_POS 3U +#define STM32_OCTOSPI_FCR_CSMF_MSK (0x1UL << STM32_OCTOSPI_FCR_CSMF_POS) +#define STM32_OCTOSPI_FCR_CSMF STM32_OCTOSPI_FCR_CSMF_MSK + +#define STM32_OCTOSPI_FCR_CTCF_POS 1U +#define STM32_OCTOSPI_FCR_CTCF_MSK (0x1UL << STM32_OCTOSPI_FCR_CTCF_POS) +#define STM32_OCTOSPI_FCR_CTCF STM32_OCTOSPI_FCR_CTCF_MSK + +#define STM32_OCTOSPI_FCR_CTEF_POS 0U +#define STM32_OCTOSPI_FCR_CTEF_MSK (0x1UL << STM32_OCTOSPI_FCR_CTEF_POS) +#define STM32_OCTOSPI_FCR_CTEF STM32_OCTOSPI_FCR_CTEF_MSK + +/* Bit values for STM32_OCTOSPI_CCR */ +#define STM32_OCTOSPI_CCR_SIOO_POS 31U +#define STM32_OCTOSPI_CCR_SIOO_MSK (0x1UL << STM32_OCTOSPI_FCR_SIOO_POS) +#define STM32_OCTOSPI_CCR_SIOO STM32_OCTOSPI_FCR_SIOO_MSK + +#define STM32_OCTOSPI_CCR_DQSE_POS 29U +#define STM32_OCTOSPI_CCR_DQSE_MSK (0x1UL << STM32_OCTOSPI_FCR_DQSE_POS) +#define STM32_OCTOSPI_CCR_DQSE STM32_OCTOSPI_FCR_DQSE_MSK + +#define STM32_OCTOSPI_CCR_DDTR_POS 27U +#define STM32_OCTOSPI_CCR_DDTR_MSK (0x1UL << STM32_OCTOSPI_CCR_DDTR_POS) +#define STM32_OCTOSPI_CCR_DDTR STM32_OCTOSPI_CCR_DDTR_MSK + +#define STM32_OCTOSPI_CCR_DMODE_POS 24U +#define STM32_OCTOSPI_CCR_DMODE_MSK (0x1UL << STM32_OCTOSPI_CCR_DMODE_POS) +#define STM32_OCTOSPI_CCR_DMODE_NONE (0UL << STM32_OCTOSPI_CCR_DMODE_POS) +#define STM32_OCTOSPI_CCR_DMODE_1WIRE (1UL << STM32_OCTOSPI_CCR_DMODE_POS) +#define STM32_OCTOSPI_CCR_DMODE_2WIRE (2UL << STM32_OCTOSPI_CCR_DMODE_POS) +#define STM32_OCTOSPI_CCR_DMODE_4WIRE (3UL << STM32_OCTOSPI_CCR_DMODE_POS) +#define STM32_OCTOSPI_CCR_DMODE_8WIRE (4UL << STM32_OCTOSPI_CCR_DMODE_POS) + +#define STM32_OCTOSPI_CCR_ABSIZE_POS 20U +#define STM32_OCTOSPI_CCR_ABSIZE_MSK (0x1UL << STM32_OCTOSPI_CCR_ABSIZE_POS) +#define STM32_OCTOSPI_CCR_ABSIZE_1BYTE (0UL << STM32_OCTOSPI_CCR_ABSIZE_POS) +#define STM32_OCTOSPI_CCR_ABSIZE_2BYTES (1UL << STM32_OCTOSPI_CCR_ABSIZE_POS) +#define STM32_OCTOSPI_CCR_ABSIZE_3BYTES (2UL << STM32_OCTOSPI_CCR_ABSIZE_POS) +#define STM32_OCTOSPI_CCR_ABSIZE_4BYTES (3UL << STM32_OCTOSPI_CCR_ABSIZE_POS) + +#define STM32_OCTOSPI_CCR_ABDTR_POS 19U +#define STM32_OCTOSPI_CCR_ABDTR_MSK (0x1UL << STM32_OCTOSPI_CCR_ABDTR_POS) +#define STM32_OCTOSPI_CCR_ABDTR STM32_OCTOSPI_CCR_ABDTR_MSK + +#define STM32_OCTOSPI_CCR_ABMODE_POS 16U +#define STM32_OCTOSPI_CCR_ABMODE_MSK (0x1UL << STM32_OCTOSPI_CCR_ABMODE_POS) +#define STM32_OCTOSPI_CCR_ABMODE_NONE (0UL << STM32_OCTOSPI_CCR_ABMODE_POS) +#define STM32_OCTOSPI_CCR_ABMODE_1WIRE (1UL << STM32_OCTOSPI_CCR_ABMODE_POS) +#define STM32_OCTOSPI_CCR_ABMODE_2WIRE (2UL << STM32_OCTOSPI_CCR_ABMODE_POS) +#define STM32_OCTOSPI_CCR_ABMODE_4WIRE (3UL << STM32_OCTOSPI_CCR_ABMODE_POS) +#define STM32_OCTOSPI_CCR_ABMODE_8WIRE (4UL << STM32_OCTOSPI_CCR_ABMODE_POS) + +#define STM32_OCTOSPI_CCR_ADSIZE_POS 12U +#define STM32_OCTOSPI_CCR_ADSIZE_MSK (0x1UL << STM32_OCTOSPI_CCR_ADSIZE_POS) +#define STM32_OCTOSPI_CCR_ADSIZE_1BYTE (0UL << STM32_OCTOSPI_CCR_ADSIZE_POS) +#define STM32_OCTOSPI_CCR_ADSIZE_2BYTES (1UL << STM32_OCTOSPI_CCR_ADSIZE_POS) +#define STM32_OCTOSPI_CCR_ADSIZE_3BYTES (2UL << STM32_OCTOSPI_CCR_ADSIZE_POS) +#define STM32_OCTOSPI_CCR_ADSIZE_4BYTES (3UL << STM32_OCTOSPI_CCR_ADSIZE_POS) + +#define STM32_OCTOSPI_CCR_ADDTR_POS 11U +#define STM32_OCTOSPI_CCR_ADDTR_MSK (0x1UL << STM32_OCTOSPI_CCR_ADDTR_POS) +#define STM32_OCTOSPI_CCR_ADDTR STM32_OCTOSPI_CCR_ADDTR_MSK + +#define STM32_OCTOSPI_CCR_ADMODE_POS 8U +#define STM32_OCTOSPI_CCR_ADMODE_MSK (0x1UL << STM32_OCTOSPI_CCR_ADMODE_POS) +#define STM32_OCTOSPI_CCR_ADMODE_NONE (0UL << STM32_OCTOSPI_CCR_ADMODE_POS) +#define STM32_OCTOSPI_CCR_ADMODE_1WIRE (1UL << STM32_OCTOSPI_CCR_ADMODE_POS) +#define STM32_OCTOSPI_CCR_ADMODE_2WIRE (2UL << STM32_OCTOSPI_CCR_ADMODE_POS) +#define STM32_OCTOSPI_CCR_ADMODE_4WIRE (3UL << STM32_OCTOSPI_CCR_ADMODE_POS) +#define STM32_OCTOSPI_CCR_ADMODE_8WIRE (4UL << STM32_OCTOSPI_CCR_ADMODE_POS) + +#define STM32_OCTOSPI_CCR_ISIZE_POS 4U +#define STM32_OCTOSPI_CCR_ISIZE_MSK (0x1UL << STM32_OCTOSPI_CCR_ISIZE_POS) +#define STM32_OCTOSPI_CCR_ISIZE_1BYTE (0UL << STM32_OCTOSPI_CCR_ISIZE_POS) +#define STM32_OCTOSPI_CCR_ISIZE_2BYTES (1UL << STM32_OCTOSPI_CCR_ISIZE_POS) +#define STM32_OCTOSPI_CCR_ISIZE_3BYTES (2UL << STM32_OCTOSPI_CCR_ISIZE_POS) +#define STM32_OCTOSPI_CCR_ISIZE_4BYTES (3UL << STM32_OCTOSPI_CCR_ISIZE_POS) + +#define STM32_OCTOSPI_CCR_IDTR_POS 3U +#define STM32_OCTOSPI_CCR_IDTR_MSK (0x1UL << STM32_OCTOSPI_CCR_IDTR_POS) +#define STM32_OCTOSPI_CCR_IDTR STM32_OCTOSPI_CCR_IDTR_MSK + +#define STM32_OCTOSPI_CCR_IMODE_POS 0U +#define STM32_OCTOSPI_CCR_IMODE_MSK (0x1UL << STM32_OCTOSPI_CCR_IMODE_POS) +#define STM32_OCTOSPI_CCR_IMODE_NONE (0UL << STM32_OCTOSPI_CCR_IMODE_POS) +#define STM32_OCTOSPI_CCR_IMODE_1WIRE (1UL << STM32_OCTOSPI_CCR_IMODE_POS) +#define STM32_OCTOSPI_CCR_IMODE_2WIRE (2UL << STM32_OCTOSPI_CCR_IMODE_POS) +#define STM32_OCTOSPI_CCR_IMODE_4WIRE (3UL << STM32_OCTOSPI_CCR_IMODE_POS) +#define STM32_OCTOSPI_CCR_IMODE_8WIRE (4UL << STM32_OCTOSPI_CCR_IMODE_POS) + +/* Bit values for STM32_OCTOSPI_TCR */ +#define STM32_OCTOSPI_TCR_SSHIFT_POS 30U +#define STM32_OCTOSPI_TCR_SSHIFT_MSK (0x1UL << STM32_OCTOSPI_TCR_SSHIFT_POS) +#define STM32_OCTOSPI_TCR_SSHIFT STM32_OCTOSPI_TCR_SSHIFT_MSK + +#define STM32_OCTOSPI_TCR_DHQC_POS 28U +#define STM32_OCTOSPI_TCR_DHQC_MSK (0x1UL << STM32_OCTOSPI_TCR_DHQC_POS) +#define STM32_OCTOSPI_TCR_DHQC STM32_OCTOSPI_TCR_DHQC_MSK + +#define STM32_OCTOSPI_TCR_DCYC_POS 0U +#define STM32_OCTOSPI_TCR_DCYC_MSK (0x1FUL << STM32_OCTOSPI_TCR_DCYC_POS) + #endif /* !__ASSEMBLER__ */ |