zephyr: shim in power sequencing

Enable shimming of power sequencing code.

BUG=b:171312361
BRANCH=none
TEST=With zephyr-chrome CL...
     https://screenshot.googleplex.com/4m6N6vd2Nx5FpiD.png

Signed-off-by: Jack Rosenthal <jrosenth@chromium.org>
Change-Id: I8fb96019c8c636010d2cd136c0116df41fc9f148
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2548308

6 files changed, 132 insertions, 2 deletions

diff --git a/power/common.c b/power/common.c
index 054206519f..637a367854 100644
--- a/power/common.c
+++ b/power/common.c
@@ -1005,7 +1005,7 @@ __overridable void board_power_5v_enable(int enable)
 
 /* 5V enable request bitmask from various tasks. */
 static uint32_t pwr_5v_en_req;
-static struct mutex pwr_5v_ctl_mtx;
+static mutex_t pwr_5v_ctl_mtx;
 
 void power_5v_enable(task_id_t tid, int enable)
 {
@@ -1030,6 +1030,12 @@ static void restore_enable_5v_state(void)
 	const uint32_t *state;
 	int size;
 
+	/*
+	 * Initialize the mutex for ZephyrOS.
+	 * This does nothing for non-Zephyr builds.
+	 */
+	(void)k_mutex_init(&pwr_5v_ctl_mtx);
+
 	state = (const uint32_t *) system_get_jump_tag(P5_SYSJUMP_TAG, 0,
 						       &size);
 	if (state && size == sizeof(pwr_5v_en_req)) {
diff --git a/power/intel_x86.c b/power/intel_x86.c
index 1fdf1b96ea..893e9fbf4e 100644
--- a/power/intel_x86.c
+++ b/power/intel_x86.c
@@ -388,7 +388,12 @@ enum power_state common_intel_x86_power_handle_state(enum power_state state)
 		/* Enable wireless */
 		wireless_set_state(WIRELESS_ON);
 
-		lpc_s3_resume_clear_masks();
+		/*
+		 * TODO(b/172678200): this function hasn't been
+		 * shimmed to Zephyr yet
+		 */
+		if (!IS_ENABLED(CONFIG_ZEPHYR))
+			lpc_s3_resume_clear_masks();
 
 		/* Call hooks now that rails are up */
 		hook_notify(HOOK_CHIPSET_RESUME);
diff --git a/zephyr/CMakeLists.txt b/zephyr/CMakeLists.txt
index 7aeeaa6d28..e0f53e39fc 100644
--- a/zephyr/CMakeLists.txt
+++ b/zephyr/CMakeLists.txt
@@ -49,5 +49,13 @@ zephyr_sources_ifdef(CONFIG_PLATFORM_EC_LID_SWITCH
                                                 "${PLATFORM_EC}/common/lid_switch.c")
 zephyr_sources_ifdef(CONFIG_PLATFORM_EC_POWER_BUTTON
                                                 "${PLATFORM_EC}/common/power_button.c")
+zephyr_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_INTEL
+                                                "${PLATFORM_EC}/common/power_button_x86.c")
 zephyr_sources_ifdef(CONFIG_PLATFORM_EC         "${PLATFORM_EC}/common/queue.c")
 zephyr_sources_ifdef(CONFIG_PLATFORM_EC_TIMER   "${PLATFORM_EC}/common/timer.c")
+zephyr_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ
+                                                "${PLATFORM_EC}/power/common.c")
+zephyr_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_INTEL
+                                                "${PLATFORM_EC}/power/intel_x86.c")
+zephyr_sources_ifdef(CONFIG_PLATFORM_EC_POWERSEQ_ICELAKE
+                                                "${PLATFORM_EC}/power/icelake.c")
diff --git a/zephyr/Kconfig b/zephyr/Kconfig
index fb1c4bfb0f..03db724612 100644
--- a/zephyr/Kconfig
+++ b/zephyr/Kconfig
@@ -12,6 +12,8 @@ menuconfig PLATFORM_EC
 
 if PLATFORM_EC
 
+rsource "Kconfig.powerseq"
+
 # Below is a hack to use CONFIG_ZEPHYR in platform/ec code before
 # config.h has been included.  There is some tricky ordering in some
 # header files that we cannot use config.h (e.g., common.h and
diff --git a/zephyr/Kconfig.powerseq b/zephyr/Kconfig.powerseq
new file mode 100644
index 0000000000..81935cdace
--- /dev/null
+++ b/zephyr/Kconfig.powerseq
@@ -0,0 +1,80 @@
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+menuconfig PLATFORM_EC_POWERSEQ
+	bool "Enable power sequencing"
+	depends on AP
+	help
+	  Enable shimming the platform/ec AP power sequencing code.
+
+if PLATFORM_EC_POWERSEQ
+
+menuconfig PLATFORM_EC_POWERSEQ_INTEL
+	bool "Enable shimming common Intel power sequencing code"
+	depends on AP_X86_INTEL
+	default y
+	help
+	  Enable shimming platform/ec AP power sequencing code for
+	  Intel.
+
+if PLATFORM_EC_POWERSEQ_INTEL
+
+config PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW
+	bool "The CPU_PROCHOT signal is an active low signal"
+	default y
+	help
+	  If CPU_PROCHOT should be treated as active-low, enable this
+	  configuration option.
+
+config PLATFORM_EC_POWERSEQ_PP5000_CONTROL
+	bool "Enable a task-safe way to control the PP5000 rail"
+	default y
+	help
+	  Guard access to the PP5000 GPIO using mutex locks, allowing
+	  the rail to be changed in a task-safe manner.
+
+config PLATFORM_EC_POWERSEQ_RSMRST_DELAY
+	bool "Wait at least 10ms before deasserting RSMRST to PCH"
+	default y if AP_X86_INTEL_TGL
+	help
+	  Wait at least 10ms between power signals going high and
+	  deasserting RSMRST to PCH.
+
+config PLATFORM_EC_POWERSEQ_RTC_RESET
+	bool "Board has an RTC reset"
+	help
+	  This project has a gpio named GPIO_PCH_RTCRST defined in
+	  gpio_map.h, which can be used to reset the AP's RTC when set
+	  high.
+
+menuconfig PLATFORM_EC_POWERSEQ_ICELAKE
+	bool "Use common Icelake code for power sequencing"
+	default y if AP_X86_INTEL_TGL
+	default y if AP_X86_INTEL_ADL
+	help
+	  Use the Icelake common code for power sequencing.  Note that
+	  this applies to more platforms than just Icelake.  For
+	  example, Tigerlake uses this code too.
+
+if PLATFORM_EC_POWERSEQ_ICELAKE
+
+config PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE
+	bool "Enable a quirk to release SLP_S3_L after DSW_PWROK is high"
+	default y if AP_X86_INTEL_TGL
+	help
+	  Enable a quirk to reconfigure SLP_S3_L back to an input a
+	  short delay after DSW_PWROK goes high.
+
+config PLATFORM_EC_POWERSEQ_PP3300_RAIL_FIRST
+	bool "Turn on the PP3300 rail before PP5000"
+	default y if AP_X86_INTEL_TGL
+	help
+	  When switching from G3 to S5, turn on the PP3300 rail before
+	  the PP5500 rail.
+
+endif # PLATFORM_EC_POWERSEQ_ICELAKE
+
+endif # PLATFORM_EC_POWERSEQ_INTEL
+
+endif # PLATFORM_EC_POWERSEQ
diff --git a/zephyr/shim/include/config_chip.h b/zephyr/shim/include/config_chip.h
index 8995edd68b..e673630cb6 100644
--- a/zephyr/shim/include/config_chip.h
+++ b/zephyr/shim/include/config_chip.h
@@ -21,6 +21,35 @@
 #define CONFIG_ZEPHYR
 #define CHROMIUM_EC
 
+/* Chipset and power configuration */
+#ifdef CONFIG_AP_X86_INTEL_TGL
+#define CONFIG_CHIPSET_TIGERLAKE
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_CPU_PROCHOT_ACTIVE_LOW
+#define CONFIG_CHIPSET_CPU_PROCHOT_ACTIVE_LOW
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_RSMRST_DELAY
+#define CONFIG_CHIPSET_X86_RSMRST_DELAY
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_SLP_S3_L_OVERRIDE
+#define CONFIG_CHIPSET_SLP_S3_L_OVERRIDE
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_PP3300_RAIL_FIRST
+#define CONFIG_CHIPSET_PP3300_RAIL_FIRST
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_RTC_RESET
+#define CONFIG_BOARD_HAS_RTC_RESET
+#endif
+
+#ifdef CONFIG_PLATFORM_EC_POWERSEQ_PP5000_CONTROL
+#define CONFIG_POWER_PP5000_CONTROL
+#endif
+
 #ifdef CONFIG_PLATFORM_EC_TIMER
 #define CONFIG_HWTIMER_64BIT
 #define CONFIG_HW_SPECIFIC_UDELAY