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authorNicolas Boichat <drinkcat@chromium.org>2021-01-06 10:21:43 +0800
committerCommit Bot <commit-bot@chromium.org>2021-01-11 04:03:37 +0000
commit23073aa336343ab0a2fec8e60a861a07d40d2f7d (patch)
tree28c8c57348a5b0ea3f0b9d37787d65ffe6f5036c
parent034be0ff1c2ff20a92dac94662e9302595043b0b (diff)
downloadchrome-ec-23073aa336343ab0a2fec8e60a861a07d40d2f7d.tar.gz
core/riscv-rv32i: Use -fsanitize-undefined-trap-on-error
Let's use -fsanitize-undefined-trap-on-error instead, to trap division by zero. This only adds 2 instructions to each division (a branch and an ebreak). BRANCH=none BUG=b:173969773 TEST=crash divzero crashes asurada TEST=tast run -var servo=localhost:9999 dut9999 crash.ECCrash passes Change-Id: I50d6016d457089ddcb105026656e1bf09bd1df81 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2612226 Commit-Queue: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@chromium.org>
-rw-r--r--core/riscv-rv32i/build.mk6
-rw-r--r--core/riscv-rv32i/math.c8
2 files changed, 3 insertions, 11 deletions
diff --git a/core/riscv-rv32i/build.mk b/core/riscv-rv32i/build.mk
index df4e5e7ca9..34f059e70c 100644
--- a/core/riscv-rv32i/build.mk
+++ b/core/riscv-rv32i/build.mk
@@ -15,9 +15,9 @@ _FPU_EXTENSION=$(if $(CONFIG_FPU),f,)
# CPU specific compilation flags
CFLAGS_CPU+=-march=rv32ima$(_FPU_EXTENSION)c -mabi=ilp32$(_FPU_EXTENSION) -Os
# RISC-V does not trap division by zero, enable the sanitizer to check those.
-# TODO(b:173969773): It might be better to add a new compiler flag for this
-# (e.g. -mcheck-zero-division that is only only available on MIPS currently).
-CFLAGS_CPU+=-fsanitize=integer-divide-by-zero
+# With `-fsanitize-undefined-trap-on-error`, we lose a bit of specificity on the
+# exact issue, but the added code is as small as it gets.
+CFLAGS_CPU+=-fsanitize=integer-divide-by-zero -fsanitize-undefined-trap-on-error
LDFLAGS_EXTRA+=-mrelax
LDFLAGS_EXTRA+=-static-libgcc -lgcc
diff --git a/core/riscv-rv32i/math.c b/core/riscv-rv32i/math.c
index 2a637c8bcc..591a67eb8f 100644
--- a/core/riscv-rv32i/math.c
+++ b/core/riscv-rv32i/math.c
@@ -4,8 +4,6 @@
*/
#include "common.h"
-#include "cpu.h"
-#include "panic.h"
#ifdef CONFIG_FPU
/* Single precision floating point square root. */
@@ -19,9 +17,3 @@ float sqrtf(float x)
return x;
}
#endif
-
-void __ubsan_handle_divrem_overflow(void *data,
- void *lhs, void *rhs)
-{
- exception_panic(PANIC_SW_DIV_ZERO, 0);
-}