diff options
| author | Caveh Jalali <caveh@chromium.org> | 2021-02-08 21:46:34 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-02-16 00:57:29 +0000 |
| commit | f1baecae5df8068ef4ee3b0d0f99659de47e7d71 (patch) | |
| tree | eb052fec45cbfcc03c4a8e2590ab88a98c1e3c13 | |
| parent | ea99e40f31445e67659c09b32cab6857cad8b83e (diff) | |
| download | chrome-ec-f1baecae5df8068ef4ee3b0d0f99659de47e7d71.tar.gz | |
brya: Enable chipset support
This enables support for the Alder Lake chipset using the SLG4BD44540
power sequencer.
BRANCH=none
BUG=b:173575131
TEST=buildall passes
Change-Id: I6718bf5500286cee0616024b27939198bcba3b5b
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2686980
| -rw-r--r-- | baseboard/brya/baseboard.h | 7 | ||||
| -rw-r--r-- | board/brya/board.h | 14 | ||||
| -rw-r--r-- | board/brya/ec.tasklist | 1 |
3 files changed, 22 insertions, 0 deletions
diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h index ad0f4fc1e7..ceb2e2a54e 100644 --- a/baseboard/brya/baseboard.h +++ b/baseboard/brya/baseboard.h @@ -24,6 +24,10 @@ #define CONFIG_EXTPOWER_GPIO +/* Host communication */ +#define CONFIG_HOSTCMD_ESPI +#define CONFIG_HOSTCMD_ESPI_VW_SLP_S4 + /* Common battery defines */ #define CONFIG_BATTERY_SMART #define CONFIG_BATTERY_FUEL_GAUGE @@ -32,6 +36,9 @@ #define CONFIG_BATTERY_HW_PRESENT_CUSTOM #define CONFIG_BATTERY_REVIVE_DISCONNECT +/* Chipset config */ +#define CONFIG_CHIPSET_ALDERLAKE_SLG4BD44540 + #define CONFIG_PWM /* Enable I2C Support */ diff --git a/board/brya/board.h b/board/brya/board.h index 414e503cf2..399e55de25 100644 --- a/board/brya/board.h +++ b/board/brya/board.h @@ -23,8 +23,22 @@ #define CONFIG_IO_EXPANDER_PORT_COUNT 2 #define GPIO_AC_PRESENT GPIO_ACOK_EC_OD +#define GPIO_CPU_PROCHOT GPIO_EC_PROCHOT_ODL #define GPIO_ENTERING_RW GPIO_EC_ENTERING_RW #define GPIO_LID_OPEN GPIO_LID_OPEN_OD +#define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L +#define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L +/* + * GPIO_EC_PCH_INT_ODL is used for MKBP events as well as a PCH wakeup + * signal. + */ +#define GPIO_PCH_WAKE_L GPIO_EC_PCH_INT_ODL +#define GPIO_PG_EC_ALL_SYS_PWRGD GPIO_SEQ_EC_ALL_SYS_PG +#define GPIO_PG_EC_DSW_PWROK GPIO_SEQ_EC_DSW_PWROK +#define GPIO_PG_EC_RSMRST_ODL GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_RSMRST_L_PGOOD GPIO_SEQ_EC_RSMRST_ODL +#define GPIO_SYS_RESET_L GPIO_SYS_RST_ODL #define GPIO_WP_L GPIO_EC_WP_ODL #define CONFIG_FANS FAN_CH_COUNT diff --git a/board/brya/ec.tasklist b/board/brya/ec.tasklist index 773d62c8cb..a12286148d 100644 --- a/board/brya/ec.tasklist +++ b/board/brya/ec.tasklist @@ -9,5 +9,6 @@ #define CONFIG_TASK_LIST \ TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \ + TASK_NOTEST(CHIPSET, chipset_task, NULL, LARGER_TASK_STACK_SIZE) \ TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \ TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) |