stm32g4: Add USB endpoint support

This CL enables USB-EP for the STM32G4 family. It also fixes backup
domain register access issues which are required for fw updates via
USB.

BUG=b:148493929
BRANCH=None
TEST=Verified on quiche that STM32G4 enumerates as an USB endpoint and
can be used successfully with fwupd.

Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I75e6b6e70e9ca2589ace76f0aa0facadd9e94142
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2268139
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>

5 files changed, 56 insertions, 4 deletions

diff --git a/chip/stm32/clock-stm32g4.c b/chip/stm32/clock-stm32g4.c
index 941cb94327..94936b932f 100644
--- a/chip/stm32/clock-stm32g4.c
+++ b/chip/stm32/clock-stm32g4.c
@@ -119,6 +119,8 @@ static void stm32g4_config_low_speed_clock(void)
 	wait_for_ready(&(STM32_RCC_CSR),
 		STM32_RCC_CSR_LSION, STM32_RCC_CSR_LSIRDY);
 
+	/* Setup RTC Clock input */
+	STM32_RCC_BDCR |= STM32_RCC_BDCR_BDRST;
 	STM32_RCC_BDCR = STM32_RCC_BDCR_RTCEN | BDCR_RTCSEL(BDCR_SRC_LSI);
 }
 
diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h
index da42faf2c3..28bea1ebb1 100644
--- a/chip/stm32/config-stm32g41xb.h
+++ b/chip/stm32/config-stm32g41xb.h
@@ -56,3 +56,9 @@
 
 /* Number of IRQ vectors on the NVIC */
 #define CONFIG_IRQ_COUNT	101
+
+/* USB packet ram config */
+#define CONFIG_USB_RAM_BASE        0x40006000
+#define CONFIG_USB_RAM_SIZE        1024
+#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
+#define CONFIG_USB_RAM_ACCESS_SIZE 2
diff --git a/chip/stm32/registers-stm32g4.h b/chip/stm32/registers-stm32g4.h
index cf4306984b..12d2c7ff40 100644
--- a/chip/stm32/registers-stm32g4.h
+++ b/chip/stm32/registers-stm32g4.h
@@ -141,7 +141,7 @@
 #define STM32_I2C1_BASE             STM32_APB1PERIPH(0x5400UL)
 #define STM32_I2C2_BASE             STM32_APB1PERIPH(0x5800UL)
 /* USB_IP Peripheral Registers base address */
-#define STM32_USB_BASE              STM32_APB1PERIPH(0x5C00UL)
+#define STM32_USB_FS_BASE           STM32_APB1PERIPH(0x5C00UL)
 /* USB_IP Packet Memory Area base address */
 #define STM32_USB_PMAADDR           STM32_APB1PERIPH(0x6000UL)
 #define STM32_FDCAN1_BASE           STM32_APB1PERIPH(0x6400UL)
@@ -154,6 +154,7 @@
 #define STM32_I2C4_BASE             STM32_APB1PERIPH(0x8400UL)
 /* UART9 is used as link to LPUART in STM32 uart.c implementation */
 #define STM32_USART9_BASE           STM32_APB1PERIPH(0x8000UL)
+#define STM32_I2C4_BASE             STM32_APB1PERIPH(0x8400UL)
 #define STM32_UCPD1_BASE            STM32_APB1PERIPH(0xA000UL)
 #define STM32_SRAMCAN_BASE          STM32_APB1PERIPH(0xA400UL)
 
@@ -587,7 +588,8 @@
 #define STM32_RCC_AHB1RSTR              REG32(STM32_RCC_BASE + 0x28)
 #define STM32_RCC_AHB2RSTR              REG32(STM32_RCC_BASE + 0x2C)
 #define STM32_RCC_AHB3RSTR              REG32(STM32_RCC_BASE + 0x30)
-#define STM32_RCC_APB1RSTR              REG32(STM32_RCC_BASE + 0x38)
+#define STM32_RCC_APB1RSTR1             REG32(STM32_RCC_BASE + 0x38)
+#define STM32_RCC_APB1RSTR2             REG32(STM32_RCC_BASE + 0x3C)
 #define STM32_RCC_APB2RSTR              REG32(STM32_RCC_BASE + 0x40)
 #define STM32_RCC_AHB1ENR               REG32(STM32_RCC_BASE + 0x48)
 #define STM32_RCC_AHB2ENR               REG32(STM32_RCC_BASE + 0x4C)
@@ -721,6 +723,11 @@
 /* gpio.c needs STM32_RCC_SYSCFGEN */
 #define STM32_RCC_SYSCFGEN STM32_RCC_APB2ENR_SYSCFGEN
 
+/* --- RCC APB1RSTR1 Bit Definitions --- */
+#define STM32_RCC_APB1RSTR1_USB_RST     BIT(23)
+#define STM32_RCC_APB1RSTR              STM32_RCC_APB1RSTR1
+#define STM32_RCC_PB1_USB               STM32_RCC_APB1RSTR1_USB_RST
+
 /* --- RCC CSR Bit Definitions --- */
 #define STM32_RCC_CSR_LSION		BIT(0)
 #define STM32_RCC_CSR_LSIRDY		BIT(1)
@@ -786,6 +793,8 @@
 #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_SCR
 #define  RESET_CAUSE_SBF_CLR            STM32_PWR_SCR_CSBF
 
+#define STM32_PWR_CR1_DBP               BIT(8)
+
 #define STM32_PWR_CR3_UCPD1_STDBY       BIT(13)
 #define STM32_PWR_CR3_UCPD1_DBDIS       BIT(14)
 
@@ -838,7 +847,7 @@
 /* --- Tamper and Backup --- */
 #define STM32_TAMP_BKPxR(n)         REG32(STM32_TAMP_BASE + 0x100 + 4 * (n))
 #define STM32_BKP_DATA(n)           STM32_TAMP_BKPxR(n)
-#define STM32_BKP_BYTES             128
+#define STM32_BKP_BYTES             64
 
 
 /* --- SPI --- */
@@ -1416,6 +1425,7 @@ enum dmamux1_request {
 #define STM32_USB_BCDR_PDET	    BIT(5)
 #define STM32_USB_BCDR_SDET	    BIT(6)
 #define STM32_USB_BCDR_PS2DET	    BIT(7)
+#define STM32_USB_BCDR_DPPU	    BIT(15)
 
 /* --- USB Endpoint bit definitions  --- */
 #define EP_MASK     0x0F0F
diff --git a/chip/stm32/system.c b/chip/stm32/system.c
index 0304c7b3be..42525deb48 100644
--- a/chip/stm32/system.c
+++ b/chip/stm32/system.c
@@ -280,6 +280,13 @@ void system_pre_init(void)
 	/* Wait for LSI to be ready */
 	while (!(STM32_RCC_CSR & BIT(1)))
 		;
+
+#if defined(CHIP_FAMILY_STM32G4)
+	/* Make sure PWR clock is enabled */
+	STM32_RCC_APB1ENR1 |= STM32_RCC_APB1ENR1_PWREN;
+	/* Enable access to backup domain registers */
+	STM32_PWR_CR1 |= STM32_PWR_CR1_DBP;
+#endif
 	/* re-configure RTC if needed */
 #ifdef CHIP_FAMILY_STM32L
 	if ((STM32_RCC_CSR & 0x00C30000) != 0x00420000) {
@@ -399,7 +406,7 @@ void system_reset(int flags)
 		 * use this for hard reset.
 		 */
 		STM32_FLASH_CR |= FLASH_CR_OBL_LAUNCH;
-#elif defined(CHIP_FAMILY_STM32L4)
+#elif defined(CHIP_FAMILY_STM32L4) || defined(CHIP_FAMILY_STM32G4)
 		STM32_FLASH_KEYR = FLASH_KEYR_KEY1;
 		STM32_FLASH_KEYR = FLASH_KEYR_KEY2;
 		STM32_FLASH_OPTKEYR = FLASH_OPTKEYR_KEY1;
diff --git a/chip/stm32/usb-stm32g4.c b/chip/stm32/usb-stm32g4.c
new file mode 100644
index 0000000000..b4402f670d
--- /dev/null
+++ b/chip/stm32/usb-stm32g4.c
@@ -0,0 +1,27 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ *
+ * STM32G4 Family specific USB functionality
+ */
+
+#include "registers.h"
+#include "system.h"
+#include "usb_api.h"
+
+void usb_connect(void)
+{
+	/* USB is in use */
+	disable_sleep(SLEEP_MASK_USB_DEVICE);
+
+	STM32_USB_BCDR |= STM32_USB_BCDR_DPPU;
+}
+
+void usb_disconnect(void)
+{
+	/* disable pull-up on DP to disconnect */
+	STM32_USB_BCDR &= ~STM32_USB_BCDR_DPPU;
+
+	/* USB is off, so sleep whenever */
+	enable_sleep(SLEEP_MASK_USB_DEVICE);
+}