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| author | Caveh Jalali <caveh@chromium.org> | 2021-03-04 17:02:57 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-05 08:25:10 +0000 |
| commit | 631392f8c7fb2a810465b1f53c8bbfd00bd2946c (patch) | |
| tree | 53ca1eaa0188d6f102990da5e02913ee888f68e5 | |
| parent | af96d6ad9f767dd223ede76fb58b7461b515b494 (diff) | |
| download | chrome-ec-631392f8c7fb2a810465b1f53c8bbfd00bd2946c.tar.gz | |
brya: Enable RTC reset
This enables the RTC reset feature of the SoC.
BRANCH=none
BUG=b:173575131
TEST=buildall passes
Change-Id: I29f7599fea831dd5751c5609b4e974059a8be2e7
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2738918
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
| -rw-r--r-- | baseboard/brya/baseboard.h | 2 | ||||
| -rw-r--r-- | board/brya/board.h | 1 |
2 files changed, 3 insertions, 0 deletions
diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h index a98e125d46..3a91cae866 100644 --- a/baseboard/brya/baseboard.h +++ b/baseboard/brya/baseboard.h @@ -51,6 +51,8 @@ #define CONFIG_POWER_SLEEP_FAILURE_DETECTION #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE +#define CONFIG_BOARD_HAS_RTC_RESET + /* Thermal features */ #define CONFIG_THROTTLE_AP diff --git a/board/brya/board.h b/board/brya/board.h index 37ef956c7c..36603a4387 100644 --- a/board/brya/board.h +++ b/board/brya/board.h @@ -37,6 +37,7 @@ #define GPIO_LID_OPEN GPIO_LID_OPEN_OD #define GPIO_PCH_PWRBTN_L GPIO_EC_PCH_PWR_BTN_ODL #define GPIO_PCH_RSMRST_L GPIO_EC_PCH_RSMRST_L +#define GPIO_PCH_RTCRST GPIO_EC_PCH_RTCRST #define GPIO_PCH_SLP_S0_L GPIO_SYS_SLP_S0IX_L #define GPIO_PCH_SLP_S3_L GPIO_SLP_S3_L /* |