mancomb: Create mancomb baseboard and variant

This is a full copy paste of guybrush just with guybrush replaced with
mancomb. Follow up CLs will make required changes so it's clear what
changed between guybrush and mancomb.

BUG=b:174424094, b:181510382
TEST=Build
BRANCH=None

Change-Id: I16f00e2749ab466e619b77925b25b275aca67a6c
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2727634
Reviewed-by: Diana Z <dzigterman@chromium.org>

11 files changed, 1606 insertions, 0 deletions

diff --git a/baseboard/mancomb/base_ec.tasklist b/baseboard/mancomb/base_ec.tasklist
new file mode 100644
index 0000000000..5226e071a5
--- /dev/null
+++ b/baseboard/mancomb/base_ec.tasklist
@@ -0,0 +1,25 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#define BASEBOARD_CONFIG_TASK_LIST \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHG_RAMP, chg_ramp_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P0, usb_charger_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(USB_CHG_P1, usb_charger_task, 1, TASK_STACK_SIZE) \
+	TASK_ALWAYS(CHARGER, charger_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(CHIPSET, chipset_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(POWERBTN, power_button_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, LARGER_TASK_STACK_SIZE) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C0, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_C1, pd_task, NULL, VENTI_TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C0, pd_interrupt_handler_task, 0, TASK_STACK_SIZE) \
+	TASK_ALWAYS(PD_INT_C1, pd_interrupt_handler_task, 1, TASK_STACK_SIZE)
diff --git a/baseboard/mancomb/base_gpio.inc b/baseboard/mancomb/base_gpio.inc
new file mode 100644
index 0000000000..935c34511b
--- /dev/null
+++ b/baseboard/mancomb/base_gpio.inc
@@ -0,0 +1,155 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* GSC Signals */
+GPIO_INT(EC_WP_L,		PIN(5, 0), GPIO_INT_BOTH,			switch_interrupt)	/* Write Protect Enabled */
+GPIO(CCD_MODE_ODL,		PIN(C, 6), GPIO_INPUT)							/* Case Closed Debug Mode */
+GPIO(EC_GSC_PACKET_MODE,	PIN(B, 1), GPIO_OUT_LOW)						/* GSC Packet Mode */
+ALTERNATE(			PIN_MASK(6, BIT(4) | BIT(5)), 0,		MODULE_UART, 0) 	/* UART_EC_TX_GSC_DBG_RX_R, UART_GSC_DBG_TX_EC_RX_R */
+
+/* Power Signals */
+GPIO_INT(MECH_PWR_BTN_ODL,	PIN(D, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_LOW, 	power_button_interrupt)	/* Mechanical Power Button */
+GPIO_INT(EC_PWR_BTN_ODL,	PIN(0, 1), GPIO_INT_BOTH, 			power_button_interrupt) /* Power Button */
+GPIO_INT(SLP_S3_L,		PIN(6, 1), GPIO_INT_BOTH,			baseboard_en_pwr_s0)	/* Sleep S3 */
+GPIO_INT(SLP_S5_L,		PIN(7, 2), GPIO_INT_BOTH,			power_signal_interrupt) /* Sleep S5 */
+GPIO_INT(SLP_S3_S0I3_L,		PIN(7, 4), GPIO_INT_BOTH,			power_signal_interrupt) /* Sleep S0ix */
+GPIO_INT(PG_PWR_S5,		PIN(C, 0), GPIO_INT_BOTH,			baseboard_en_pwr_s0)	/* S5 Power OK */
+GPIO_INT(PG_PCORE_S0_R_OD,		PIN(B, 6), GPIO_INT_BOTH, 			power_signal_interrupt) /* S0 Power OK */
+GPIO_INT(ACOK_OD,		PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	extpower_interrupt)	/* AC Power Present */
+GPIO_INT(EC_PCORE_INT_ODL,	PIN(F, 0), GPIO_INT_BOTH | GPIO_PULL_UP,	power_signal_interrupt)	/* Power Core Interrupt */
+GPIO_INT(PG_GROUPC_S0_OD,	PIN(A, 3), GPIO_INT_BOTH, 			baseboard_en_pwr_pcore_s0)	/* Power Group C S0 */
+GPIO_INT(PG_LPDDR4X_S3_OD,	PIN(9, 5), GPIO_INT_BOTH, 			baseboard_en_pwr_pcore_s0)	/* Power Group LPDDR4 S3 */
+GPIO(EN_PWR_S5,			PIN(B, 7), GPIO_OUT_LOW)						/* Enable S5 Power */
+GPIO(EN_PWR_S0_R,		PIN(F, 1), GPIO_OUT_LOW)
+GPIO(EN_PWR_Z1,			PIN(8, 5), GPIO_OUT_LOW)						/* Enable Z1 Power */
+GPIO(EN_PWR_PCORE_S0_R,		PIN(E, 1), GPIO_OUT_LOW)
+ALTERNATE(/*MECH_PWR_BTN_ODL*/	PIN_MASK(D, BIT(2)), 0,				MODULE_PMU, 0)		/* PSL - Mechanical Power Button */
+ALTERNATE(/*LID_OPEN*/		PIN_MASK(0, BIT(2)), 0, 			MODULE_PMU, 0)		/* PSL - Lid Open */
+ALTERNATE(/*ACOK_OD*/		PIN_MASK(0, BIT(0)), 0,				MODULE_PMU, 0)		/* PSL - AC Power Present */
+
+/* SOC Signals */
+UNIMPLEMENTED(ENTERING_RW) 										/* GPIO_ENTERING_RW */
+GPIO(EC_SYS_RST_L,		PIN(7, 6), GPIO_ODR_HIGH)						/* Cold Reset SOC */
+GPIO(EC_SOC_RSMRST_L,		PIN(C, 5), GPIO_OUT_LOW)						/* Resume Reset SOC */
+GPIO(EC_CLR_CMOS,		PIN(A, 1), GPIO_OUT_LOW)						/* Clear SOC CMOS */
+GPIO(EC_MEM_EVENT,		PIN(A, 5), GPIO_OUT_LOW)						/* Memory Thermal Event to SOC*/
+GPIO(EC_SOC_PWR_BTN_L,		PIN(6, 3), GPIO_OUT_HIGH)						/* Power Button to SOC */
+GPIO(EC_SOC_PWR_GOOD,		PIN(D, 3), GPIO_OUT_LOW)						/* Power Good to SOC */
+GPIO(EC_SOC_WAKE_L,		PIN(0, 3), GPIO_OUT_HIGH)						/* Wake SOC */
+GPIO(EC_SOC_INT_L,		PIN(8, 3), GPIO_OUT_HIGH)						/* Matrix Keyboard Protocol Event to SOC */
+GPIO(PROCHOT_ODL,		PIN(D, 5), GPIO_ODR_HIGH)						/* Force SOC into HTC-active state */
+GPIO(SOC_ALERT_EC_L,		PIN(E, 2), GPIO_INPUT)							/* Sideband-Temperature Iterrupt */
+GPIO(SOC_THERMTRIP_ODL, 	PIN(E, 5), GPIO_INPUT)							/* Temperature Trip Sensor */
+
+/* USB Signals */
+GPIO_INT(USB_C0_TCPC_INT_ODL,	PIN(E, 0), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C1_TCPC_INT_ODL,	PIN(C, 7), GPIO_INT_FALLING,			tcpc_alert_event)
+GPIO_INT(USB_C0_PPC_INT_ODL,	PIN(7, 5), GPIO_INT_FALLING,			ppc_interrupt)
+GPIO_INT(USB_C1_PPC_INT_ODL,	PIN(D, 4), GPIO_INT_FALLING,			ppc_interrupt)
+GPIO_INT(USB_C0_BC12_INT_ODL,	PIN(A, 4), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
+GPIO_INT(USB_C1_BC12_INT_ODL, 	PIN(9, 6), GPIO_INT_FALLING | GPIO_PULL_UP,	bc12_interrupt)
+GPIO(USB_C0_C1_FAULT_ODL,	PIN(7, 3), GPIO_ODR_HIGH)						/* C0/C1 Fault to SOC */
+GPIO(USB_C0_TCPC_RST_L,		PIN(3, 4), GPIO_OUT_HIGH)						/* C0 TCPC Reset */
+GPIO(USB_C1_TCPC_RST_L,		PIN(3, 7), GPIO_OUT_HIGH)						/* C1 TCPC Reset */
+GPIO(USB_C0_HPD,		PIN(F, 5), GPIO_OUT_LOW)						/* C0 DP Hotplug Detect */
+GPIO(USB_C1_HPD,		PIN(F, 4), GPIO_OUT_LOW)						/* C1 DP Hotplug Detect */
+
+/* Sensor Signals */
+/* TODO: Make 6AXIS_INT_L an interrupt */
+GPIO(6AXIS_INT_L,		PIN(A, 0), GPIO_INT_FALLING | GPIO_PULL_UP)				/* 6 Axis IMU */
+GPIO(3AXIS_INT_L,		PIN(A, 2), GPIO_INPUT | GPIO_PULL_DOWN)					/* 3 Axis Accel */
+GPIO_INT(LID_OPEN,		PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH,	lid_interrupt)		/* Lid Open */
+GPIO_INT(TABLET_MODE,		PIN(C, 1), GPIO_INT_BOTH,			gmr_tablet_switch_isr)	/* 360 Tablet Mode */
+GPIO_INT(VOLDN_BTN_ODL,		PIN(A, 7), GPIO_INT_BOTH | GPIO_PULL_UP,	button_interrupt)	/* Volume Down */
+GPIO_INT(VOLUP_BTN_ODL,		PIN(9, 3), GPIO_INT_BOTH | GPIO_PULL_UP, 	button_interrupt)	/* Volume Up */
+GPIO(EC_BATT_PRES_ODL,		PIN(9, 4), GPIO_INPUT | GPIO_PULL_UP)					/* Battery Present */
+ALTERNATE(/*TEMP_SOC|CHRG|MEM*/	PIN_MASK(4, BIT(3) | BIT(4) | BIT(5)), 0, 	MODULE_PWM, 0)		/* SOC, Charger and Memory Temperature */
+ALTERNATE(			PIN_MASK(4, BIT(1) | BIT(2)), 0,		MODULE_PWM, 0)		/* EC_ADC_CORE_IMON1, EC_ADC_SOC_IMON2 */
+
+/* LED Signals */
+GPIO(EC_DISABLE_DISP_BL,	PIN(A, 6), GPIO_OUT_HIGH)						/* Disable Display Backlight */
+ALTERNATE(/*EC_PWM_LED_CHRG_L*/	PIN_MASK(C, BIT(4)), 0, 			MODULE_PWM, 0)		/* Charging LED */
+ALTERNATE(/*EC_PWM_LED_FULL_L*/	PIN_MASK(8, BIT(0)), 0, 			MODULE_PWM, 0)		/* Full LED */
+
+/* Fan Signals */
+ALTERNATE(			PIN_MASK(C, BIT(3)), 0, 			MODULE_PWM, 0)		/* EC_FAN_PWM - Fan PWM */
+ALTERNATE(			PIN_MASK(4, BIT(0)), 0, 			MODULE_PWM, 0)		/* EC_FAN_SPEED - Fan Speed */
+
+/* I2C Signals -- i2c pins need to be exposed as GPIO for bit banging, even though set to alternate mode below */
+GPIO(EC_I2C_USB_A0_C0_SCL,	PIN(B, 5), GPIO_INPUT)
+GPIO(EC_I2C_USB_A0_C0_SDA,	PIN(B, 4), GPIO_INPUT)
+GPIO(EC_I2C_USB_A1_C1_SCL,	PIN(9, 0), GPIO_INPUT)
+GPIO(EC_I2C_USB_A1_C1_SDA,	PIN(8, 7), GPIO_INPUT)
+GPIO(EC_I2C_BATT_SCL,		PIN(9, 2), GPIO_INPUT)
+GPIO(EC_I2C_BATT_SDA,		PIN(9, 1), GPIO_INPUT)
+GPIO(EC_I2C_USBC_MUX_SCL,	PIN(D, 1), GPIO_INPUT)
+GPIO(EC_I2C_USBC_MUX_SDA,	PIN(D, 0), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SCL,		PIN(F, 3), GPIO_INPUT)
+GPIO(EC_I2C_POWER_SDA,		PIN(F, 2), GPIO_INPUT)
+GPIO(EC_I2C_CBI_SCL,		PIN(3, 3), GPIO_INPUT)
+GPIO(EC_I2C_CBI_SDA,		PIN(3, 6), GPIO_INPUT)
+GPIO(EC_I2C_SENSOR_SCL,		PIN(E, 4), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SENSOR_SDA,		PIN(E, 3), GPIO_INPUT | GPIO_SEL_1P8V)
+GPIO(EC_I2C_SOC_SIC,		PIN(B, 3), GPIO_INPUT)
+GPIO(EC_I2C_SOC_SID,		PIN(B, 2), GPIO_INPUT)
+
+ALTERNATE(			PIN_MASK(B, BIT(4) | BIT(5)), 0, 		MODULE_I2C, 0)		/* I2C0 */
+ALTERNATE(			PIN_MASK(9, BIT(0) | BIT(1) | BIT(2)), 0, 	MODULE_I2C, 0)		/* I2C1 SCL / I2C2 */
+ALTERNATE(			PIN_MASK(8, BIT(7)), 0, MODULE_I2C, 0)					/* I2C1 SDA */
+ALTERNATE(			PIN_MASK(D, BIT(0) | BIT(1)), 0, 		MODULE_I2C, 0)		/* I2C3 */
+ALTERNATE(			PIN_MASK(F, BIT(2) | BIT(3)), 0, 		MODULE_I2C, 0)		/* I2C4 */
+ALTERNATE(			PIN_MASK(3, BIT(3) | BIT(6)), 0, 		MODULE_I2C, 0)		/* I2C5 */
+ALTERNATE(			PIN_MASK(E, BIT(3) | BIT(4)), 0, 		MODULE_I2C, 0)		/* I2C6 */
+ALTERNATE(			PIN_MASK(B, BIT(2) | BIT(3)), 0, 		MODULE_I2C, 0)		/* I2C7 */
+
+/* Keyboard Signals */
+GPIO(EN_KB_BL, 			PIN(9, 7), GPIO_OUT_HIGH)						/* Enable Keyboard Backlight */
+ALTERNATE(/*PWM_KB_BL*/ 	PIN_MASK(C, BIT(2)), 0, 			MODULE_PWM, 0)		/* Keyboard Backlight Level */
+ALTERNATE(/*KSI_00-01*/		PIN_MASK(3, BIT(0) | BIT(1)), 0, 		MODULE_KEYBOARD_SCAN, GPIO_INPUT)
+ALTERNATE(/*KSI_02-07*/		PIN_MASK(2, GENMASK(7, 2)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_INPUT)
+ALTERNATE(/*KSO_00-01*/		PIN_MASK(2, BIT(0) | BIT(1)), 0, 		MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
+GPIO(EC_KSO_02_INV, 		PIN(1, 7), GPIO_OUT_LOW)						/* KSO_02 inverted */
+ALTERNATE(/*KSO_03-09*/		PIN_MASK(1, GENMASK(6, 0)), 0,			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
+ALTERNATE(/*KSO_10-13*/		PIN_MASK(0, GENMASK(7, 4)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
+ALTERNATE(/*KSO_14*/		PIN_MASK(8, BIT(2)), 0, 			MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH)
+
+/* SOC eSPI Bus */
+GPIO(ESPI_SOC_CLK,		PIN(5, 5), GPIO_DEFAULT)
+GPIO(ESPI_SOC_CS_EC_L,		PIN(5, 3), GPIO_DEFAULT)
+GPIO(ESPI_SOC_D0_EC,		PIN(4, 6), GPIO_DEFAULT)
+GPIO(ESPI_SOC_D1_EC,		PIN(4, 7), GPIO_DEFAULT)
+GPIO(ESPI_SOC_D2_EC,		PIN(5, 1), GPIO_DEFAULT)
+GPIO(ESPI_SOC_D3_EC,		PIN(5, 2), GPIO_DEFAULT)
+GPIO(EC_ESPI_RST_L,		PIN(5, 4), GPIO_DEFAULT)
+GPIO(ESPI_EC_ALERT_SOC_L,	PIN(5, 7), GPIO_DEFAULT)
+
+/* TCPC C0 */
+IOEX(USB_C0_PPC_EN_L,		EXPIN(USBC_PORT_C0, 1, 0), GPIO_OUT_HIGH)
+IOEX(USB_C0_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C0, 1, 1), GPIO_OUT_LOW)
+IOEX_INT(USB_C0_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C0, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
+IOEX(EN_PP5000_USB_A0_VBUS,	EXPIN(USBC_PORT_C0, 1, 5), GPIO_OUT_LOW)
+IOEX(USB_A0_LIMIT_SDP,		EXPIN(USBC_PORT_C0, 1, 6), GPIO_OUT_LOW)
+IOEX(USB_C0_SBU_FLIP,		EXPIN(USBC_PORT_C0, 1, 7), GPIO_OUT_LOW)
+
+/* TCPC C1 */
+IOEX(USB_C1_IN_HPD,		EXPIN(USBC_PORT_C1, 0, 3), GPIO_OUT_LOW)
+IOEX(USB_C1_PPC_EN_L,		EXPIN(USBC_PORT_C1, 1, 0), GPIO_OUT_HIGH)
+IOEX(USB_C1_PPC_ILIM_3A_EN,	EXPIN(USBC_PORT_C1, 1, 1), GPIO_OUT_LOW)
+IOEX_INT(USB_C1_SBU_FAULT_ODL,	EXPIN(USBC_PORT_C1, 1, 2), GPIO_INT_FALLING,	sbu_fault_interrupt)
+IOEX(EN_PP5000_USB_A1_VBUS_DB,	EXPIN(USBC_PORT_C1, 1, 5), GPIO_OUT_LOW)
+IOEX(USB_A1_LIMIT_SDP_DB,	EXPIN(USBC_PORT_C1, 1, 6), GPIO_OUT_LOW)
+
+/* Test Points */
+GPIO(EC_GPIO56,			PIN(5, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PS2_CLK,		PIN(6, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PS2_DAT,		PIN(7, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PS2_RST,		PIN(6, 2), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_GPIOB0,			PIN(B, 0), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_GPIO81,			PIN(8, 1), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_FLPRG2,			PIN(8, 6), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PSL_GPO,		PIN(D, 7), GPIO_INPUT | GPIO_PULL_UP)
+GPIO(EC_PWM7,			PIN(6, 0), GPIO_INPUT | GPIO_PULL_UP)
diff --git a/baseboard/mancomb/baseboard.c b/baseboard/mancomb/baseboard.c
new file mode 100644
index 0000000000..7151157ae4
--- /dev/null
+++ b/baseboard/mancomb/baseboard.c
@@ -0,0 +1,921 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Mancomb family-specific configuration */
+
+#include "adc.h"
+#include "adc_chip.h"
+#include "battery_fuel_gauge.h"
+#include "charge_manager.h"
+#include "charge_ramp.h"
+#include "charge_state_v2.h"
+#include "charge_state.h"
+#include "charger.h"
+#include "chip/npcx/ps2_chip.h"
+#include "chip/npcx/pwm_chip.h"
+#include "chipset.h"
+#include "driver/ppc/aoz1380.h"
+#include "driver/ppc/nx20p348x.h"
+#include "driver/retimer/ps8818.h"
+#include "driver/tcpm/nct38xx.h"
+#include "driver/temp_sensor/sb_tsi.h"
+#include "driver/usb_mux/amd_fp6.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "i2c.h"
+#include "ioexpander.h"
+#include "isl9241.h"
+#include "keyboard_scan.h"
+#include "nct38xx.h"
+#include "pi3usb9201.h"
+#include "power.h"
+#include "pwm.h"
+#include "temp_sensor.h"
+#include "thermal.h"
+#include "thermistor.h"
+#include "usb_mux.h"
+#include "usb_pd_tcpm.h"
+#include "usbc_ppc.h"
+
+#define CPRINTSUSB(format, args...) cprints(CC_USBCHARGE, format, ## args)
+#define CPRINTFUSB(format, args...) cprintf(CC_USBCHARGE, format, ## args)
+
+/* Wake Sources */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_LID_OPEN,
+	GPIO_AC_PRESENT,
+	GPIO_POWER_BUTTON_L,
+};
+const int hibernate_wake_pins_used =  ARRAY_SIZE(hibernate_wake_pins);
+
+/* Power Signal Input List */
+const struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S0_N] = {
+		.gpio = GPIO_PCH_SLP_S0_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S0_DEASSERTED",
+	},
+	[X86_SLP_S3_N] = {
+		.gpio = GPIO_PCH_SLP_S3_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S3_DEASSERTED",
+	},
+	[X86_SLP_S5_N] = {
+		.gpio = GPIO_PCH_SLP_S5_L,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "SLP_S5_DEASSERTED",
+	},
+	[X86_S0_PGOOD] = {
+		.gpio = GPIO_S0_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S0_PGOOD",
+	},
+	[X86_S5_PGOOD] = {
+		.gpio = GPIO_S5_PGOOD,
+		.flags = POWER_SIGNAL_ACTIVE_HIGH,
+		.name = "S5_PGOOD",
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+const struct i2c_port_t i2c_ports[] = {
+	{
+		.name = "tcpc0",
+		.port = I2C_PORT_TCPC0,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_A0_C0_SCL,
+		.sda = GPIO_EC_I2C_USB_A0_C0_SDA,
+	},
+	{
+		.name = "tcpc1",
+		.port = I2C_PORT_TCPC1,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USB_A1_C1_SCL,
+		.sda = GPIO_EC_I2C_USB_A1_C1_SDA,
+	},
+	{
+		.name = "battery",
+		.port = I2C_PORT_BATTERY,
+		.kbps = 100,
+		.scl = GPIO_EC_I2C_BATT_SCL,
+		.sda = GPIO_EC_I2C_BATT_SDA,
+	},
+	{
+		.name = "usb_mux",
+		.port = I2C_PORT_USB_MUX,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_USBC_MUX_SCL,
+		.sda = GPIO_EC_I2C_USBC_MUX_SDA,
+	},
+	{
+		.name = "charger",
+		.port = I2C_PORT_CHARGER,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_POWER_SCL,
+		.sda = GPIO_EC_I2C_POWER_SDA,
+	},
+	{
+		.name = "eeprom",
+		.port = I2C_PORT_EEPROM,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_CBI_SCL,
+		.sda = GPIO_EC_I2C_CBI_SDA,
+	},
+	{
+		.name = "sensor",
+		.port = I2C_PORT_SENSOR,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SENSOR_SCL,
+		.sda = GPIO_EC_I2C_SENSOR_SDA,
+	},
+	{
+		.name = "soc_thermal",
+		.port = I2C_PORT_THERMAL_AP,
+		.kbps = 400,
+		.scl = GPIO_EC_I2C_SOC_SIC,
+		.sda = GPIO_EC_I2C_SOC_SID,
+	},
+};
+const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* ADC Channels */
+const struct adc_t adc_channels[] = {
+	[ADC_TEMP_SENSOR_SOC] = {
+		.name = "SOC",
+		.input_ch = NPCX_ADC_CH0,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_CHARGER] = {
+		.name = "CHARGER",
+		.input_ch = NPCX_ADC_CH1,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+	[ADC_TEMP_SENSOR_MEMORY] = {
+		.name = "MEMORY",
+		.input_ch = NPCX_ADC_CH2,
+		.factor_mul = ADC_MAX_VOLT,
+		.factor_div = ADC_READ_MAX + 1,
+		.shift = 0,
+	},
+
+};
+BUILD_ASSERT(ARRAY_SIZE(adc_channels) == ADC_CH_COUNT);
+
+/* Temp Sensors */
+static int board_get_memory_temp(int, int *);
+static int board_get_soc_temp(int, int *);
+const struct temp_sensor_t temp_sensors[] = {
+	[TEMP_SENSOR_SOC] = {
+		.name = "SOC",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = board_get_soc_temp,
+		.idx = TEMP_SENSOR_SOC,
+	},
+	[TEMP_SENSOR_CHARGER] = {
+		.name = "Charger",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = get_temp_3v3_30k9_47k_4050b,
+		.idx = TEMP_SENSOR_CHARGER,
+	},
+	[TEMP_SENSOR_MEMORY] = {
+		.name = "Memory",
+		.type = TEMP_SENSOR_TYPE_BOARD,
+		.read = board_get_memory_temp,
+		.idx = TEMP_SENSOR_MEMORY,
+	},
+	[TEMP_SENSOR_CPU] = {
+		.name = "CPU",
+		.type = TEMP_SENSOR_TYPE_CPU,
+		.read = sb_tsi_get_val,
+		.idx = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(temp_sensors) == TEMP_SENSOR_COUNT);
+
+struct ec_thermal_config thermal_params[TEMP_SENSOR_COUNT] = {
+	[TEMP_SENSOR_SOC] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		},
+		.temp_fan_off = C_TO_K(32),
+		.temp_fan_max = C_TO_K(75),
+	},
+	[TEMP_SENSOR_CHARGER] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		},
+		.temp_fan_off = 0,
+		.temp_fan_max = 0,
+	},
+	[TEMP_SENSOR_MEMORY] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		},
+		.temp_fan_off = 0,
+		.temp_fan_max = 0,
+	},
+	[TEMP_SENSOR_CPU] = {
+		.temp_host = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(90),
+			[EC_TEMP_THRESH_HALT] = C_TO_K(92),
+		},
+		.temp_host_release = {
+			[EC_TEMP_THRESH_HIGH] = C_TO_K(80),
+		},
+		.temp_fan_off = 0,
+		.temp_fan_max = 0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(thermal_params) == TEMP_SENSOR_COUNT);
+
+/*
+ * Battery info for all Mancomb battery types. Note that the fields
+ * start_charging_min/max and charging_min/max are not used for the charger.
+ * The effective temperature limits are given by discharging_min/max_c.
+ *
+ * Fuel Gauge (FG) parameters which are used for determining if the battery
+ * is connected, the appropriate ship mode (battery cutoff) command, and the
+ * charge/discharge FETs status.
+ *
+ * Ship mode (battery cutoff) requires 2 writes to the appropriate smart battery
+ * register. For some batteries, the charge/discharge FET bits are set when
+ * charging/discharging is active, in other types, these bits set mean that
+ * charging/discharging is disabled. Therefore, in addition to the mask for
+ * these bits, a disconnect value must be specified. Note that for TI fuel
+ * gauge, the charge/discharge FET status is found in Operation Status (0x54),
+ * but a read of Manufacturer Access (0x00) will return the lower 16 bits of
+ * Operation status which contains the FET status bits.
+ *
+ * The assumption for battery types supported is that the charge/discharge FET
+ * status can be read with a sb_read() command and therefore, only the register
+ * address, mask, and disconnect value need to be provided.
+ */
+const struct board_batt_params board_battery_info[] = {
+	/* AP18F4M / LIS4163ACPC */
+	[BATTERY_AP18F4M] = {
+		.fuel_gauge = {
+			.manuf_name = "Murata KT00404001",
+			.ship_mode = {
+				.reg_addr = 0x3A,
+				.reg_data = { 0xC574, 0xC574 },
+			},
+			.fet = {
+				.reg_addr = 0x0,
+				.reg_mask = 0x2000,
+				.disconnect_val = 0x2000,
+			}
+		},
+		.batt_info = {
+			.voltage_max          = 8700,
+			.voltage_normal       = 7600,
+			.voltage_min          = 5500,
+			.precharge_current    = 256,
+			.start_charging_min_c = 0,
+			.start_charging_max_c = 50,
+			.charging_min_c       = 0,
+			.charging_max_c       = 60,
+			.discharging_min_c    = -20,
+			.discharging_max_c    = 75,
+		},
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(board_battery_info) == BATTERY_TYPE_COUNT);
+const enum battery_type DEFAULT_BATTERY_TYPE = BATTERY_AP18F4M;
+
+const struct charger_config_t chg_chips[] = {
+	{
+		.i2c_port = I2C_PORT_CHARGER,
+		.i2c_addr_flags = ISL9241_ADDR_FLAGS,
+		.drv = &isl9241_drv,
+	},
+};
+
+const struct tcpc_config_t tcpc_config[] = {
+	[USBC_PORT_C0] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC0,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+	[USBC_PORT_C1] = {
+		.bus_type = EC_BUS_TYPE_I2C,
+		.i2c_info = {
+			.port = I2C_PORT_TCPC1,
+			.addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		},
+		.drv = &nct38xx_tcpm_drv,
+		.flags = TCPC_FLAGS_TCPCI_REV2_0,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(tcpc_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_USB_PD_PORT_MAX_COUNT == USBC_PORT_COUNT);
+
+const int usb_port_enable[USBA_PORT_COUNT] = {
+	IOEX_EN_PP5000_USB_A0_VBUS,
+	IOEX_EN_PP5000_USB_A1_VBUS_DB,
+};
+
+static void baseboard_interrupt_init(void)
+{
+	/* Enable PPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_PPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_PPC_INT_ODL);
+
+	/* Enable TCPC interrupts. */
+	gpio_enable_interrupt(GPIO_USB_C0_TCPC_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_TCPC_INT_ODL);
+
+	/* Enable BC 1.2 interrupts */
+	gpio_enable_interrupt(GPIO_USB_C0_BC12_INT_ODL);
+	gpio_enable_interrupt(GPIO_USB_C1_BC12_INT_ODL);
+
+	/* Enable SBU fault interrupts */
+	ioex_enable_interrupt(IOEX_USB_C0_SBU_FAULT_ODL);
+	ioex_enable_interrupt(IOEX_USB_C1_SBU_FAULT_ODL);
+}
+DECLARE_HOOK(HOOK_INIT, baseboard_interrupt_init, HOOK_PRIO_INIT_I2C + 1);
+
+struct ppc_config_t ppc_chips[] = {
+	[USBC_PORT_C0] = {
+		/* Device does not talk I2C */
+		.drv = &aoz1380_drv
+	},
+
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = NX20P3483_ADDR1_FLAGS,
+		.drv = &nx20p348x_drv
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ppc_chips) == USBC_PORT_COUNT);
+unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips);
+
+const struct pi3usb9201_config_t pi3usb9201_bc12_chips[] = {
+	[USBC_PORT_C0] = {
+		.i2c_port = I2C_PORT_TCPC0,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+
+	[USBC_PORT_C1] = {
+		.i2c_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = PI3USB9201_I2C_ADDR_3_FLAGS,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pi3usb9201_bc12_chips) == USBC_PORT_COUNT);
+
+/*
+ * .init is not necessary here because it has nothing
+ * to do. Primary mux will handle mux state so .get is
+ * not needed as well. usb_mux.c can handle the situation
+ * properly.
+ */
+static int fsusb42umx_set_mux(const struct usb_mux*, mux_state_t);
+const struct usb_mux_driver usbc0_sbu_mux_driver = {
+	.set = fsusb42umx_set_mux,
+};
+
+/*
+ * Since FSUSB42UMX is not a i2c device, .i2c_port and
+ * .i2c_addr_flags are not required here.
+ */
+const struct usb_mux usbc0_sbu_mux = {
+	.usb_port = USBC_PORT_C0,
+	.driver = &usbc0_sbu_mux_driver,
+};
+
+static int board_ps8818_mux_set(const struct usb_mux*, mux_state_t);
+const struct usb_mux usbc1_ps8818 = {
+	.usb_port = USBC_PORT_C1,
+	.i2c_port = I2C_PORT_TCPC1,
+	.i2c_addr_flags = PS8818_I2C_ADDR_FLAGS,
+	.driver = &ps8818_usb_retimer_driver,
+	.board_set = &board_ps8818_mux_set,
+};
+
+struct usb_mux usb_muxes[] = {
+	[USBC_PORT_C0] = {
+		.usb_port = USBC_PORT_C0,
+		.i2c_port = I2C_PORT_USB_MUX,
+		.i2c_addr_flags = AMD_FP6_C0_MUX_I2C_ADDR,
+		.driver = &amd_fp6_usb_mux_driver,
+		.next_mux = &usbc0_sbu_mux,
+	},
+	[USBC_PORT_C1] = {
+		.usb_port = USBC_PORT_C1,
+		.i2c_port = I2C_PORT_USB_MUX,
+		.i2c_addr_flags = AMD_FP6_C4_MUX_I2C_ADDR,
+		.driver = &amd_fp6_usb_mux_driver,
+		.next_mux = &usbc1_ps8818,
+	}
+};
+BUILD_ASSERT(ARRAY_SIZE(usb_muxes) == USBC_PORT_COUNT);
+
+struct ioexpander_config_t ioex_config[] = {
+	[USBC_PORT_C0] = {
+		.i2c_host_port = I2C_PORT_TCPC0,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+	},
+	[USBC_PORT_C1] = {
+		.i2c_host_port = I2C_PORT_TCPC1,
+		.i2c_addr_flags = NCT38XX_I2C_ADDR1_1_FLAGS,
+		.drv = &nct38xx_ioexpander_drv,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(ioex_config) == USBC_PORT_COUNT);
+BUILD_ASSERT(CONFIG_IO_EXPANDER_PORT_COUNT == USBC_PORT_COUNT);
+
+/* Keyboard scan setting */
+struct keyboard_scan_config keyscan_config = {
+	/*
+	 * F3 key scan cycle completed but scan input is not
+	 * charging to logic high when EC start scan next
+	 * column for "T" key, so we set .output_settle_us
+	 * to 80us
+	 */
+	.output_settle_us = 80,
+	.debounce_down_us = 6 * MSEC,
+	.debounce_up_us = 30 * MSEC,
+	.scan_period_us = 1500,
+	.min_post_scan_delay_us = 1000,
+	.poll_timeout_us = SECOND,
+	.actual_key_mask = {
+		0x3c, 0xff, 0xff, 0xff, 0xff, 0xf5, 0xff,
+		0xa4, 0xff, 0xfe, 0x55, 0xfa, 0xca  /* full set */
+	},
+};
+
+const struct pwm_t pwm_channels[] = {
+	[PWM_CH_FAN] = {
+		.channel = 0,
+		.flags = PWM_CONFIG_OPEN_DRAIN,
+		.freq = 25000,
+	},
+	[PWM_CH_KBLIGHT] = {
+		.channel = 1,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 100,
+	},
+	[PWM_CH_LED_CHRG] = {
+		.channel = 2,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 100,
+	},
+	[PWM_CH_LED_FULL] = {
+		.channel = 3,
+		.flags = PWM_CONFIG_DSLEEP,
+		.freq = 100,
+	},
+};
+BUILD_ASSERT(ARRAY_SIZE(pwm_channels) == PWM_CH_COUNT);
+
+/*
+ * USB C0 port SBU mux use standalone FSUSB42UMX
+ * chip and it needs a board specific driver.
+ * Overall, it will use chained mux framework.
+ */
+static int fsusb42umx_set_mux(const struct usb_mux *me, mux_state_t mux_state)
+{
+	if (mux_state & USB_PD_MUX_POLARITY_INVERTED)
+		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 1);
+	else
+		ioex_set_level(IOEX_USB_C0_SBU_FLIP, 0);
+
+	return EC_SUCCESS;
+}
+
+/*
+ * PS8818 set mux board tuning.
+ * Adds in board specific gain and DP lane count configuration
+ * TODO(b/179036200): Adjust PS8818 tuning for mancomb and variants
+ */
+static int board_ps8818_mux_set(const struct usb_mux *me,
+				mux_state_t mux_state)
+{
+	int rv = EC_SUCCESS;
+
+	/* USB specific config */
+	if (mux_state & USB_PD_MUX_USB_ENABLED) {
+		/* Boost the USB gain */
+		rv = ps8818_i2c_field_update8(me,
+					PS8818_REG_PAGE1,
+					PS8818_REG1_APTX1EQ_10G_LEVEL,
+					PS8818_EQ_LEVEL_UP_MASK,
+					PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me,
+					PS8818_REG_PAGE1,
+					PS8818_REG1_APTX2EQ_10G_LEVEL,
+					PS8818_EQ_LEVEL_UP_MASK,
+					PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me,
+					PS8818_REG_PAGE1,
+					PS8818_REG1_APTX1EQ_5G_LEVEL,
+					PS8818_EQ_LEVEL_UP_MASK,
+					PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		rv = ps8818_i2c_field_update8(me,
+					PS8818_REG_PAGE1,
+					PS8818_REG1_APTX2EQ_5G_LEVEL,
+					PS8818_EQ_LEVEL_UP_MASK,
+					PS8818_EQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		/* Set the RX input termination */
+		rv = ps8818_i2c_field_update8(me,
+					PS8818_REG_PAGE1,
+					PS8818_REG1_RX_PHY,
+					PS8818_RX_INPUT_TERM_MASK,
+					PS8818_RX_INPUT_TERM_112_OHM);
+		if (rv)
+			return rv;
+	}
+
+	/* DP specific config */
+	if (mux_state & USB_PD_MUX_DP_ENABLED) {
+		/* Boost the DP gain */
+		rv = ps8818_i2c_field_update8(me,
+					PS8818_REG_PAGE1,
+					PS8818_REG1_DPEQ_LEVEL,
+					PS8818_DPEQ_LEVEL_UP_MASK,
+					PS8818_DPEQ_LEVEL_UP_19DB);
+		if (rv)
+			return rv;
+
+		/* Enable HPD on the DB */
+		gpio_set_level(GPIO_USB_C1_HPD, 1);
+	} else {
+		/* Disable HPD on the DB */
+		gpio_set_level(GPIO_USB_C1_HPD, 0);
+	}
+
+	return rv;
+}
+
+int board_set_active_charge_port(int port)
+{
+	int is_valid_port = (port >= 0 &&
+			     port < CONFIG_USB_PD_PORT_MAX_COUNT);
+	int i;
+
+	if (port == CHARGE_PORT_NONE) {
+		CPRINTSUSB("Disabling all charger ports");
+
+		/* Disable all ports. */
+		for (i = 0; i < ppc_cnt; i++) {
+			/*
+			 * Do not return early if one fails otherwise we can
+			 * get into a boot loop assertion failure.
+			 */
+			if (ppc_vbus_sink_enable(i, 0))
+				CPRINTSUSB("Disabling C%d as sink failed.", i);
+		}
+
+		return EC_SUCCESS;
+	} else if (!is_valid_port) {
+		return EC_ERROR_INVAL;
+	}
+
+
+	/* Check if the port is sourcing VBUS. */
+	if (ppc_is_sourcing_vbus(port)) {
+		CPRINTFUSB("Skip enable C%d", port);
+		return EC_ERROR_INVAL;
+	}
+
+	CPRINTSUSB("New charge port: C%d", port);
+
+	/*
+	 * Turn off the other ports' sink path FETs, before enabling the
+	 * requested charge port.
+	 */
+	for (i = 0; i < ppc_cnt; i++) {
+		if (i == port)
+			continue;
+
+		if (ppc_vbus_sink_enable(i, 0))
+			CPRINTSUSB("C%d: sink path disable failed.", i);
+	}
+
+	/* Enable requested charge port. */
+	if (ppc_vbus_sink_enable(port, 1)) {
+		CPRINTSUSB("C%d: sink path enable failed.", port);
+		return EC_ERROR_UNKNOWN;
+	}
+
+	return EC_SUCCESS;
+}
+
+int board_is_i2c_port_powered(int port)
+{
+	switch (port) {
+	case I2C_PORT_USB_MUX:
+	case I2C_PORT_SENSOR:
+		/* USB mux and sensor i2c bus is unpowered in Z1 */
+		return chipset_in_state(CHIPSET_STATE_HARD_OFF) ? 0 : 1;
+	case I2C_PORT_THERMAL_AP:
+		/* SOC thermal i2c bus is unpowered in S0i3/S3/S5/Z1 */
+		return chipset_in_state(CHIPSET_STATE_ANY_OFF |
+					CHIPSET_STATE_ANY_SUSPEND) ? 0 : 1;
+	default:
+		return 1;
+	}
+}
+
+/*
+ * In the AOZ1380 PPC, there are no programmable features.  We use
+ * the attached NCT3807 to control a GPIO to indicate 1A5 or 3A0
+ * current limits.
+ */
+int board_aoz1380_set_vbus_source_current_limit(int port,
+						enum tcpc_rp_value rp)
+{
+	int rv;
+
+	/* Use the TCPC to set the current limit */
+	rv = ioex_set_level(IOEX_USB_C0_PPC_ILIM_3A_EN,
+			    (rp == TYPEC_RP_3A0) ? 1 : 0);
+
+	return rv;
+}
+
+void board_set_charge_limit(int port, int supplier, int charge_ma,
+			    int max_ma, int charge_mv)
+{
+	charge_set_input_current_limit(MAX(charge_ma,
+					   CONFIG_CHARGER_INPUT_CURRENT),
+				       charge_mv);
+}
+
+void sbu_fault_interrupt(enum ioex_signal signal)
+{
+	int port = (signal == IOEX_USB_C0_SBU_FAULT_ODL) ? 0 : 1;
+
+	pd_handle_overcurrent(port);
+}
+
+static void set_ac_prochot(void)
+{
+	isl9241_set_ac_prochot(CHARGER_SOLO, MANCOMB_AC_PROCHOT_CURRENT_MA);
+}
+DECLARE_HOOK(HOOK_INIT, set_ac_prochot, HOOK_PRIO_DEFAULT);
+
+void tcpc_alert_event(enum gpio_signal signal)
+{
+	int port;
+
+	switch (signal) {
+	case GPIO_USB_C0_TCPC_INT_ODL:
+		port = 0;
+		break;
+	case GPIO_USB_C1_TCPC_INT_ODL:
+		port = 1;
+		break;
+	default:
+		return;
+	}
+
+	schedule_deferred_pd_interrupt(port);
+}
+
+static void reset_pd_port(int port, enum gpio_signal reset_gpio_l,
+			  int hold_delay, int post_delay)
+{
+	gpio_set_level(reset_gpio_l, 0);
+	msleep(hold_delay);
+	gpio_set_level(reset_gpio_l, 1);
+	if (post_delay)
+		msleep(post_delay);
+}
+
+
+void board_reset_pd_mcu(void)
+{
+	/* Reset TCPC0 */
+	reset_pd_port(USBC_PORT_C0, GPIO_USB_C0_TCPC_RST_L,
+		      NCT38XX_RESET_HOLD_DELAY_MS,
+		      NCT38XX_RESET_POST_DELAY_MS);
+
+	/* Reset TCPC1 */
+	reset_pd_port(USBC_PORT_C1, GPIO_USB_C1_TCPC_RST_L,
+		      NCT38XX_RESET_HOLD_DELAY_MS,
+		      NCT38XX_RESET_POST_DELAY_MS);
+}
+
+uint16_t tcpc_get_alert_status(void)
+{
+	uint16_t status = 0;
+
+	/*
+	 * Check which port has the ALERT line set and ignore if that TCPC has
+	 * its reset line active.
+	 */
+	if (!gpio_get_level(GPIO_USB_C0_TCPC_INT_ODL)) {
+		if (gpio_get_level(GPIO_USB_C0_TCPC_RST_L) != 0)
+			status |= PD_STATUS_TCPC_ALERT_0;
+	}
+
+	if (!gpio_get_level(GPIO_USB_C1_TCPC_INT_ODL)) {
+		if (gpio_get_level(GPIO_USB_C1_TCPC_RST_L) != 0)
+			status |= PD_STATUS_TCPC_ALERT_1;
+	}
+
+	return status;
+}
+
+void ppc_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_PPC_INT_ODL:
+		aoz1380_interrupt(USBC_PORT_C0);
+		break;
+
+	case GPIO_USB_C1_PPC_INT_ODL:
+		nx20p348x_interrupt(USBC_PORT_C1);
+		break;
+
+	default:
+		break;
+	}
+}
+
+void bc12_interrupt(enum gpio_signal signal)
+{
+	switch (signal) {
+	case GPIO_USB_C0_BC12_INT_ODL:
+		task_set_event(TASK_ID_USB_CHG_P0, USB_CHG_EVENT_BC12);
+		break;
+
+	case GPIO_USB_C1_BC12_INT_ODL:
+		task_set_event(TASK_ID_USB_CHG_P1, USB_CHG_EVENT_BC12);
+		break;
+
+	default:
+		break;
+	}
+}
+
+static int board_get_memory_temp(int idx, int *temp_k)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+	return get_temp_3v3_30k9_47k_4050b(idx, temp_k);
+}
+
+static int board_get_soc_temp(int idx, int *temp_k)
+{
+	if (chipset_in_state(CHIPSET_STATE_HARD_OFF))
+		return EC_ERROR_NOT_POWERED;
+	return get_temp_3v3_30k9_47k_4050b(idx, temp_k);
+}
+
+/**
+ * Return if VBUS is sagging too low
+ */
+int board_is_vbus_too_low(int port, enum chg_ramp_vbus_state ramp_state)
+{
+	int voltage = 0;
+	int rv;
+
+	rv = charger_get_vbus_voltage(port, &voltage);
+
+	if (rv) {
+		CPRINTSUSB("%s rv=%d", __func__, rv);
+		return 0;
+	}
+
+	/*
+	 * b/168569046: The ISL9241 sometimes incorrectly reports 0 for unknown
+	 * reason, causing ramp to stop at 0.5A. Workaround this by ignoring 0.
+	 * This partly defeats the point of ramping, but will still catch
+	 * VBUS below 4.5V and above 0V.
+	 */
+	if (voltage == 0) {
+		CPRINTSUSB("%s vbus=0", __func__);
+		return 0;
+	}
+
+	if (voltage < BC12_MIN_VOLTAGE)
+		CPRINTSUSB("%s vbus=%d", __func__, voltage);
+
+	return voltage < BC12_MIN_VOLTAGE;
+}
+
+/**
+ * b/175324615: On G3->S5, wait for RSMRST_L to be deasserted before asserting
+ * PCH_PWRBTN_L.
+ */
+void board_pwrbtn_to_pch(int level)
+{
+	/* Add delay for G3 exit if asserting PWRBTN_L and S5_PGOOD is low. */
+	if (!level && !gpio_get_level(GPIO_S5_PGOOD)) {
+		/*
+		 * From measurement, wait 80 ms for RSMRST_L to rise after
+		 * S5_PGOOD.
+		 */
+		msleep(G3_TO_PWRBTN_DELAY_MS);
+
+		if (!gpio_get_level(GPIO_S5_PGOOD))
+			ccprints("Error: pwrbtn S5_PGOOD low");
+	}
+	gpio_set_level(GPIO_PCH_PWRBTN_L, level);
+}
+
+void board_hibernate(void)
+{
+	int port;
+
+	/*
+	 * If we are charging, then drop the Vbus level down to 5V to ensure
+	 * that we don't get locked out of the 6.8V OVLO for our PPCs in
+	 * dead-battery mode. This is needed when the TCPC/PPC rails go away.
+	 * (b/79218851, b/143778351, b/147007265)
+	 */
+	port = charge_manager_get_active_charge_port();
+	if (port != CHARGE_PORT_NONE) {
+		pd_request_source_voltage(port, SAFE_RESET_VBUS_MV);
+
+		/* Give PD task and PPC chip time to get to 5V */
+		msleep(SAFE_RESET_VBUS_DELAY_MS);
+	}
+}
+
+static void baseboard_chipset_suspend(void)
+{
+	/* Disable display and keyboard backlights. */
+	gpio_set_level(GPIO_EC_DISABLE_DISP_BL, 1);
+	ioex_set_level(GPIO_EN_KB_BL, 0);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
+	     HOOK_PRIO_DEFAULT);
+
+static void baseboard_chipset_resume(void)
+{
+	/* Enable display and keyboard backlights. */
+	gpio_set_level(GPIO_EC_DISABLE_DISP_BL, 0);
+	ioex_set_level(GPIO_EN_KB_BL, 1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
+
+void board_overcurrent_event(int port, int is_overcurrented)
+{
+	switch (port) {
+	case USBC_PORT_C0:
+	case USBC_PORT_C1:
+		gpio_set_level(GPIO_USB_C0_C1_FAULT_ODL, !is_overcurrented);
+		break;
+
+	default:
+		break;
+	}
+}
+
+void baseboard_en_pwr_pcore_s0(enum gpio_signal signal)
+{
+
+	/* EC must AND signals PG_LPDDR4X_S3_OD and PG_GROUPC_S0_OD */
+	gpio_set_level(GPIO_EN_PWR_PCORE_S0_R,
+					gpio_get_level(GPIO_PG_LPDDR4X_S3_OD) &&
+					gpio_get_level(GPIO_PG_GROUPC_S0_OD));
+}
+
+void baseboard_en_pwr_s0(enum gpio_signal signal)
+{
+
+	/* EC must AND signals SLP_S3_L and PG_PWR_S5 */
+	gpio_set_level(GPIO_EN_PWR_S0_R,
+					gpio_get_level(GPIO_SLP_S3_L) &&
+					gpio_get_level(GPIO_PG_PWR_S5));
+
+	/* Now chain off to the normal power signal interrupt handler. */
+	power_signal_interrupt(signal);
+}
diff --git a/baseboard/mancomb/baseboard.h b/baseboard/mancomb/baseboard.h
new file mode 100644
index 0000000000..d357e6675b
--- /dev/null
+++ b/baseboard/mancomb/baseboard.h
@@ -0,0 +1,319 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Mancomb baseboard configuration */
+
+#ifndef __CROS_EC_BASEBOARD_H
+#define __CROS_EC_BASEBOARD_H
+
+/* NPCX9 config */
+#define NPCX9_PWM1_SEL    1  /* GPIO C2 is used as PWM1. */
+#define NPCX_UART_MODULE2 1  /* GPIO64/65 are used as UART pins. */
+
+/* Optional features */
+#define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */
+#define CONFIG_LTO /* Link-Time Optimizations to reduce code size */
+#define CONFIG_BRINGUP /* EC will not automatically power on the AP */
+#define CONFIG_I2C_DEBUG /* Print i2c traces */
+#define CONFIG_KEYBOARD_DEBUG /* Print keyboard debug messages */
+
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 4096
+
+/* Power Config */
+#undef  CONFIG_EXTPOWER_DEBOUNCE_MS
+#define CONFIG_EXTPOWER_DEBOUNCE_MS 200
+#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_HIBERNATE_PSL
+#define CONFIG_LOW_POWER_IDLE
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_TO_PCH_CUSTOM
+#define CONFIG_POWER_BUTTON_X86
+#define CONFIG_POWER_COMMON
+#define CONFIG_POWER_S0IX
+#define CONFIG_POWER_SLEEP_FAILURE_DETECTION
+#define CONFIG_POWER_SHUTDOWN_PAUSE_IN_S5
+#define CONFIG_POWER_TRACK_HOST_SLEEP_STATE
+#define G3_TO_PWRBTN_DELAY_MS 80
+#define GPIO_AC_PRESENT		GPIO_ACOK_OD
+#define GPIO_EN_PWR_A		GPIO_EN_PWR_Z1
+#define GPIO_PCH_PWRBTN_L	GPIO_EC_SOC_PWR_BTN_L
+#define GPIO_PCH_RSMRST_L	GPIO_EC_SOC_RSMRST_L
+#define GPIO_PCH_SLP_S0_L	GPIO_SLP_S3_S0I3_L
+#define GPIO_PCH_SLP_S3_L	GPIO_SLP_S3_L
+#define GPIO_PCH_SLP_S5_L	GPIO_SLP_S5_L
+#define GPIO_PCH_SYS_PWROK	GPIO_EC_SOC_PWR_GOOD
+#define GPIO_PCH_WAKE_L		GPIO_EC_SOC_WAKE_L
+#define GPIO_POWER_BUTTON_L	GPIO_MECH_PWR_BTN_ODL
+#define GPIO_S0_PGOOD		GPIO_PG_PCORE_S0_R_OD
+#define GPIO_S5_PGOOD		GPIO_PG_PWR_S5
+#define GPIO_SYS_RESET_L	GPIO_EC_SYS_RST_L
+#define SAFE_RESET_VBUS_DELAY_MS 900
+#define SAFE_RESET_VBUS_MV 5000
+/*
+ * On power-on, H1 releases the EC from reset but then quickly asserts and
+ * releases the reset a second time. This means the EC sees 2 resets:
+ * (1) power-on reset, (2) reset-pin reset. This config will
+ * allow the second reset to be treated as a power-on.
+ */
+#define CONFIG_BOARD_RESET_AFTER_POWER_ON
+
+/* Thermal Config */
+#define CONFIG_ADC
+#define CONFIG_STEINHART_HART_3V3_30K9_47K_4050B
+#define CONFIG_THROTTLE_AP
+#define CONFIG_TEMP_SENSOR_SB_TSI
+#define CONFIG_THERMISTOR
+#define CONFIG_CPU_PROCHOT_ACTIVE_LOW
+#define GPIO_CPU_PROCHOT	GPIO_PROCHOT_ODL
+
+/* Flash Config */
+/* See config_chip-npcx9.h for SPI flash configuration */
+#undef CONFIG_SPI_FLASH /* Don't enable external flash interface */
+#define GPIO_WP_L			GPIO_EC_WP_L
+
+/* Host communication */
+#define CONFIG_CMD_CHARGEN
+#define CONFIG_HOSTCMD_ESPI
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO_AND_HOST_EVENT
+#define GPIO_EC_INT_L		GPIO_EC_SOC_INT_L
+
+/* Chipset config */
+#define CONFIG_CHIPSET_CEZANNE
+#define CONFIG_CHIPSET_CAN_THROTTLE
+#define CONFIG_CHIPSET_RESET_HOOK
+
+/* Keyboard Config */
+#define CONFIG_KEYBOARD_BACKLIGHT
+#define CONFIG_KEYBOARD_BOARD_CONFIG
+#define CONFIG_KEYBOARD_COL2_INVERTED
+#define CONFIG_KEYBOARD_PROTOCOL_8042
+#define CONFIG_KEYBOARD_VIVALDI
+#define GPIO_KBD_KSO2		GPIO_EC_KSO_02_INV
+
+/* Sensors */
+#define CONFIG_TABLET_MODE
+#define CONFIG_GMR_TABLET_MODE
+#define GMR_TABLET_MODE_GPIO_L		GPIO_TABLET_MODE
+
+/* Battery Config */
+#define CONFIG_BATTERY_PRESENT_GPIO	GPIO_EC_BATT_PRES_ODL
+#define CONFIG_BATTERY_CUT_OFF
+#define CONFIG_BATTERY_FUEL_GAUGE
+#define CONFIG_BATTERY_REVIVE_DISCONNECT
+#define CONFIG_BATTERY_SMART
+#define CONFIG_BATTERY_V2
+#define CONFIG_BATTERY_COUNT 1
+#define CONFIG_HOSTCMD_BATTERY_V2
+#define CONFIG_BC12_DETECT_PI3USB9201
+
+/* Charger Config */
+#define CONFIG_CHARGER
+#define CONFIG_CHARGE_MANAGER
+#define CONFIG_CHARGER_DISCHARGE_ON_AC
+#define CONFIG_CHARGER_INPUT_CURRENT 512
+#define CONFIG_CHARGER_ISL9241
+#define CONFIG_CHARGER_SENSE_RESISTOR 10
+#define CONFIG_CHARGER_SENSE_RESISTOR_AC 20
+
+/*
+ * EC will boot AP to depthcharge if: (BAT >= 4%) || (AC >= 50W)
+ * CONFIG_CHARGER_LIMIT_* is not set, so there is no additional restriction on
+ * Depthcharge to boot OS.
+ */
+#define CONFIG_CHARGER_MIN_BAT_PCT_FOR_POWER_ON			4
+#define CONFIG_CHARGER_MIN_POWER_MW_FOR_POWER_ON		50000
+
+/*
+ * We would prefer to use CONFIG_CHARGE_RAMP_HW to enable legacy BC1.2 charging
+ * but that feature of ISL9241 is broken (b/160287056) so we have to use
+ * CONFIG_CHARGE_RAMP_SW instead.
+ */
+#define CONFIG_CHARGE_RAMP_SW
+
+/* USB Type C and USB PD config */
+#define CONFIG_USB_PD_REV30
+#define CONFIG_USB_PD_TCPMV2
+#define CONFIG_USB_PD_DECODE_SOP
+#define CONFIG_USB_DRP_ACC_TRYSRC
+/* TODO: Enable TCPMv2 Fast Role Swap (FRS) */
+#define CONFIG_HOSTCMD_PD_CONTROL
+#define CONFIG_CMD_TCPC_DUMP
+#define CONFIG_USB_CHARGER
+#define CONFIG_USB_POWER_DELIVERY
+#define CONFIG_USB_PD_ALT_MODE
+#define CONFIG_USB_PD_ALT_MODE_DFP
+#define CONFIG_USB_PD_DISCHARGE_TCPC
+#define CONFIG_USB_PD_DP_HPD_GPIO
+#define CONFIG_USB_PD_DUAL_ROLE
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_LOGGING
+#define CONFIG_USB_PD_TCPC_LOW_POWER
+#define CONFIG_USB_PD_TCPM_MUX
+#define CONFIG_USB_PD_TCPM_NCT38XX
+#define CONFIG_USB_PD_TCPM_TCPCI
+#define CONFIG_USB_PD_TRY_SRC
+#define CONFIG_USB_PD_VBUS_DETECT_TCPC
+#define CONFIG_USBC_PPC
+#define CONFIG_USBC_PPC_SBU
+#define CONFIG_USBC_PPC_AOZ1380
+#define CONFIG_USBC_RETIMER_PI3HDX1204
+#define CONFIG_USBC_SS_MUX
+#define CONFIG_USBC_SS_MUX_DFP_ONLY
+#define CONFIG_USBC_VCONN
+#define CONFIG_USBC_VCONN_SWAP
+#define CONFIG_USB_MUX_ANX7451
+#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USBC_PPC_NX20P3483
+#define CONFIG_USBC_RETIMER_PS8818
+#define CONFIG_USB_MUX_RUNTIME_CONFIG
+#define CONFIG_USB_MUX_AMD_FP6
+
+#define GPIO_USB_C0_DP_HPD GPIO_USB_C0_HPD
+#define GPIO_USB_C1_DP_HPD GPIO_USB_C1_HPD
+
+#define CONFIG_IO_EXPANDER
+#define CONFIG_IO_EXPANDER_NCT38XX
+#define CONFIG_IO_EXPANDER_PORT_COUNT USBC_PORT_COUNT
+
+/* TODO(b/176988382): Tune values for mancomb */
+#define PD_POWER_SUPPLY_TURN_ON_DELAY	30000 /* us */
+#define PD_POWER_SUPPLY_TURN_OFF_DELAY	30000 /* us */
+
+#define PD_OPERATING_POWER_MW	15000
+#define PD_MAX_POWER_MW		65000
+#define PD_MAX_CURRENT_MA	3250
+#define PD_MAX_VOLTAGE_MV	20000
+
+/* USB-A config */
+#define USB_PORT_COUNT USBA_PORT_COUNT
+#define CONFIG_USB_PORT_POWER_SMART
+#define CONFIG_USB_PORT_POWER_SMART_CDP_SDP_ONLY
+#define CONFIG_USB_PORT_POWER_SMART_DEFAULT_MODE USB_CHARGE_MODE_CDP
+#define CONFIG_USB_PORT_POWER_SMART_INVERTED
+
+#define GPIO_USB1_ILIM_SEL IOEX_USB_A0_LIMIT_SDP
+#define GPIO_USB2_ILIM_SEL IOEX_USB_A1_LIMIT_SDP_DB
+
+/* Round up 3250 max current to multiple of 128mA for ISL9241 AC prochot. */
+#define MANCOMB_AC_PROCHOT_CURRENT_MA 3328
+
+/*
+ * USB ID - This is allocated specifically for Mancomb
+ */
+#define CONFIG_USB_PID 0x504D
+
+/* BC 1.2 */
+/*
+ * For legacy BC1.2 charging with CONFIG_CHARGE_RAMP_SW, ramp up input current
+ * until voltage drops to 4.5V. Don't go lower than this to be kind to the
+ * charger (see b/67964166).
+ */
+#define BC12_MIN_VOLTAGE 4500
+
+/* I2C Bus Configuration */
+#define CONFIG_I2C
+#define CONFIG_I2C_BUS_MAY_BE_UNPOWERED
+#define CONFIG_I2C_CONTROLLER
+#define CONFIG_I2C_UPDATE_IF_CHANGED
+#define I2C_PORT_TCPC0		NPCX_I2C_PORT0_0
+#define I2C_PORT_TCPC1		NPCX_I2C_PORT1_0
+#define I2C_PORT_BATTERY	NPCX_I2C_PORT2_0
+#define I2C_PORT_USB_MUX	NPCX_I2C_PORT3_0
+#define I2C_PORT_POWER		NPCX_I2C_PORT4_1
+#define I2C_PORT_CHARGER	I2C_PORT_POWER
+#define I2C_PORT_EEPROM		NPCX_I2C_PORT5_0
+#define I2C_PORT_SENSOR		NPCX_I2C_PORT6_1
+#define I2C_PORT_THERMAL_AP	NPCX_I2C_PORT7_0
+#define I2C_ADDR_EEPROM_FLAGS	0x50
+
+/* Volume Button Config */
+#define CONFIG_VOLUME_BUTTONS
+#define GPIO_VOLUME_UP_L		GPIO_VOLUP_BTN_ODL
+#define GPIO_VOLUME_DOWN_L		GPIO_VOLDN_BTN_ODL
+
+/* Fan features */
+
+/* LED Config */
+#define CONFIG_PWM
+#define CONFIG_PWM_KBLIGHT
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+/* Power input signals */
+enum power_signal {
+	X86_SLP_S0_N,		/* SOC  -> SLP_S3_S0I3_L */
+	X86_SLP_S3_N,		/* SOC  -> SLP_S3_L */
+	X86_SLP_S5_N,		/* SOC  -> SLP_S5_L */
+
+	X86_S0_PGOOD,		/* PMIC -> S0_PWROK_OD */
+	X86_S5_PGOOD,		/* PMIC -> S5_PWROK */
+
+	/* Number of X86 signals */
+	POWER_SIGNAL_COUNT,
+};
+
+/* USB-C ports */
+enum usbc_port {
+	USBC_PORT_C0 = 0,
+	USBC_PORT_C1,
+	USBC_PORT_COUNT
+};
+
+/* USB-A ports */
+enum usba_port {
+	USBA_PORT_A0 = 0,
+	USBA_PORT_A1,
+	USBA_PORT_COUNT
+};
+
+/* ADC Channels */
+enum adc_channel {
+	ADC_TEMP_SENSOR_SOC = 0,
+	ADC_TEMP_SENSOR_CHARGER,
+	ADC_TEMP_SENSOR_MEMORY,
+	ADC_CH_COUNT
+};
+
+/* Temp Sensors */
+enum temp_sensor_id {
+	TEMP_SENSOR_SOC = 0,
+	TEMP_SENSOR_CHARGER,
+	TEMP_SENSOR_MEMORY,
+	TEMP_SENSOR_CPU,
+	TEMP_SENSOR_COUNT
+};
+
+/* Battery Types */
+enum battery_type {
+	BATTERY_AP18F4M,
+	BATTERY_TYPE_COUNT,
+};
+
+/* PWM Channels */
+enum pwm_channel {
+	PWM_CH_FAN = 0,
+	PWM_CH_KBLIGHT,
+	PWM_CH_LED_CHRG,
+	PWM_CH_LED_FULL,
+	PWM_CH_COUNT
+};
+
+/* Common definition for the USB PD interrupt handlers. */
+void tcpc_alert_event(enum gpio_signal signal);
+void bc12_interrupt(enum gpio_signal signal);
+void ppc_interrupt(enum gpio_signal signal);
+void sbu_fault_interrupt(enum ioex_signal signal);
+
+void baseboard_en_pwr_pcore_s0(enum gpio_signal signal);
+void baseboard_en_pwr_s0(enum gpio_signal signal);
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BASEBOARD_H */
diff --git a/baseboard/mancomb/build.mk b/baseboard/mancomb/build.mk
new file mode 100644
index 0000000000..aed9b9d460
--- /dev/null
+++ b/baseboard/mancomb/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Mancomb baseboard specific files build
+#
+
+CHIP:=npcx
+CHIP_FAMILY:=npcx9
+CHIP_VARIANT:=npcx9m3f
+
+baseboard-y=baseboard.o
+baseboard-$(CONFIG_USB_POWER_DELIVERY)+=usb_pd_policy.o
\ No newline at end of file
diff --git a/baseboard/mancomb/usb_pd_policy.c b/baseboard/mancomb/usb_pd_policy.c
new file mode 100644
index 0000000000..ac92a6e0ad
--- /dev/null
+++ b/baseboard/mancomb/usb_pd_policy.c
@@ -0,0 +1,77 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Shared USB-C policy for Zork boards */
+
+#include "charge_manager.h"
+#include "chipset.h"
+#include "common.h"
+#include "compile_time_macros.h"
+#include "console.h"
+#include "ec_commands.h"
+#include "gpio.h"
+#include "system.h"
+#include "usb_mux.h"
+#include "usb_pd.h"
+#include "usbc_ppc.h"
+#include "util.h"
+
+int pd_check_vconn_swap(int port)
+{
+	/*
+	 * Do not allow vconn swap 5V rail is off
+	 * S5_PGOOD depends on PG_PP5000_S5 being asserted,
+	 * so GPIO_S5_PGOOD is a reasonable proxy for PP5000_S5
+	 */
+	return gpio_get_level(GPIO_S5_PGOOD);
+}
+
+void pd_power_supply_reset(int port)
+{
+	/*
+	 * Don't need to shutoff VBus if we are not sourcing it
+	 * TODO: Ensure Vbus sourcing is being disabled appropriately to
+	 *       avoid invalid TC states
+	 */
+	if (ppc_is_sourcing_vbus(port)) {
+		/* Disable VBUS. */
+		ppc_vbus_source_enable(port, 0);
+
+		/* Enable discharge if we were previously sourcing 5V */
+		if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+			pd_set_vbus_discharge(port, 1);
+	}
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+}
+
+int pd_set_power_supply_ready(int port)
+{
+	int rv;
+
+	/* Disable charging. */
+	rv = ppc_vbus_sink_enable(port, 0);
+	if (rv)
+		return rv;
+
+	if (IS_ENABLED(CONFIG_USB_PD_DISCHARGE))
+		pd_set_vbus_discharge(port, 0);
+
+	/* Provide Vbus. */
+	rv = ppc_vbus_source_enable(port, 1);
+	if (rv)
+		return rv;
+
+	/* Notify host of power info change. */
+	pd_send_host_event(PD_EVENT_POWER_CHANGE);
+
+	return EC_SUCCESS;
+}
+
+int board_vbus_source_enabled(int port)
+{
+	return ppc_is_sourcing_vbus(port);
+}
diff --git a/board/mancomb/board.c b/board/mancomb/board.c
new file mode 100644
index 0000000000..4f2b6087d1
--- /dev/null
+++ b/board/mancomb/board.c
@@ -0,0 +1,25 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Mancomb board-specific configuration */
+
+#include "button.h"
+#include "common.h"
+#include "extpower.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "lid_switch.h"
+#include "power.h"
+#include "power_button.h"
+#include "switch.h"
+#include "tablet_mode.h"
+
+#include "gpio_list.h" /* Must come after other header files. */
+
+static void board_init(void)
+{
+	/* TODO */
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/mancomb/board.h b/board/mancomb/board.h
new file mode 100644
index 0000000000..9d651404e9
--- /dev/null
+++ b/board/mancomb/board.h
@@ -0,0 +1,37 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Mancomb board configuration */
+
+#ifndef __CROS_EC_BOARD_H
+#define __CROS_EC_BOARD_H
+
+/* Baseboard features */
+#include "baseboard.h"
+
+/* Motion sensing drivers */
+
+/* Keyboard features */
+
+/* Sensors */
+
+/* USB Type C and USB PD defines */
+
+/* USB Type A Features */
+
+/* BC 1.2 */
+
+/* Volume Button feature */
+
+/* Fan features */
+
+#ifndef __ASSEMBLER__
+
+#include "gpio_signal.h"
+#include "registers.h"
+
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BOARD_H */
diff --git a/board/mancomb/build.mk b/board/mancomb/build.mk
new file mode 100644
index 0000000000..1630304826
--- /dev/null
+++ b/board/mancomb/build.mk
@@ -0,0 +1,11 @@
+# -*- makefile -*-
+# Copyright 2021 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+#
+
+BASEBOARD:=mancomb
+
+board-y=board.o
diff --git a/board/mancomb/ec.tasklist b/board/mancomb/ec.tasklist
new file mode 100644
index 0000000000..fe4d4edc4a
--- /dev/null
+++ b/board/mancomb/ec.tasklist
@@ -0,0 +1,12 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+
+#include "base_ec.tasklist"
+
+#define CONFIG_TASK_LIST BASEBOARD_CONFIG_TASK_LIST
diff --git a/board/mancomb/gpio.inc b/board/mancomb/gpio.inc
new file mode 100644
index 0000000000..567bf737f3
--- /dev/null
+++ b/board/mancomb/gpio.inc
@@ -0,0 +1,10 @@
+/* -*- mode:c -*-
+ *
+ * Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Declare symbolic names for all the board GPIOs that we care about. */
+
+#include "base_gpio.inc"