stm32g4: Add support for stm32g473xc variant

This CL adds the stm32g473xc variant to the STM32G4 family. The
primary change is that the internal flash is increased from 128 to
256kB. In addition, the stm32g431xb flash size is set back to its
actual value of 128kB.

BUG=b:167462264
BRANCH=None
TEST=make -j BOARD=quiche

Signed-off-by: Scott Collyer <scollyer@google.com>
Change-Id: I163b6044d48425c70f9e6c5d7e352d5c1dd7df72
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2682783
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Scott Collyer <scollyer@chromium.org>

3 files changed, 67 insertions, 6 deletions

diff --git a/chip/stm32/config-stm32g41xb.h b/chip/stm32/config-stm32g41xb.h
index 28bea1ebb1..4f1ed96871 100644
--- a/chip/stm32/config-stm32g41xb.h
+++ b/chip/stm32/config-stm32g41xb.h
@@ -16,12 +16,8 @@
  * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support
  * PSTATE in single bank memories with a write size > 4 bytes.
  */
-/*
- * TODO(b/167462264): This is a temporary change to allow for platform bringup
- * without being constrained by flash space issue. Currently only using RO image
- * flashed with STM32 debugger.
- */
-#define CONFIG_FLASH_SIZE_BYTES       (256 * 1024)
+
+#define CONFIG_FLASH_SIZE_BYTES       (128 * 1024)
 #define CONFIG_FLASH_WRITE_SIZE 0x0004
 #define CONFIG_FLASH_BANK_SIZE (2 * 1024)
 #define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE
diff --git a/chip/stm32/config-stm32g473xc.h b/chip/stm32/config-stm32g473xc.h
new file mode 100644
index 0000000000..8771ff455b
--- /dev/null
+++ b/chip/stm32/config-stm32g473xc.h
@@ -0,0 +1,63 @@
+/* Copyright 2021 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Memory mapping for STM32G473xc. The STM32G473xc is a category 1 device within
+ * the STM32G4 chip family. Category 1 devices have either 128, 256, or 512 kB
+ * of internal flash. 'xc' indicates 256 kB of internal flash.
+ *
+ * STM32G473xc can be configured via option bytes as either a single bank or
+ * dual bank device. Dual bank is the default selection.
+ * CONFIG_FLASH_BANK_SIZE is consistent with page size as defined in RM0440 TRM
+ * for the STM32G4 chip family. In dual bank mode, the flash is organized in 2
+ * kB pages, with 64 pages per bank for this variant.
+ *
+ * The minimum write size for STM32G4 is 8 bytes. Cros-EC does not support
+ * PSTATE in single bank memories with a write size > 4 bytes.
+ *
+ * TODO(b/181874494): Verify that dual bank mode should be used, or add support
+ * for enabling single bank mode on STM32G473xc.
+ */
+#define CONFIG_FLASH_SIZE_BYTES (256 * 1024)
+#define CONFIG_FLASH_WRITE_SIZE 0x0004
+#define CONFIG_FLASH_BANK_SIZE (2 * 1024)
+#define CONFIG_FLASH_ERASE_SIZE CONFIG_FLASH_BANK_SIZE
+
+
+/* Erasing 128K can take up to 2s, need to defer erase. */
+#define CONFIG_FLASH_DEFERRED_ERASE
+
+/* No page mode on STM32G4, so no benefit to larger write sizes */
+#define CONFIG_FLASH_WRITE_IDEAL_SIZE CONFIG_FLASH_WRITE_SIZE
+
+/*
+ * STM32G473xc is a category 3 SRAM device featuring 128 Kbytes of embedded
+ * SRAM. This SRAM is split into three blocks:
+ * • 80 Kbytes mapped at address 0x2000 0000 (SRAM1).
+ * • 16 Kbytes mapped at address 0x2001 4000 (SRAM2).
+ * • 32 Kbytes mapped at address 0x1000 0000 (CCM SRAM). It is also aliased
+ *   at 0x2001 8000 address to be accessed by all bus controllers.
+ */
+#define CONFIG_RAM_BASE		0x20000000
+#define CONFIG_RAM_SIZE		0x00020000
+
+#undef I2C_PORT_COUNT
+#define I2C_PORT_COUNT	4
+
+/* Number of DMA channels supported (6 channels each for DMA1 and DMA2) */
+#define DMAC_COUNT 12
+
+/* Use PSTATE embedded in the RO image, not in its own erase block */
+#define CONFIG_FLASH_PSTATE
+#undef CONFIG_FLASH_PSTATE_BANK
+
+/* Number of IRQ vectors on the NVIC */
+#define CONFIG_IRQ_COUNT	101
+
+/* USB packet ram config */
+#define CONFIG_USB_RAM_BASE        0x40006000
+#define CONFIG_USB_RAM_SIZE        1024
+#define CONFIG_USB_RAM_ACCESS_TYPE uint16_t
+#define CONFIG_USB_RAM_ACCESS_SIZE 2
diff --git a/chip/stm32/config_chip.h b/chip/stm32/config_chip.h
index 35acf94c82..816737731f 100644
--- a/chip/stm32/config_chip.h
+++ b/chip/stm32/config_chip.h
@@ -61,6 +61,8 @@
 #include "config-stm32h7x3.h"
 #elif defined(CHIP_VARIANT_STM32G431XB)
 #include "config-stm32g41xb.h"
+#elif defined(CHIP_VARIANT_STM32G473XC)
+#include "config-stm32g473xc.h"
 #else
 #error "Unsupported chip variant"
 #endif