diff options
| author | Vadim Bendebury <vbendeb@chromium.org> | 2015-10-05 12:12:45 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-10-05 20:31:23 -0700 |
| commit | 217e72d700257057801ea6ba3620a368a89f9cbd (patch) | |
| tree | 6f7da957f4f344145a1c6d78b1faa5692f4511aa | |
| parent | 9e21514972c7d0b21e826e2edb2db7b8be2249ec (diff) | |
| download | chrome-ec-217e72d700257057801ea6ba3620a368a89f9cbd.tar.gz | |
cr50: upgrade to the latest FPGA image
This patch updates the EC codebase to match the suggested USB build
(20151005_041713). The spiflash utility must come from the same
tarball.
BRANCH=none
BUG=none
TEST=as follows:
- programmed the FPGA, it now reports the following when reset:
BootRom 0.8.91hw
- booted the new image using the latest spiflash version.
- disconnected the FPGA upgrade port, rebooted the device, entered
on the device console:
> spstp off
> spste
run on the workstation:
$ examples/spiraw.py -l 10 -f 800000
FT232H Future Technology Devices International, Ltd initialized at 857142 hertz
and observe on the DUT console:
Processed 10 frames rx count 11604, tx count 5512, tx_empty 10, max rx batch 11
>
Change-Id: Iff778087149ae3e7570f8fd4d81c2857a4ea5367
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/304123
Reviewed-by: Marius Schilder <mschilder@chromium.org>
| -rw-r--r-- | chip/g/config_chip.h | 11 | ||||
| -rw-r--r-- | chip/g/cr50_fpga_regdefs.h | 2971 | ||||
| -rw-r--r-- | util/signer/codesigner.cc | 12 | ||||
| -rw-r--r-- | util/signer/common/publickey.h | 6 | ||||
| -rw-r--r-- | util/signer/common/signed_header.h | 4 | ||||
| -rw-r--r-- | util/signer/image.cc | 1 | ||||
| -rw-r--r-- | util/signer/rom-testkey-A.pem | 399 |
7 files changed, 1641 insertions, 1763 deletions
diff --git a/chip/g/config_chip.h b/chip/g/config_chip.h index 8bef2e687a..50655d5e22 100644 --- a/chip/g/config_chip.h +++ b/chip/g/config_chip.h @@ -7,10 +7,7 @@ #define __CROS_EC_CONFIG_CHIP_H #include "core/cortex-m/config_core.h" - -/* Number of IRQ vectors on the NVIC */ -/* TODO_FPGA this should come from the generated .h file */ -#define CONFIG_IRQ_COUNT 192 +#include "cr50_fpga_regdefs.h" /* Describe the RAM layout */ #define CONFIG_RAM_BASE 0x10000 @@ -61,7 +58,9 @@ #define GPIO_PIN(port, index) GPIO_##port, (1 << index) #define GPIO_PIN_MASK(port, mask) GPIO_##port, (mask) -/* TODO_FPGA this should come from the generated .h file */ -#define PCLK_FREQ (24 * 1000 * 1000) +#define PCLK_FREQ (GC_CONST_FPGA_TIMER_FIXED_FREQ * 1000 * 1000) + +/* Number of IRQ vectors on the NVIC */ +#define CONFIG_IRQ_COUNT (GC_INTERRUPTS_COUNT - 16) #endif /* __CROS_EC_CONFIG_CHIP_H */ diff --git a/chip/g/cr50_fpga_regdefs.h b/chip/g/cr50_fpga_regdefs.h index 5622dd1ce0..117460d478 100644 --- a/chip/g/cr50_fpga_regdefs.h +++ b/chip/g/cr50_fpga_regdefs.h @@ -88,42 +88,42 @@ #define GC_PINMUX_SPI1_SPICSB_SEL 0x2a #define GC_PINMUX_SPI1_SPIMISO_SEL 0x2b #define GC_PINMUX_SPI1_SPIMOSI_SEL 0x2c -#define GC_PINMUX_SWDP0_TRACE2_SEL 0x2d #define GC_PINMUX_SWDPDATA_SEL 0x3 #define GC_PINMUX_SWDPTRACE_SEL 0x4 -#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL 0x2e -#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL 0x2f -#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL 0x30 -#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL 0x31 -#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL 0x32 -#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL 0x33 -#define GC_PINMUX_UART0_CTS_SEL 0x34 -#define GC_PINMUX_UART0_RTS_SEL 0x35 -#define GC_PINMUX_UART0_RX_SEL 0x36 -#define GC_PINMUX_UART0_TX_SEL 0x37 -#define GC_PINMUX_UART1_CTS_SEL 0x38 -#define GC_PINMUX_UART1_RTS_SEL 0x39 -#define GC_PINMUX_UART1_RX_SEL 0x3a -#define GC_PINMUX_UART1_TX_SEL 0x3b -#define GC_PINMUX_UART2_CTS_SEL 0x3c -#define GC_PINMUX_UART2_RTS_SEL 0x3d -#define GC_PINMUX_UART2_RX_SEL 0x3e -#define GC_PINMUX_UART2_TX_SEL 0x3f -#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x40 -#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x41 -#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x42 -#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x43 -#define GC_PINMUX_USB0_EXT_RX_DMI_SEL 0x44 -#define GC_PINMUX_USB0_EXT_RX_DPI_SEL 0x45 -#define GC_PINMUX_USB0_EXT_RX_RCV_SEL 0x46 -#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL 0x47 -#define GC_PINMUX_USB0_EXT_TX_DMO_SEL 0x48 -#define GC_PINMUX_USB0_EXT_TX_DPO_SEL 0x49 -#define GC_PINMUX_USB0_EXT_TX_OEB_SEL 0x4a +#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL 0x2d +#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL 0x2e +#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL 0x2f +#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL 0x30 +#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL 0x31 +#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL 0x32 +#define GC_PINMUX_UART0_CTS_SEL 0x33 +#define GC_PINMUX_UART0_RTS_SEL 0x34 +#define GC_PINMUX_UART0_RX_SEL 0x35 +#define GC_PINMUX_UART0_TX_SEL 0x36 +#define GC_PINMUX_UART1_CTS_SEL 0x37 +#define GC_PINMUX_UART1_RTS_SEL 0x38 +#define GC_PINMUX_UART1_RX_SEL 0x39 +#define GC_PINMUX_UART1_TX_SEL 0x3a +#define GC_PINMUX_UART2_CTS_SEL 0x3b +#define GC_PINMUX_UART2_RTS_SEL 0x3c +#define GC_PINMUX_UART2_RX_SEL 0x3d +#define GC_PINMUX_UART2_TX_SEL 0x3e +#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL 0x3f +#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL 0x40 +#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL 0x41 +#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL 0x42 +#define GC_PINMUX_USB0_EXT_RX_DMI_SEL 0x43 +#define GC_PINMUX_USB0_EXT_RX_DPI_SEL 0x44 +#define GC_PINMUX_USB0_EXT_RX_RCV_SEL 0x45 +#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL 0x46 +#define GC_PINMUX_USB0_EXT_TX_DMO_SEL 0x47 +#define GC_PINMUX_USB0_EXT_TX_DPO_SEL 0x48 +#define GC_PINMUX_USB0_EXT_TX_OEB_SEL 0x49 #define GC_PINMUX_VIO0_SEL 0x2 #define GC_PINMUX_VIO1_SEL 0x1 -#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL 0x4b -#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL 0x4c +#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL 0x4a +#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL 0x4b +#define GC_PINMUX_SEL_COUNT 107 #define GC_EXCEPTNUM_RESET 0x1 #define GC_EXCEPTNUM_NMI 0x2 #define GC_EXCEPTNUM_HARDFAULT 0x3 @@ -147,199 +147,201 @@ #define GC_EXCEPTNUM_CRYPTO0_HOST_CMD_RECV_INT 0x15 #define GC_EXCEPTNUM_CRYPTO0_LOOP_STACK_OVERFLOW_INT 0x16 #define GC_EXCEPTNUM_CRYPTO0_LOOP_STACK_UNDERFLOW_INT 0x17 -#define GC_EXCEPTNUM_CRYPTO0_PC_STACK_OVERFLOW_INT 0x18 -#define GC_EXCEPTNUM_CRYPTO0_PGM_FAULT_INT 0x19 -#define GC_EXCEPTNUM_CRYPTO0_TRAP_INT 0x1a -#define GC_EXCEPTNUM_DMA0_INTR_COMPLETE_CHAN_INT 0x1b -#define GC_EXCEPTNUM_DMA0_INTR_ERROR_CHAN_INT 0x1c -#define GC_EXCEPTNUM_DMA0_INTR_PROG_CHAN_INT 0x1d -#define GC_EXCEPTNUM_DMA0_INTR_TIMEOUT_CHAN_INT 0x1e -#define GC_EXCEPTNUM_FLASH0_EDONEINT 0x1f -#define GC_EXCEPTNUM_FLASH0_PDONEINT 0x20 -#define GC_EXCEPTNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT 0x21 -#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_DMEM_PARITY_ALERT_INT 0x22 -#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_DRF_PARITY_ALERT_INT 0x23 -#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_IMEM_PARITY_ALERT_INT 0x24 -#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_PGM_FAULT_ALERT_INT 0x25 -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_INT 0x26 -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_INT 0x27 -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_INT 0x28 -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_INT 0x29 -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_INT 0x2a -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_INT 0x2b -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_INT 0x2c -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_INT 0x2d -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_INT 0x2e -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 0x2f -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 0x30 -#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 0x31 -#define GC_EXCEPTNUM_GLOBALSEC_FUSE0_FUSE_DEFAULTS_ALERT_INT 0x32 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 0x33 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 0x34 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 0x35 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 0x36 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 0x37 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 0x38 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 0x39 -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 0x3a -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 0x3b -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_PROC_OPCODE_HASH_ALERT_INT 0x3c -#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 0x3d -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 0x3e -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 0x3f -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 0x40 -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 0x41 -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 0x42 -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_INT 0x43 -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_FAULT_ALERT_INT 0x44 -#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 0x45 -#define GC_EXCEPTNUM_GLOBALSEC_PMU_BATTERY_MON_ALERT_INT 0x46 -#define GC_EXCEPTNUM_GLOBALSEC_PMU_PMU_WDOG_ALERT_INT 0x47 -#define GC_EXCEPTNUM_GLOBALSEC_RTC0_RTC_DEAD_ALERT_INT 0x48 -#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 0x49 -#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 0x4a -#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 0x4b -#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 0x4c -#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 0x4d -#define GC_EXCEPTNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 0x4e -#define GC_EXCEPTNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 0x4f -#define GC_EXCEPTNUM_GPIO0_GPIO0INT 0x50 -#define GC_EXCEPTNUM_GPIO0_GPIO1INT 0x51 -#define GC_EXCEPTNUM_GPIO0_GPIO2INT 0x52 -#define GC_EXCEPTNUM_GPIO0_GPIO3INT 0x53 -#define GC_EXCEPTNUM_GPIO0_GPIO4INT 0x54 -#define GC_EXCEPTNUM_GPIO0_GPIO5INT 0x55 -#define GC_EXCEPTNUM_GPIO0_GPIO6INT 0x56 -#define GC_EXCEPTNUM_GPIO0_GPIO7INT 0x57 -#define GC_EXCEPTNUM_GPIO0_GPIO8INT 0x58 -#define GC_EXCEPTNUM_GPIO0_GPIO9INT 0x59 -#define GC_EXCEPTNUM_GPIO0_GPIO10INT 0x5a -#define GC_EXCEPTNUM_GPIO0_GPIO11INT 0x5b -#define GC_EXCEPTNUM_GPIO0_GPIO12INT 0x5c -#define GC_EXCEPTNUM_GPIO0_GPIO13INT 0x5d -#define GC_EXCEPTNUM_GPIO0_GPIO14INT 0x5e -#define GC_EXCEPTNUM_GPIO0_GPIO15INT 0x5f -#define GC_EXCEPTNUM_GPIO0_GPIOCOMBINT 0x60 -#define GC_EXCEPTNUM_GPIO1_GPIO0INT 0x61 -#define GC_EXCEPTNUM_GPIO1_GPIO1INT 0x62 -#define GC_EXCEPTNUM_GPIO1_GPIO2INT 0x63 -#define GC_EXCEPTNUM_GPIO1_GPIO3INT 0x64 -#define GC_EXCEPTNUM_GPIO1_GPIO4INT 0x65 -#define GC_EXCEPTNUM_GPIO1_GPIO5INT 0x66 -#define GC_EXCEPTNUM_GPIO1_GPIO6INT 0x67 -#define GC_EXCEPTNUM_GPIO1_GPIO7INT 0x68 -#define GC_EXCEPTNUM_GPIO1_GPIO8INT 0x69 -#define GC_EXCEPTNUM_GPIO1_GPIO9INT 0x6a -#define GC_EXCEPTNUM_GPIO1_GPIO10INT 0x6b -#define GC_EXCEPTNUM_GPIO1_GPIO11INT 0x6c -#define GC_EXCEPTNUM_GPIO1_GPIO12INT 0x6d -#define GC_EXCEPTNUM_GPIO1_GPIO13INT 0x6e -#define GC_EXCEPTNUM_GPIO1_GPIO14INT 0x6f -#define GC_EXCEPTNUM_GPIO1_GPIO15INT 0x70 -#define GC_EXCEPTNUM_GPIO1_GPIOCOMBINT 0x71 -#define GC_EXCEPTNUM_I2C0_I2CINT 0x72 -#define GC_EXCEPTNUM_I2C1_I2CINT 0x73 -#define GC_EXCEPTNUM_I2CS0_INTR_READ_BEGIN_INT 0x74 -#define GC_EXCEPTNUM_I2CS0_INTR_READ_COMPLETE_INT 0x75 -#define GC_EXCEPTNUM_I2CS0_INTR_WRITE_COMPLETE_INT 0x76 -#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_CIPHER_INT 0x77 -#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 0x78 -#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 0x79 -#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 0x7a -#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 0x7b -#define GC_EXCEPTNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 0x7c -#define GC_EXCEPTNUM_KEYMGR0_DSHA_INT 0x7d -#define GC_EXCEPTNUM_PMU_INTR_WAKEUP_INT 0x7e -#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_FED_INT 0x7f -#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_RED_INT 0x80 -#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 0x81 -#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 0x82 -#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 0x83 -#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_FED_INT 0x84 -#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_RED_INT 0x85 -#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_FED_INT 0x86 -#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_RED_INT 0x87 -#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_FED_INT 0x88 -#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_RED_INT 0x89 -#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_FED_INT 0x8a -#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_RED_INT 0x8b -#define GC_EXCEPTNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT 0x8c -#define GC_EXCEPTNUM_SPI0_SPITXINT 0x8d -#define GC_EXCEPTNUM_SPI1_SPITXINT 0x8e -#define GC_EXCEPTNUM_SPS0_CS_ASSERT_INTR 0x8f -#define GC_EXCEPTNUM_SPS0_CS_DEASSERT_INTR 0x90 -#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 0x91 -#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 0x92 -#define GC_EXCEPTNUM_SPS0_INTR_CMD_MEM_OVFL_INT 0x93 -#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 0x94 -#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 0x95 -#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 0x96 -#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 0x97 -#define GC_EXCEPTNUM_SPS0_RXFIFO_LVL_INTR 0x98 -#define GC_EXCEPTNUM_SPS0_RXFIFO_OVERFLOW_INTR 0x99 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT0 0x9a -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT1 0x9b -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT2 0x9c -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT3 0x9d -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT4 0x9e -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT5 0x9f -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT6 0xa0 -#define GC_EXCEPTNUM_SPS0_SPSCTRLINT7 0xa1 -#define GC_EXCEPTNUM_SPS0_TXFIFO_EMPTY_INTR 0xa2 -#define GC_EXCEPTNUM_SPS0_TXFIFO_FULL_INTR 0xa3 -#define GC_EXCEPTNUM_SPS0_TXFIFO_LVL_INTR 0xa4 -#define GC_EXCEPTNUM_TEMP0_ADC_ICLKDV_INT 0xa5 -#define GC_EXCEPTNUM_TEMP0_COMP_OVERFLOW_INT 0xa6 -#define GC_EXCEPTNUM_TIMEHS0_TIMINT1 0xa7 -#define GC_EXCEPTNUM_TIMEHS0_TIMINT2 0xa8 -#define GC_EXCEPTNUM_TIMEHS0_TIMINTC 0xa9 -#define GC_EXCEPTNUM_TIMEHS1_TIMINT1 0xaa -#define GC_EXCEPTNUM_TIMEHS1_TIMINT2 0xab -#define GC_EXCEPTNUM_TIMEHS1_TIMINTC 0xac -#define GC_EXCEPTNUM_TIMELS0_TIMINT0 0xad -#define GC_EXCEPTNUM_TIMELS0_TIMINT1 0xae -#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 0xaf -#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 0xb0 -#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 0xb1 -#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 0xb2 -#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 0xb3 -#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 0xb4 -#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 0xb5 -#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 0xb6 -#define GC_EXCEPTNUM_TRNG0_INTR_BUFFER_FULL_INT 0xb7 -#define GC_EXCEPTNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 0xb8 -#define GC_EXCEPTNUM_TRNG0_INTR_READ_EMPTY_INT 0xb9 -#define GC_EXCEPTNUM_UART0_RXBINT 0xba -#define GC_EXCEPTNUM_UART0_RXFINT 0xbb -#define GC_EXCEPTNUM_UART0_RXINT 0xbc -#define GC_EXCEPTNUM_UART0_RXOVINT 0xbd -#define GC_EXCEPTNUM_UART0_RXTOINT 0xbe -#define GC_EXCEPTNUM_UART0_TXINT 0xbf -#define GC_EXCEPTNUM_UART0_TXOVINT 0xc0 -#define GC_EXCEPTNUM_UART1_RXBINT 0xc1 -#define GC_EXCEPTNUM_UART1_RXFINT 0xc2 -#define GC_EXCEPTNUM_UART1_RXINT 0xc3 -#define GC_EXCEPTNUM_UART1_RXOVINT 0xc4 -#define GC_EXCEPTNUM_UART1_RXTOINT 0xc5 -#define GC_EXCEPTNUM_UART1_TXINT 0xc6 -#define GC_EXCEPTNUM_UART1_TXOVINT 0xc7 -#define GC_EXCEPTNUM_UART2_RXBINT 0xc8 -#define GC_EXCEPTNUM_UART2_RXFINT 0xc9 -#define GC_EXCEPTNUM_UART2_RXINT 0xca -#define GC_EXCEPTNUM_UART2_RXOVINT 0xcb -#define GC_EXCEPTNUM_UART2_RXTOINT 0xcc -#define GC_EXCEPTNUM_UART2_TXINT 0xcd -#define GC_EXCEPTNUM_UART2_TXOVINT 0xce -#define GC_EXCEPTNUM_USB0_USBINTR 0xcf -#define GC_EXCEPTNUM_WATCHDOG0_WDOGINT 0xd0 -#define GC_EXCEPTNUM_XO0_CLK_JTR_NOP_SEEN_INT 0xd1 -#define GC_EXCEPTNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 0xd2 -#define GC_EXCEPTNUM_XO0_CLK_TIMER_NOP_SEEN_INT 0xd3 -#define GC_EXCEPTNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 0xd4 -#define GC_EXCEPTNUM_XO0_FAST_CALIB_OVERFLOW_INT 0xd5 -#define GC_EXCEPTNUM_XO0_FAST_CALIB_UNDERRUN_INT 0xd6 -#define GC_EXCEPTNUM_XO0_SLOW_CALIB_OVERFLOW_INT 0xd7 -#define GC_EXCEPTNUM_XO0_SLOW_CALIB_UNDERRUN_INT 0xd8 +#define GC_EXCEPTNUM_CRYPTO0_MOD_OPERAND_OUT_OF_RANGE_INT 0x18 +#define GC_EXCEPTNUM_CRYPTO0_PC_STACK_OVERFLOW_INT 0x19 +#define GC_EXCEPTNUM_CRYPTO0_PGM_FAULT_INT 0x1a +#define GC_EXCEPTNUM_CRYPTO0_TRAP_INT 0x1b +#define GC_EXCEPTNUM_DMA0_INTR_COMPLETE_CHAN_INT 0x1c +#define GC_EXCEPTNUM_DMA0_INTR_ERROR_CHAN_INT 0x1d +#define GC_EXCEPTNUM_DMA0_INTR_PROG_CHAN_INT 0x1e +#define GC_EXCEPTNUM_DMA0_INTR_TIMEOUT_CHAN_INT 0x1f +#define GC_EXCEPTNUM_FLASH0_EDONEINT 0x20 +#define GC_EXCEPTNUM_FLASH0_PDONEINT 0x21 +#define GC_EXCEPTNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT 0x22 +#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_DMEM_PARITY_ALERT_INT 0x23 +#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_DRF_PARITY_ALERT_INT 0x24 +#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_IMEM_PARITY_ALERT_INT 0x25 +#define GC_EXCEPTNUM_GLOBALSEC_CRYPTO0_PGM_FAULT_ALERT_INT 0x26 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_INT 0x27 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_INT 0x28 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_INT 0x29 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_INT 0x2a +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_INT 0x2b +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_INT 0x2c +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_INT 0x2d +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_INT 0x2e +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_INT 0x2f +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 0x30 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 0x31 +#define GC_EXCEPTNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 0x32 +#define GC_EXCEPTNUM_GLOBALSEC_FUSE0_FUSE_DEFAULTS_ALERT_INT 0x33 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 0x34 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 0x35 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 0x36 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 0x37 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 0x38 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 0x39 +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 0x3a +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 0x3b +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 0x3c +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_PROC_OPCODE_HASH_ALERT_INT 0x3d +#define GC_EXCEPTNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 0x3e +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 0x3f +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 0x40 +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 0x41 +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 0x42 +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 0x43 +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_INT 0x44 +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_FAULT_ALERT_INT 0x45 +#define GC_EXCEPTNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 0x46 +#define GC_EXCEPTNUM_GLOBALSEC_PMU_BATTERY_MON_ALERT_INT 0x47 +#define GC_EXCEPTNUM_GLOBALSEC_PMU_PMU_WDOG_ALERT_INT 0x48 +#define GC_EXCEPTNUM_GLOBALSEC_RTC0_RTC_DEAD_ALERT_INT 0x49 +#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 0x4a +#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 0x4b +#define GC_EXCEPTNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 0x4c +#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 0x4d +#define GC_EXCEPTNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 0x4e +#define GC_EXCEPTNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 0x4f +#define GC_EXCEPTNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 0x50 +#define GC_EXCEPTNUM_GPIO0_GPIO0INT 0x51 +#define GC_EXCEPTNUM_GPIO0_GPIO1INT 0x52 +#define GC_EXCEPTNUM_GPIO0_GPIO2INT 0x53 +#define GC_EXCEPTNUM_GPIO0_GPIO3INT 0x54 +#define GC_EXCEPTNUM_GPIO0_GPIO4INT 0x55 +#define GC_EXCEPTNUM_GPIO0_GPIO5INT 0x56 +#define GC_EXCEPTNUM_GPIO0_GPIO6INT 0x57 +#define GC_EXCEPTNUM_GPIO0_GPIO7INT 0x58 +#define GC_EXCEPTNUM_GPIO0_GPIO8INT 0x59 +#define GC_EXCEPTNUM_GPIO0_GPIO9INT 0x5a +#define GC_EXCEPTNUM_GPIO0_GPIO10INT 0x5b +#define GC_EXCEPTNUM_GPIO0_GPIO11INT 0x5c +#define GC_EXCEPTNUM_GPIO0_GPIO12INT 0x5d +#define GC_EXCEPTNUM_GPIO0_GPIO13INT 0x5e +#define GC_EXCEPTNUM_GPIO0_GPIO14INT 0x5f +#define GC_EXCEPTNUM_GPIO0_GPIO15INT 0x60 +#define GC_EXCEPTNUM_GPIO0_GPIOCOMBINT 0x61 +#define GC_EXCEPTNUM_GPIO1_GPIO0INT 0x62 +#define GC_EXCEPTNUM_GPIO1_GPIO1INT 0x63 +#define GC_EXCEPTNUM_GPIO1_GPIO2INT 0x64 +#define GC_EXCEPTNUM_GPIO1_GPIO3INT 0x65 +#define GC_EXCEPTNUM_GPIO1_GPIO4INT 0x66 +#define GC_EXCEPTNUM_GPIO1_GPIO5INT 0x67 +#define GC_EXCEPTNUM_GPIO1_GPIO6INT 0x68 +#define GC_EXCEPTNUM_GPIO1_GPIO7INT 0x69 +#define GC_EXCEPTNUM_GPIO1_GPIO8INT 0x6a +#define GC_EXCEPTNUM_GPIO1_GPIO9INT 0x6b +#define GC_EXCEPTNUM_GPIO1_GPIO10INT 0x6c +#define GC_EXCEPTNUM_GPIO1_GPIO11INT 0x6d +#define GC_EXCEPTNUM_GPIO1_GPIO12INT 0x6e +#define GC_EXCEPTNUM_GPIO1_GPIO13INT 0x6f +#define GC_EXCEPTNUM_GPIO1_GPIO14INT 0x70 +#define GC_EXCEPTNUM_GPIO1_GPIO15INT 0x71 +#define GC_EXCEPTNUM_GPIO1_GPIOCOMBINT 0x72 +#define GC_EXCEPTNUM_I2C0_I2CINT 0x73 +#define GC_EXCEPTNUM_I2C1_I2CINT 0x74 +#define GC_EXCEPTNUM_I2CS0_INTR_READ_BEGIN_INT 0x75 +#define GC_EXCEPTNUM_I2CS0_INTR_READ_COMPLETE_INT 0x76 +#define GC_EXCEPTNUM_I2CS0_INTR_WRITE_COMPLETE_INT 0x77 +#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_CIPHER_INT 0x78 +#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 0x79 +#define GC_EXCEPTNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 0x7a +#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 0x7b +#define GC_EXCEPTNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 0x7c +#define GC_EXCEPTNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 0x7d +#define GC_EXCEPTNUM_KEYMGR0_DSHA_INT 0x7e +#define GC_EXCEPTNUM_PMU_INTR_WAKEUP_INT 0x7f +#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_FED_INT 0x80 +#define GC_EXCEPTNUM_RBOX0_INTR_AC_PRESENT_RED_INT 0x81 +#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 0x82 +#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 0x83 +#define GC_EXCEPTNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 0x84 +#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_FED_INT 0x85 +#define GC_EXCEPTNUM_RBOX0_INTR_EC_RST_RED_INT 0x86 +#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_FED_INT 0x87 +#define GC_EXCEPTNUM_RBOX0_INTR_KEY0_IN_RED_INT 0x88 +#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_FED_INT 0x89 +#define GC_EXCEPTNUM_RBOX0_INTR_KEY1_IN_RED_INT 0x8a +#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_FED_INT 0x8b +#define GC_EXCEPTNUM_RBOX0_INTR_PWRB_IN_RED_INT 0x8c +#define GC_EXCEPTNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT 0x8d +#define GC_EXCEPTNUM_SPI0_SPITXINT 0x8e +#define GC_EXCEPTNUM_SPI1_SPITXINT 0x8f +#define GC_EXCEPTNUM_SPS0_CS_ASSERT_INTR 0x90 +#define GC_EXCEPTNUM_SPS0_CS_DEASSERT_INTR 0x91 +#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 0x92 +#define GC_EXCEPTNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 0x93 +#define GC_EXCEPTNUM_SPS0_INTR_CMD_MEM_OVFL_INT 0x94 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 0x95 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 0x96 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 0x97 +#define GC_EXCEPTNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 0x98 +#define GC_EXCEPTNUM_SPS0_RXFIFO_LVL_INTR 0x99 +#define GC_EXCEPTNUM_SPS0_RXFIFO_OVERFLOW_INTR 0x9a +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT0 0x9b +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT1 0x9c +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT2 0x9d +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT3 0x9e +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT4 0x9f +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT5 0xa0 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT6 0xa1 +#define GC_EXCEPTNUM_SPS0_SPSCTRLINT7 0xa2 +#define GC_EXCEPTNUM_SPS0_TXFIFO_EMPTY_INTR 0xa3 +#define GC_EXCEPTNUM_SPS0_TXFIFO_FULL_INTR 0xa4 +#define GC_EXCEPTNUM_SPS0_TXFIFO_LVL_INTR 0xa5 +#define GC_EXCEPTNUM_TEMP0_ADC_ICLKDV_INT 0xa6 +#define GC_EXCEPTNUM_TEMP0_COMP_OVERFLOW_INT 0xa7 +#define GC_EXCEPTNUM_TIMEHS0_TIMINT1 0xa8 +#define GC_EXCEPTNUM_TIMEHS0_TIMINT2 0xa9 +#define GC_EXCEPTNUM_TIMEHS0_TIMINTC 0xaa +#define GC_EXCEPTNUM_TIMEHS1_TIMINT1 0xab +#define GC_EXCEPTNUM_TIMEHS1_TIMINT2 0xac +#define GC_EXCEPTNUM_TIMEHS1_TIMINTC 0xad +#define GC_EXCEPTNUM_TIMELS0_TIMINT0 0xae +#define GC_EXCEPTNUM_TIMELS0_TIMINT1 0xaf +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 0xb0 +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 0xb1 +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 0xb2 +#define GC_EXCEPTNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 0xb3 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 0xb4 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 0xb5 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 0xb6 +#define GC_EXCEPTNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 0xb7 +#define GC_EXCEPTNUM_TRNG0_INTR_BUFFER_FULL_INT 0xb8 +#define GC_EXCEPTNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 0xb9 +#define GC_EXCEPTNUM_TRNG0_INTR_READ_EMPTY_INT 0xba +#define GC_EXCEPTNUM_UART0_RXBINT 0xbb +#define GC_EXCEPTNUM_UART0_RXFINT 0xbc +#define GC_EXCEPTNUM_UART0_RXINT 0xbd +#define GC_EXCEPTNUM_UART0_RXOVINT 0xbe +#define GC_EXCEPTNUM_UART0_RXTOINT 0xbf +#define GC_EXCEPTNUM_UART0_TXINT 0xc0 +#define GC_EXCEPTNUM_UART0_TXOVINT 0xc1 +#define GC_EXCEPTNUM_UART1_RXBINT 0xc2 +#define GC_EXCEPTNUM_UART1_RXFINT 0xc3 +#define GC_EXCEPTNUM_UART1_RXINT 0xc4 +#define GC_EXCEPTNUM_UART1_RXOVINT 0xc5 +#define GC_EXCEPTNUM_UART1_RXTOINT 0xc6 +#define GC_EXCEPTNUM_UART1_TXINT 0xc7 +#define GC_EXCEPTNUM_UART1_TXOVINT 0xc8 +#define GC_EXCEPTNUM_UART2_RXBINT 0xc9 +#define GC_EXCEPTNUM_UART2_RXFINT 0xca +#define GC_EXCEPTNUM_UART2_RXINT 0xcb +#define GC_EXCEPTNUM_UART2_RXOVINT 0xcc +#define GC_EXCEPTNUM_UART2_RXTOINT 0xcd +#define GC_EXCEPTNUM_UART2_TXINT 0xce +#define GC_EXCEPTNUM_UART2_TXOVINT 0xcf +#define GC_EXCEPTNUM_USB0_USBINTR 0xd0 +#define GC_EXCEPTNUM_WATCHDOG0_WDOGINT 0xd1 +#define GC_EXCEPTNUM_XO0_CLK_JTR_NOP_SEEN_INT 0xd2 +#define GC_EXCEPTNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 0xd3 +#define GC_EXCEPTNUM_XO0_CLK_TIMER_NOP_SEEN_INT 0xd4 +#define GC_EXCEPTNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 0xd5 +#define GC_EXCEPTNUM_XO0_FAST_CALIB_OVERFLOW_INT 0xd6 +#define GC_EXCEPTNUM_XO0_FAST_CALIB_UNDERRUN_INT 0xd7 +#define GC_EXCEPTNUM_XO0_SLOW_CALIB_OVERFLOW_INT 0xd8 +#define GC_EXCEPTNUM_XO0_SLOW_CALIB_UNDERRUN_INT 0xd9 +#define GC_EXCEPTIONS_COUNT 217 #define GC_IRQNUM_RESET 0 #define GC_IRQNUM_NMI 0 #define GC_IRQNUM_HARDFAULT 0 @@ -363,199 +365,201 @@ #define GC_IRQNUM_CRYPTO0_HOST_CMD_RECV_INT 5 #define GC_IRQNUM_CRYPTO0_LOOP_STACK_OVERFLOW_INT 6 #define GC_IRQNUM_CRYPTO0_LOOP_STACK_UNDERFLOW_INT 7 -#define GC_IRQNUM_CRYPTO0_PC_STACK_OVERFLOW_INT 8 -#define GC_IRQNUM_CRYPTO0_PGM_FAULT_INT 9 -#define GC_IRQNUM_CRYPTO0_TRAP_INT 10 -#define GC_IRQNUM_DMA0_INTR_COMPLETE_CHAN_INT 11 -#define GC_IRQNUM_DMA0_INTR_ERROR_CHAN_INT 12 -#define GC_IRQNUM_DMA0_INTR_PROG_CHAN_INT 13 -#define GC_IRQNUM_DMA0_INTR_TIMEOUT_CHAN_INT 14 -#define GC_IRQNUM_FLASH0_EDONEINT 15 -#define GC_IRQNUM_FLASH0_PDONEINT 16 -#define GC_IRQNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT 17 -#define GC_IRQNUM_GLOBALSEC_CRYPTO0_DMEM_PARITY_ALERT_INT 18 -#define GC_IRQNUM_GLOBALSEC_CRYPTO0_DRF_PARITY_ALERT_INT 19 -#define GC_IRQNUM_GLOBALSEC_CRYPTO0_IMEM_PARITY_ALERT_INT 20 -#define GC_IRQNUM_GLOBALSEC_CRYPTO0_PGM_FAULT_ALERT_INT 21 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_INT 22 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_INT 23 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_INT 24 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_INT 25 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_INT 26 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_INT 27 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_INT 28 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_INT 29 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_INT 30 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 31 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 32 -#define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 33 -#define GC_IRQNUM_GLOBALSEC_FUSE0_FUSE_DEFAULTS_ALERT_INT 34 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 35 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 36 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 37 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 38 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 39 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 40 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 41 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 42 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 43 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_PROC_OPCODE_HASH_ALERT_INT 44 -#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 45 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 46 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 47 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 48 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 49 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 50 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_INT 51 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_FAULT_ALERT_INT 52 -#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 53 -#define GC_IRQNUM_GLOBALSEC_PMU_BATTERY_MON_ALERT_INT 54 -#define GC_IRQNUM_GLOBALSEC_PMU_PMU_WDOG_ALERT_INT 55 -#define GC_IRQNUM_GLOBALSEC_RTC0_RTC_DEAD_ALERT_INT 56 -#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 57 -#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 58 -#define GC_IRQNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 59 -#define GC_IRQNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 60 -#define GC_IRQNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 61 -#define GC_IRQNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 62 -#define GC_IRQNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 63 -#define GC_IRQNUM_GPIO0_GPIO0INT 64 -#define GC_IRQNUM_GPIO0_GPIO1INT 65 -#define GC_IRQNUM_GPIO0_GPIO2INT 66 -#define GC_IRQNUM_GPIO0_GPIO3INT 67 -#define GC_IRQNUM_GPIO0_GPIO4INT 68 -#define GC_IRQNUM_GPIO0_GPIO5INT 69 -#define GC_IRQNUM_GPIO0_GPIO6INT 70 -#define GC_IRQNUM_GPIO0_GPIO7INT 71 -#define GC_IRQNUM_GPIO0_GPIO8INT 72 -#define GC_IRQNUM_GPIO0_GPIO9INT 73 -#define GC_IRQNUM_GPIO0_GPIO10INT 74 -#define GC_IRQNUM_GPIO0_GPIO11INT 75 -#define GC_IRQNUM_GPIO0_GPIO12INT 76 -#define GC_IRQNUM_GPIO0_GPIO13INT 77 -#define GC_IRQNUM_GPIO0_GPIO14INT 78 -#define GC_IRQNUM_GPIO0_GPIO15INT 79 -#define GC_IRQNUM_GPIO0_GPIOCOMBINT 80 -#define GC_IRQNUM_GPIO1_GPIO0INT 81 -#define GC_IRQNUM_GPIO1_GPIO1INT 82 -#define GC_IRQNUM_GPIO1_GPIO2INT 83 -#define GC_IRQNUM_GPIO1_GPIO3INT 84 -#define GC_IRQNUM_GPIO1_GPIO4INT 85 -#define GC_IRQNUM_GPIO1_GPIO5INT 86 -#define GC_IRQNUM_GPIO1_GPIO6INT 87 -#define GC_IRQNUM_GPIO1_GPIO7INT 88 -#define GC_IRQNUM_GPIO1_GPIO8INT 89 -#define GC_IRQNUM_GPIO1_GPIO9INT 90 -#define GC_IRQNUM_GPIO1_GPIO10INT 91 -#define GC_IRQNUM_GPIO1_GPIO11INT 92 -#define GC_IRQNUM_GPIO1_GPIO12INT 93 -#define GC_IRQNUM_GPIO1_GPIO13INT 94 -#define GC_IRQNUM_GPIO1_GPIO14INT 95 -#define GC_IRQNUM_GPIO1_GPIO15INT 96 -#define GC_IRQNUM_GPIO1_GPIOCOMBINT 97 -#define GC_IRQNUM_I2C0_I2CINT 98 -#define GC_IRQNUM_I2C1_I2CINT 99 -#define GC_IRQNUM_I2CS0_INTR_READ_BEGIN_INT 100 -#define GC_IRQNUM_I2CS0_INTR_READ_COMPLETE_INT 101 -#define GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT 102 -#define GC_IRQNUM_KEYMGR0_AES_DONE_CIPHER_INT 103 -#define GC_IRQNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 104 -#define GC_IRQNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 105 -#define GC_IRQNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 106 -#define GC_IRQNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 107 -#define GC_IRQNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 108 -#define GC_IRQNUM_KEYMGR0_DSHA_INT 109 -#define GC_IRQNUM_PMU_INTR_WAKEUP_INT 110 -#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_FED_INT 111 -#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_RED_INT 112 -#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 113 -#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 114 -#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 115 -#define GC_IRQNUM_RBOX0_INTR_EC_RST_FED_INT 116 -#define GC_IRQNUM_RBOX0_INTR_EC_RST_RED_INT 117 -#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_FED_INT 118 -#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_RED_INT 119 -#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_FED_INT 120 -#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_RED_INT 121 -#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_FED_INT 122 -#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_RED_INT 123 -#define GC_IRQNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT 124 -#define GC_IRQNUM_SPI0_SPITXINT 125 -#define GC_IRQNUM_SPI1_SPITXINT 126 -#define GC_IRQNUM_SPS0_CS_ASSERT_INTR 127 -#define GC_IRQNUM_SPS0_CS_DEASSERT_INTR 128 -#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 129 -#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 130 -#define GC_IRQNUM_SPS0_INTR_CMD_MEM_OVFL_INT 131 -#define GC_IRQNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 132 -#define GC_IRQNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 133 -#define GC_IRQNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 134 -#define GC_IRQNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 135 -#define GC_IRQNUM_SPS0_RXFIFO_LVL_INTR 136 -#define GC_IRQNUM_SPS0_RXFIFO_OVERFLOW_INTR 137 -#define GC_IRQNUM_SPS0_SPSCTRLINT0 138 -#define GC_IRQNUM_SPS0_SPSCTRLINT1 139 -#define GC_IRQNUM_SPS0_SPSCTRLINT2 140 -#define GC_IRQNUM_SPS0_SPSCTRLINT3 141 -#define GC_IRQNUM_SPS0_SPSCTRLINT4 142 -#define GC_IRQNUM_SPS0_SPSCTRLINT5 143 -#define GC_IRQNUM_SPS0_SPSCTRLINT6 144 -#define GC_IRQNUM_SPS0_SPSCTRLINT7 145 -#define GC_IRQNUM_SPS0_TXFIFO_EMPTY_INTR 146 -#define GC_IRQNUM_SPS0_TXFIFO_FULL_INTR 147 -#define GC_IRQNUM_SPS0_TXFIFO_LVL_INTR 148 -#define GC_IRQNUM_TEMP0_ADC_ICLKDV_INT 149 -#define GC_IRQNUM_TEMP0_COMP_OVERFLOW_INT 150 -#define GC_IRQNUM_TIMEHS0_TIMINT1 151 -#define GC_IRQNUM_TIMEHS0_TIMINT2 152 -#define GC_IRQNUM_TIMEHS0_TIMINTC 153 -#define GC_IRQNUM_TIMEHS1_TIMINT1 154 -#define GC_IRQNUM_TIMEHS1_TIMINT2 155 -#define GC_IRQNUM_TIMEHS1_TIMINTC 156 -#define GC_IRQNUM_TIMELS0_TIMINT0 157 -#define GC_IRQNUM_TIMELS0_TIMINT1 158 -#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 159 -#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 160 -#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 161 -#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 162 -#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 163 -#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 164 -#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 165 -#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 166 -#define GC_IRQNUM_TRNG0_INTR_BUFFER_FULL_INT 167 -#define GC_IRQNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 168 -#define GC_IRQNUM_TRNG0_INTR_READ_EMPTY_INT 169 -#define GC_IRQNUM_UART0_RXBINT 170 -#define GC_IRQNUM_UART0_RXFINT 171 -#define GC_IRQNUM_UART0_RXINT 172 -#define GC_IRQNUM_UART0_RXOVINT 173 -#define GC_IRQNUM_UART0_RXTOINT 174 -#define GC_IRQNUM_UART0_TXINT 175 -#define GC_IRQNUM_UART0_TXOVINT 176 -#define GC_IRQNUM_UART1_RXBINT 177 -#define GC_IRQNUM_UART1_RXFINT 178 -#define GC_IRQNUM_UART1_RXINT 179 -#define GC_IRQNUM_UART1_RXOVINT 180 -#define GC_IRQNUM_UART1_RXTOINT 181 -#define GC_IRQNUM_UART1_TXINT 182 -#define GC_IRQNUM_UART1_TXOVINT 183 -#define GC_IRQNUM_UART2_RXBINT 184 -#define GC_IRQNUM_UART2_RXFINT 185 -#define GC_IRQNUM_UART2_RXINT 186 -#define GC_IRQNUM_UART2_RXOVINT 187 -#define GC_IRQNUM_UART2_RXTOINT 188 -#define GC_IRQNUM_UART2_TXINT 189 -#define GC_IRQNUM_UART2_TXOVINT 190 -#define GC_IRQNUM_USB0_USBINTR 191 -#define GC_IRQNUM_WATCHDOG0_WDOGINT 192 -#define GC_IRQNUM_XO0_CLK_JTR_NOP_SEEN_INT 193 -#define GC_IRQNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 194 -#define GC_IRQNUM_XO0_CLK_TIMER_NOP_SEEN_INT 195 -#define GC_IRQNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 196 -#define GC_IRQNUM_XO0_FAST_CALIB_OVERFLOW_INT 197 -#define GC_IRQNUM_XO0_FAST_CALIB_UNDERRUN_INT 198 -#define GC_IRQNUM_XO0_SLOW_CALIB_OVERFLOW_INT 199 -#define GC_IRQNUM_XO0_SLOW_CALIB_UNDERRUN_INT 200 +#define GC_IRQNUM_CRYPTO0_MOD_OPERAND_OUT_OF_RANGE_INT 8 +#define GC_IRQNUM_CRYPTO0_PC_STACK_OVERFLOW_INT 9 +#define GC_IRQNUM_CRYPTO0_PGM_FAULT_INT 10 +#define GC_IRQNUM_CRYPTO0_TRAP_INT 11 +#define GC_IRQNUM_DMA0_INTR_COMPLETE_CHAN_INT 12 +#define GC_IRQNUM_DMA0_INTR_ERROR_CHAN_INT 13 +#define GC_IRQNUM_DMA0_INTR_PROG_CHAN_INT 14 +#define GC_IRQNUM_DMA0_INTR_TIMEOUT_CHAN_INT 15 +#define GC_IRQNUM_FLASH0_EDONEINT 16 +#define GC_IRQNUM_FLASH0_PDONEINT 17 +#define GC_IRQNUM_GLOBALSEC_CAMO0_BREACH_ALERT_INT 18 +#define GC_IRQNUM_GLOBALSEC_CRYPTO0_DMEM_PARITY_ALERT_INT 19 +#define GC_IRQNUM_GLOBALSEC_CRYPTO0_DRF_PARITY_ALERT_INT 20 +#define GC_IRQNUM_GLOBALSEC_CRYPTO0_IMEM_PARITY_ALERT_INT 21 +#define GC_IRQNUM_GLOBALSEC_CRYPTO0_PGM_FAULT_ALERT_INT 22 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_BUS_ERR_ALERT_INT 23 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_D_IF_UPDATE_WATCHDOG_ALERT_INT 24 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_BUS_ERR_ALERT_INT 25 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_I_IF_UPDATE_WATCHDOG_ALERT_INT 26 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_BUS_ERR_ALERT_INT 27 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_CPU0_S_IF_UPDATE_WATCHDOG_ALERT_INT 28 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DDMA0_IF_BUS_ERR_ALERT_INT 29 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DDMA0_IF_UPDATE_WATCHDOG_ALERT_INT 30 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DSPS0_IF_BUS_ERR_ALERT_INT 31 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DSPS0_IF_UPDATE_WATCHDOG_ALERT_INT 32 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_BUS_ERR_ALERT_INT 33 +#define GC_IRQNUM_GLOBALSEC_DBCTRL_DUSB0_IF_UPDATE_WATCHDOG_ALERT_INT 34 +#define GC_IRQNUM_GLOBALSEC_FUSE0_FUSE_DEFAULTS_ALERT_INT 35 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPA_INT 36 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPB_INT 37 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_ALERT_GROUPC_INT 38 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_DIFF_FAIL_ALERT_INT 39 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW0_ALERT_INT 40 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW1_ALERT_INT 41 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW2_ALERT_INT 42 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_FW3_ALERT_INT 43 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_HEARTBEAT_FAIL_ALERT_INT 44 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_PROC_OPCODE_HASH_ALERT_INT 45 +#define GC_IRQNUM_GLOBALSEC_GLOBALSEC_SRAM_PARITY_SCRUB_ALERT_INT 46 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_EXEC_CTR_MAX_ALERT_INT 47 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_AES_HKEY_ALERT_INT 48 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_CERT_LOOKUP_ALERT_INT 49 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_FLASH_ENTRY_ALERT_INT 50 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_PW_ALERT_INT 51 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_EXEC_CTR_MAX_ALERT_INT 52 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_FAULT_ALERT_INT 53 +#define GC_IRQNUM_GLOBALSEC_KEYMGR0_SHA_HKEY_ALERT_INT 54 +#define GC_IRQNUM_GLOBALSEC_PMU_BATTERY_MON_ALERT_INT 55 +#define GC_IRQNUM_GLOBALSEC_PMU_PMU_WDOG_ALERT_INT 56 +#define GC_IRQNUM_GLOBALSEC_RTC0_RTC_DEAD_ALERT_INT 57 +#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_ALERT_INT 58 +#define GC_IRQNUM_GLOBALSEC_TEMP0_MAX_TEMP_DIFF_ALERT_INT 59 +#define GC_IRQNUM_GLOBALSEC_TEMP0_MIN_TEMP_ALERT_INT 60 +#define GC_IRQNUM_GLOBALSEC_TRNG0_OUT_OF_SPEC_ALERT_INT 61 +#define GC_IRQNUM_GLOBALSEC_TRNG0_TIMEOUT_ALERT_INT 62 +#define GC_IRQNUM_GLOBALSEC_VOLT0_VOLT_ERR_ALERT_INT 63 +#define GC_IRQNUM_GLOBALSEC_XO0_JITTERY_TRIM_DIS_ALERT_INT 64 +#define GC_IRQNUM_GPIO0_GPIO0INT 65 +#define GC_IRQNUM_GPIO0_GPIO1INT 66 +#define GC_IRQNUM_GPIO0_GPIO2INT 67 +#define GC_IRQNUM_GPIO0_GPIO3INT 68 +#define GC_IRQNUM_GPIO0_GPIO4INT 69 +#define GC_IRQNUM_GPIO0_GPIO5INT 70 +#define GC_IRQNUM_GPIO0_GPIO6INT 71 +#define GC_IRQNUM_GPIO0_GPIO7INT 72 +#define GC_IRQNUM_GPIO0_GPIO8INT 73 +#define GC_IRQNUM_GPIO0_GPIO9INT 74 +#define GC_IRQNUM_GPIO0_GPIO10INT 75 +#define GC_IRQNUM_GPIO0_GPIO11INT 76 +#define GC_IRQNUM_GPIO0_GPIO12INT 77 +#define GC_IRQNUM_GPIO0_GPIO13INT 78 +#define GC_IRQNUM_GPIO0_GPIO14INT 79 +#define GC_IRQNUM_GPIO0_GPIO15INT 80 +#define GC_IRQNUM_GPIO0_GPIOCOMBINT 81 +#define GC_IRQNUM_GPIO1_GPIO0INT 82 +#define GC_IRQNUM_GPIO1_GPIO1INT 83 +#define GC_IRQNUM_GPIO1_GPIO2INT 84 +#define GC_IRQNUM_GPIO1_GPIO3INT 85 +#define GC_IRQNUM_GPIO1_GPIO4INT 86 +#define GC_IRQNUM_GPIO1_GPIO5INT 87 +#define GC_IRQNUM_GPIO1_GPIO6INT 88 +#define GC_IRQNUM_GPIO1_GPIO7INT 89 +#define GC_IRQNUM_GPIO1_GPIO8INT 90 +#define GC_IRQNUM_GPIO1_GPIO9INT 91 +#define GC_IRQNUM_GPIO1_GPIO10INT 92 +#define GC_IRQNUM_GPIO1_GPIO11INT 93 +#define GC_IRQNUM_GPIO1_GPIO12INT 94 +#define GC_IRQNUM_GPIO1_GPIO13INT 95 +#define GC_IRQNUM_GPIO1_GPIO14INT 96 +#define GC_IRQNUM_GPIO1_GPIO15INT 97 +#define GC_IRQNUM_GPIO1_GPIOCOMBINT 98 +#define GC_IRQNUM_I2C0_I2CINT 99 +#define GC_IRQNUM_I2C1_I2CINT 100 +#define GC_IRQNUM_I2CS0_INTR_READ_BEGIN_INT 101 +#define GC_IRQNUM_I2CS0_INTR_READ_COMPLETE_INT 102 +#define GC_IRQNUM_I2CS0_INTR_WRITE_COMPLETE_INT 103 +#define GC_IRQNUM_KEYMGR0_AES_DONE_CIPHER_INT 104 +#define GC_IRQNUM_KEYMGR0_AES_DONE_KEYEXPANSION_INT 105 +#define GC_IRQNUM_KEYMGR0_AES_DONE_WIPE_SECRETS_INT 106 +#define GC_IRQNUM_KEYMGR0_AES_RFIFO_OVERFLOW_INT 107 +#define GC_IRQNUM_KEYMGR0_AES_RFIFO_UNDERFLOW_INT 108 +#define GC_IRQNUM_KEYMGR0_AES_WFIFO_OVERFLOW_INT 109 +#define GC_IRQNUM_KEYMGR0_DSHA_INT 110 +#define GC_IRQNUM_PMU_INTR_WAKEUP_INT 111 +#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_FED_INT 112 +#define GC_IRQNUM_RBOX0_INTR_AC_PRESENT_RED_INT 113 +#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO0_RDY_INT 114 +#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO1_RDY_INT 115 +#define GC_IRQNUM_RBOX0_INTR_BUTTON_COMBO2_RDY_INT 116 +#define GC_IRQNUM_RBOX0_INTR_EC_RST_FED_INT 117 +#define GC_IRQNUM_RBOX0_INTR_EC_RST_RED_INT 118 +#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_FED_INT 119 +#define GC_IRQNUM_RBOX0_INTR_KEY0_IN_RED_INT 120 +#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_FED_INT 121 +#define GC_IRQNUM_RBOX0_INTR_KEY1_IN_RED_INT 122 +#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_FED_INT 123 +#define GC_IRQNUM_RBOX0_INTR_PWRB_IN_RED_INT 124 +#define GC_IRQNUM_RDD0_INTR_DEBUG_STATE_DETECTED_INT 125 +#define GC_IRQNUM_SPI0_SPITXINT 126 +#define GC_IRQNUM_SPI1_SPITXINT 127 +#define GC_IRQNUM_SPS0_CS_ASSERT_INTR 128 +#define GC_IRQNUM_SPS0_CS_DEASSERT_INTR 129 +#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_NOT_EMPTY_INT 130 +#define GC_IRQNUM_SPS0_INTR_CMD_ADDR_FIFO_OVFL_INT 131 +#define GC_IRQNUM_SPS0_INTR_CMD_MEM_OVFL_INT 132 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE0_LVL_INT 133 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE1_LVL_INT 134 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE2_LVL_INT 135 +#define GC_IRQNUM_SPS0_INTR_RAM_PAGE3_LVL_INT 136 +#define GC_IRQNUM_SPS0_RXFIFO_LVL_INTR 137 +#define GC_IRQNUM_SPS0_RXFIFO_OVERFLOW_INTR 138 +#define GC_IRQNUM_SPS0_SPSCTRLINT0 139 +#define GC_IRQNUM_SPS0_SPSCTRLINT1 140 +#define GC_IRQNUM_SPS0_SPSCTRLINT2 141 +#define GC_IRQNUM_SPS0_SPSCTRLINT3 142 +#define GC_IRQNUM_SPS0_SPSCTRLINT4 143 +#define GC_IRQNUM_SPS0_SPSCTRLINT5 144 +#define GC_IRQNUM_SPS0_SPSCTRLINT6 145 +#define GC_IRQNUM_SPS0_SPSCTRLINT7 146 +#define GC_IRQNUM_SPS0_TXFIFO_EMPTY_INTR 147 +#define GC_IRQNUM_SPS0_TXFIFO_FULL_INTR 148 +#define GC_IRQNUM_SPS0_TXFIFO_LVL_INTR 149 +#define GC_IRQNUM_TEMP0_ADC_ICLKDV_INT 150 +#define GC_IRQNUM_TEMP0_COMP_OVERFLOW_INT 151 +#define GC_IRQNUM_TIMEHS0_TIMINT1 152 +#define GC_IRQNUM_TIMEHS0_TIMINT2 153 +#define GC_IRQNUM_TIMEHS0_TIMINTC 154 +#define GC_IRQNUM_TIMEHS1_TIMINT1 155 +#define GC_IRQNUM_TIMEHS1_TIMINT2 156 +#define GC_IRQNUM_TIMEHS1_TIMINTC 157 +#define GC_IRQNUM_TIMELS0_TIMINT0 158 +#define GC_IRQNUM_TIMELS0_TIMINT1 159 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT0_INT 160 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT1_INT 161 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT2_INT 162 +#define GC_IRQNUM_TIMEUS0_INTR_MAX_COUNT_HIT3_INT 163 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT0_INT 164 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT1_INT 165 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT2_INT 166 +#define GC_IRQNUM_TIMEUS0_INTR_PROG_COUNT_HIT3_INT 167 +#define GC_IRQNUM_TRNG0_INTR_BUFFER_FULL_INT 168 +#define GC_IRQNUM_TRNG0_INTR_ONE_SHOT_DONE_INT 169 +#define GC_IRQNUM_TRNG0_INTR_READ_EMPTY_INT 170 +#define GC_IRQNUM_UART0_RXBINT 171 +#define GC_IRQNUM_UART0_RXFINT 172 +#define GC_IRQNUM_UART0_RXINT 173 +#define GC_IRQNUM_UART0_RXOVINT 174 +#define GC_IRQNUM_UART0_RXTOINT 175 +#define GC_IRQNUM_UART0_TXINT 176 +#define GC_IRQNUM_UART0_TXOVINT 177 +#define GC_IRQNUM_UART1_RXBINT 178 +#define GC_IRQNUM_UART1_RXFINT 179 +#define GC_IRQNUM_UART1_RXINT 180 +#define GC_IRQNUM_UART1_RXOVINT 181 +#define GC_IRQNUM_UART1_RXTOINT 182 +#define GC_IRQNUM_UART1_TXINT 183 +#define GC_IRQNUM_UART1_TXOVINT 184 +#define GC_IRQNUM_UART2_RXBINT 185 +#define GC_IRQNUM_UART2_RXFINT 186 +#define GC_IRQNUM_UART2_RXINT 187 +#define GC_IRQNUM_UART2_RXOVINT 188 +#define GC_IRQNUM_UART2_RXTOINT 189 +#define GC_IRQNUM_UART2_TXINT 190 +#define GC_IRQNUM_UART2_TXOVINT 191 +#define GC_IRQNUM_USB0_USBINTR 192 +#define GC_IRQNUM_WATCHDOG0_WDOGINT 193 +#define GC_IRQNUM_XO0_CLK_JTR_NOP_SEEN_INT 194 +#define GC_IRQNUM_XO0_CLK_JTR_SW_TRIM_DONE_INT 195 +#define GC_IRQNUM_XO0_CLK_TIMER_NOP_SEEN_INT 196 +#define GC_IRQNUM_XO0_CLK_TIMER_SW_TRIM_DONE_INT 197 +#define GC_IRQNUM_XO0_FAST_CALIB_OVERFLOW_INT 198 +#define GC_IRQNUM_XO0_FAST_CALIB_UNDERRUN_INT 199 +#define GC_IRQNUM_XO0_SLOW_CALIB_OVERFLOW_INT 200 +#define GC_IRQNUM_XO0_SLOW_CALIB_UNDERRUN_INT 201 +#define GC_INTERRUPTS_COUNT 217 #define GC_CAMO0_BASE_ADDR 0x40560000 #define GC_CRYPTO0_BASE_ADDR 0x40420000 #define GC_DMA0_BASE_ADDR 0x40430000 @@ -599,7 +603,7 @@ #define GC_CAMO_VERSION_OFFSET 0x8 #define GC_CAMO_VERSION_DEFAULT 0x3011319 #define GC_CRYPTO_VERSION_OFFSET 0x0 -#define GC_CRYPTO_VERSION_DEFAULT 0x28011ed5 +#define GC_CRYPTO_VERSION_DEFAULT 0x290122a1 #define GC_CRYPTO_CONTROL_OFFSET 0x4 #define GC_CRYPTO_CONTROL_DEFAULT 0x0 #define GC_CRYPTO_PARITY_CFG_OFFSET 0x8 @@ -624,19 +628,21 @@ #define GC_CRYPTO_AUX_CC_DEFAULT 0x0 #define GC_CRYPTO_RAND_STALL_CTL_OFFSET 0x30 #define GC_CRYPTO_RAND_STALL_CTL_DEFAULT 0x5 -#define GC_CRYPTO_IMEM_PARITY_ERRS_CTR_STATE_OFFSET 0x34 +#define GC_CRYPTO_RAND256_OFFSET 0x34 +#define GC_CRYPTO_RAND256_DEFAULT 0x1 +#define GC_CRYPTO_IMEM_PARITY_ERRS_CTR_STATE_OFFSET 0x38 #define GC_CRYPTO_IMEM_PARITY_ERRS_CTR_STATE_DEFAULT 0x0 -#define GC_CRYPTO_DMEM_PARITY_ERRS_CTR_STATE_OFFSET 0x38 +#define GC_CRYPTO_DMEM_PARITY_ERRS_CTR_STATE_OFFSET 0x3c #define GC_CRYPTO_DMEM_PARITY_ERRS_CTR_STATE_DEFAULT 0x0 -#define GC_CRYPTO_DRF_PARITY_ERRS_CTR_STATE_OFFSET 0x3c +#define GC_CRYPTO_DRF_PARITY_ERRS_CTR_STATE_OFFSET 0x40 #define GC_CRYPTO_DRF_PARITY_ERRS_CTR_STATE_DEFAULT 0x0 -#define GC_CRYPTO_PGM_LFSR_OFFSET 0x40 +#define GC_CRYPTO_PGM_LFSR_OFFSET 0x44 #define GC_CRYPTO_PGM_LFSR_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT0_OFFSET 0x44 +#define GC_CRYPTO_DEBUG_BRKPT0_OFFSET 0x48 #define GC_CRYPTO_DEBUG_BRKPT0_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT1_OFFSET 0x48 +#define GC_CRYPTO_DEBUG_BRKPT1_OFFSET 0x4c #define GC_CRYPTO_DEBUG_BRKPT1_DEFAULT 0x0 -#define GC_CRYPTO_WIPE_SECRETS_OFFSET 0x4c +#define GC_CRYPTO_WIPE_SECRETS_OFFSET 0x50 #define GC_CRYPTO_WIPE_SECRETS_DEFAULT 0x0 #define GC_CRYPTO_DMEM_DUMMY_OFFSET 0x4000 #define GC_CRYPTO_IMEM_DUMMY_OFFSET 0x8000 @@ -1045,539 +1051,541 @@ #define GC_FUSE_ERROR_INJECT_DISABLE 0x0 #define GC_FUSE_VDDQ_RAMP_TIMING_OFFSET 0x24 #define GC_FUSE_VDDQ_RAMP_TIMING_DEFAULT 0x1d4c0 -#define GC_FUSE_VERSION_OFFSET 0x28 -#define GC_FUSE_VERSION_DEFAULT 0xf011cd4 -#define GC_FUSE_BNK0_INTG_CHKSUM_OFFSET 0x2c +#define GC_FUSE_ANTEST_EN_OFFSET 0x28 +#define GC_FUSE_ANTEST_EN_DEFAULT 0x0 +#define GC_FUSE_VERSION_OFFSET 0x2c +#define GC_FUSE_VERSION_DEFAULT 0x12012324 +#define GC_FUSE_BNK0_INTG_CHKSUM_OFFSET 0x30 #define GC_FUSE_BNK0_INTG_CHKSUM_DEFAULT 0x55000000 -#define GC_FUSE_BNK0_INTG_N_WR_LOCK_OFFSET 0x30 -#define GC_FUSE_BNK0_INTG_N_WR_LOCK_DEFAULT 0x55555550 -#define GC_FUSE_DS_GRP0_OFFSET 0x34 +#define GC_FUSE_BNK0_INTG_LOCK_OFFSET 0x34 +#define GC_FUSE_BNK0_INTG_LOCK_DEFAULT 0x55555550 +#define GC_FUSE_DS_GRP0_OFFSET 0x38 #define GC_FUSE_DS_GRP0_DEFAULT 0x55555400 -#define GC_FUSE_DS_GRP1_OFFSET 0x38 +#define GC_FUSE_DS_GRP1_OFFSET 0x3c #define GC_FUSE_DS_GRP1_DEFAULT 0x55555400 -#define GC_FUSE_DS_GRP2_OFFSET 0x3c +#define GC_FUSE_DS_GRP2_OFFSET 0x40 #define GC_FUSE_DS_GRP2_DEFAULT 0x55555400 -#define GC_FUSE_DEV_ID0_OFFSET 0x40 +#define GC_FUSE_DEV_ID0_OFFSET 0x44 #define GC_FUSE_DEV_ID0_DEFAULT 0x0 -#define GC_FUSE_DEV_ID1_OFFSET 0x44 +#define GC_FUSE_DEV_ID1_OFFSET 0x48 #define GC_FUSE_DEV_ID1_DEFAULT 0x0 -#define GC_FUSE_BNK1_INTG_CHKSUM_OFFSET 0x48 +#define GC_FUSE_BNK1_INTG_CHKSUM_OFFSET 0x4c #define GC_FUSE_BNK1_INTG_CHKSUM_DEFAULT 0x55000000 -#define GC_FUSE_BNK1_INTG_N_WR_LOCK_OFFSET 0x4c -#define GC_FUSE_BNK1_INTG_N_WR_LOCK_DEFAULT 0x55555550 -#define GC_FUSE_LB0_POST_OVRD_OFFSET 0x50 +#define GC_FUSE_BNK1_INTG_LOCK_OFFSET 0x50 +#define GC_FUSE_BNK1_INTG_LOCK_DEFAULT 0x55555550 +#define GC_FUSE_LB0_POST_OVRD_OFFSET 0x54 #define GC_FUSE_LB0_POST_OVRD_DEFAULT 0x55555550 -#define GC_FUSE_LB0_POST_PATCNT_OFFSET 0x54 +#define GC_FUSE_LB0_POST_PATCNT_OFFSET 0x58 #define GC_FUSE_LB0_POST_PATCNT_DEFAULT 0x55555554 -#define GC_FUSE_LB0_POST_WARMUP_OVRD_OFFSET 0x58 +#define GC_FUSE_LB0_POST_WARMUP_OVRD_OFFSET 0x5c #define GC_FUSE_LB0_POST_WARMUP_OVRD_DEFAULT 0x55555550 -#define GC_FUSE_LB0_POST_WARMUP_CNT_OFFSET 0x5c +#define GC_FUSE_LB0_POST_WARMUP_CNT_OFFSET 0x60 #define GC_FUSE_LB0_POST_WARMUP_CNT_DEFAULT 0x55555554 -#define GC_FUSE_LB1_POST_OVRD_OFFSET 0x60 +#define GC_FUSE_LB1_POST_OVRD_OFFSET 0x64 #define GC_FUSE_LB1_POST_OVRD_DEFAULT 0x55555550 -#define GC_FUSE_LB1_POST_PATCNT_OFFSET 0x64 +#define GC_FUSE_LB1_POST_PATCNT_OFFSET 0x68 #define GC_FUSE_LB1_POST_PATCNT_DEFAULT 0x55555554 -#define GC_FUSE_LB1_POST_WARMUP_OVRD_OFFSET 0x68 +#define GC_FUSE_LB1_POST_WARMUP_OVRD_OFFSET 0x6c #define GC_FUSE_LB1_POST_WARMUP_OVRD_DEFAULT 0x55555550 -#define GC_FUSE_LB1_POST_WARMUP_CNT_OFFSET 0x6c +#define GC_FUSE_LB1_POST_WARMUP_CNT_OFFSET 0x70 #define GC_FUSE_LB1_POST_WARMUP_CNT_DEFAULT 0x55555554 -#define GC_FUSE_LB2_POST_OVRD_OFFSET 0x70 +#define GC_FUSE_LB2_POST_OVRD_OFFSET 0x74 #define GC_FUSE_LB2_POST_OVRD_DEFAULT 0x55555550 -#define GC_FUSE_LB2_POST_PATCNT_OFFSET 0x74 +#define GC_FUSE_LB2_POST_PATCNT_OFFSET 0x78 #define GC_FUSE_LB2_POST_PATCNT_DEFAULT 0x55555554 -#define GC_FUSE_LB2_POST_WARMUP_OVRD_OFFSET 0x78 +#define GC_FUSE_LB2_POST_WARMUP_OVRD_OFFSET 0x7c #define GC_FUSE_LB2_POST_WARMUP_OVRD_DEFAULT 0x55555550 -#define GC_FUSE_LB2_POST_WARMUP_CNT_OFFSET 0x7c +#define GC_FUSE_LB2_POST_WARMUP_CNT_OFFSET 0x80 #define GC_FUSE_LB2_POST_WARMUP_CNT_DEFAULT 0x55555554 -#define GC_FUSE_LB3_POST_OVRD_OFFSET 0x80 +#define GC_FUSE_LB3_POST_OVRD_OFFSET 0x84 #define GC_FUSE_LB3_POST_OVRD_DEFAULT 0x55555550 -#define GC_FUSE_LB3_POST_PATCNT_OFFSET 0x84 +#define GC_FUSE_LB3_POST_PATCNT_OFFSET 0x88 #define GC_FUSE_LB3_POST_PATCNT_DEFAULT 0x55555554 -#define GC_FUSE_LB3_POST_WARMUP_OVRD_OFFSET 0x88 +#define GC_FUSE_LB3_POST_WARMUP_OVRD_OFFSET 0x8c #define GC_FUSE_LB3_POST_WARMUP_OVRD_DEFAULT 0x55555550 -#define GC_FUSE_LB3_POST_WARMUP_CNT_OFFSET 0x8c +#define GC_FUSE_LB3_POST_WARMUP_CNT_OFFSET 0x90 #define GC_FUSE_LB3_POST_WARMUP_CNT_DEFAULT 0x55555554 -#define GC_FUSE_MBIST_POST_SEQ_OFFSET 0x90 +#define GC_FUSE_MBIST_POST_SEQ_OFFSET 0x94 #define GC_FUSE_MBIST_POST_SEQ_DEFAULT 0x54000000 -#define GC_FUSE_LBIST_POST_SEQ_OFFSET 0x94 +#define GC_FUSE_LBIST_POST_SEQ_OFFSET 0x98 #define GC_FUSE_LBIST_POST_SEQ_DEFAULT 0x55550000 -#define GC_FUSE_LBIST_VIA_TAP_DIS_OFFSET 0x98 +#define GC_FUSE_LBIST_VIA_TAP_DIS_OFFSET 0x9c #define GC_FUSE_LBIST_VIA_TAP_DIS_DEFAULT 0x55555550 -#define GC_FUSE_MBIST_VIA_TAP_DIS_OFFSET 0x9c +#define GC_FUSE_MBIST_VIA_TAP_DIS_OFFSET 0xa0 #define GC_FUSE_MBIST_VIA_TAP_DIS_DEFAULT 0x55555550 -#define GC_FUSE_TAP_DISABLE_OFFSET 0xa0 +#define GC_FUSE_TAP_DISABLE_OFFSET 0xa4 #define GC_FUSE_TAP_DISABLE_DEFAULT 0x55555550 -#define GC_FUSE_RNGBIST_AR_EN_OFFSET 0xa4 +#define GC_FUSE_RNGBIST_AR_EN_OFFSET 0xa8 #define GC_FUSE_RNGBIST_AR_EN_DEFAULT 0x55555550 -#define GC_FUSE_TESTMODE_KEYS_EN_OFFSET 0xa8 +#define GC_FUSE_TESTMODE_KEYS_EN_OFFSET 0xac #define GC_FUSE_TESTMODE_KEYS_EN_DEFAULT 0x55555550 -#define GC_FUSE_PKG_ID_OFFSET 0xac +#define GC_FUSE_PKG_ID_OFFSET 0xb0 #define GC_FUSE_PKG_ID_DEFAULT 0x55555550 -#define GC_FUSE_BIN_ID_OFFSET 0xb0 +#define GC_FUSE_BIN_ID_OFFSET 0xb4 #define GC_FUSE_BIN_ID_DEFAULT 0x55555550 -#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_OFFSET 0xb4 +#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_OFFSET 0xb8 #define GC_FUSE_RC_JTR_OSC48_CC_TRIM_DEFAULT 0x55555500 -#define GC_FUSE_RC_JTR_OSC48_CC_EN_OFFSET 0xb8 +#define GC_FUSE_RC_JTR_OSC48_CC_EN_OFFSET 0xbc #define GC_FUSE_RC_JTR_OSC48_CC_EN_DEFAULT 0x55555550 -#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_OFFSET 0xbc +#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_OFFSET 0xc0 #define GC_FUSE_RC_JTR_OSC60_CC_TRIM_DEFAULT 0x55555500 -#define GC_FUSE_RC_JTR_OSC60_CC_EN_OFFSET 0xc0 +#define GC_FUSE_RC_JTR_OSC60_CC_EN_OFFSET 0xc4 #define GC_FUSE_RC_JTR_OSC60_CC_EN_DEFAULT 0x55555550 -#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_OFFSET 0xc4 +#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_OFFSET 0xc8 #define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_DEFAULT 0x55555500 -#define GC_FUSE_RC_TIMER_OSC48_CC_EN_OFFSET 0xc8 +#define GC_FUSE_RC_TIMER_OSC48_CC_EN_OFFSET 0xcc #define GC_FUSE_RC_TIMER_OSC48_CC_EN_DEFAULT 0x55555550 -#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_OFFSET 0xcc +#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_OFFSET 0xd0 #define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_DEFAULT 0x55555540 -#define GC_FUSE_RC_TIMER_OSC48_FC_EN_OFFSET 0xd0 +#define GC_FUSE_RC_TIMER_OSC48_FC_EN_OFFSET 0xd4 #define GC_FUSE_RC_TIMER_OSC48_FC_EN_DEFAULT 0x55555550 -#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_OFFSET 0xd4 +#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_OFFSET 0xd8 #define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_DEFAULT 0x55555500 -#define GC_FUSE_RC_RTC_OSC32K_CC_EN_OFFSET 0xd8 +#define GC_FUSE_RC_RTC_OSC32K_CC_EN_OFFSET 0xdc #define GC_FUSE_RC_RTC_OSC32K_CC_EN_DEFAULT 0x55555550 -#define GC_FUSE_SEL_VREG_REG_EN_OFFSET 0xdc +#define GC_FUSE_SEL_VREG_REG_EN_OFFSET 0xe0 #define GC_FUSE_SEL_VREG_REG_EN_DEFAULT 0x55555550 -#define GC_FUSE_SEL_VREF_REG_OFFSET 0xe0 +#define GC_FUSE_SEL_VREF_REG_OFFSET 0xe4 #define GC_FUSE_SEL_VREF_REG_DEFAULT 0x55555550 -#define GC_FUSE_SEL_VREF_BATMON_EN_OFFSET 0xe4 +#define GC_FUSE_SEL_VREF_BATMON_EN_OFFSET 0xe8 #define GC_FUSE_SEL_VREF_BATMON_EN_DEFAULT 0x55555550 -#define GC_FUSE_SEL_VREF_BATMON_OFFSET 0xe8 +#define GC_FUSE_SEL_VREF_BATMON_OFFSET 0xec #define GC_FUSE_SEL_VREF_BATMON_DEFAULT 0x55555550 -#define GC_FUSE_X_OSC_LDO_CTRL_EN_OFFSET 0xec +#define GC_FUSE_X_OSC_LDO_CTRL_EN_OFFSET 0xf0 #define GC_FUSE_X_OSC_LDO_CTRL_EN_DEFAULT 0x55555550 -#define GC_FUSE_X_OSC_LDO_CTRL_OFFSET 0xf0 +#define GC_FUSE_X_OSC_LDO_CTRL_OFFSET 0xf4 #define GC_FUSE_X_OSC_LDO_CTRL_DEFAULT 0x55555550 -#define GC_FUSE_EXT_XTAL_PDB_OFFSET 0xf4 +#define GC_FUSE_EXT_XTAL_PDB_OFFSET 0xf8 #define GC_FUSE_EXT_XTAL_PDB_DEFAULT 0x55555554 -#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_OFFSET 0xf8 +#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_OFFSET 0xfc #define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_DEFAULT 0x55555550 -#define GC_FUSE_OBFUSCATION_EN_OFFSET 0xfc +#define GC_FUSE_OBFUSCATION_EN_OFFSET 0x100 #define GC_FUSE_OBFUSCATION_EN_DEFAULT 0x55555550 -#define GC_FUSE_JITTER_CLK_EN_OFFSET 0x100 +#define GC_FUSE_JITTER_CLK_EN_OFFSET 0x104 #define GC_FUSE_JITTER_CLK_EN_DEFAULT 0x55555550 -#define GC_FUSE_HIK_CREATE_LOCK_OFFSET 0x104 +#define GC_FUSE_HIK_CREATE_LOCK_OFFSET 0x108 #define GC_FUSE_HIK_CREATE_LOCK_DEFAULT 0x55555550 -#define GC_FUSE_BNK2_INTG_CHKSUM_OFFSET 0x108 +#define GC_FUSE_BNK2_INTG_CHKSUM_OFFSET 0x10c #define GC_FUSE_BNK2_INTG_CHKSUM_DEFAULT 0x55000000 -#define GC_FUSE_BNK2_INTG_LOCK_OFFSET 0x10c +#define GC_FUSE_BNK2_INTG_LOCK_OFFSET 0x110 #define GC_FUSE_BNK2_INTG_LOCK_DEFAULT 0x55555550 -#define GC_FUSE_TESTMODE_OTPW_DIS_OFFSET 0x110 +#define GC_FUSE_TESTMODE_OTPW_DIS_OFFSET 0x114 #define GC_FUSE_TESTMODE_OTPW_DIS_DEFAULT 0x55555550 -#define GC_FUSE_HKEY_WDOG_TIMER_EN_OFFSET 0x114 +#define GC_FUSE_HKEY_WDOG_TIMER_EN_OFFSET 0x118 #define GC_FUSE_HKEY_WDOG_TIMER_EN_DEFAULT 0x55555550 -#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_OFFSET 0x118 +#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_OFFSET 0x11c #define GC_FUSE_FLASH_PERSO_PAGE_LOCK_DEFAULT 0x55555550 -#define GC_FUSE_ALERT_RSP_CFG_OFFSET 0x11c +#define GC_FUSE_ALERT_RSP_CFG_OFFSET 0x120 #define GC_FUSE_ALERT_RSP_CFG_DEFAULT 0x55555500 -#define GC_FUSE_BNK3_INTG_CHKSUM_OFFSET 0x120 +#define GC_FUSE_BNK3_INTG_CHKSUM_OFFSET 0x124 #define GC_FUSE_BNK3_INTG_CHKSUM_DEFAULT 0x55000000 -#define GC_FUSE_BNK3_INTG_LOCK_OFFSET 0x124 +#define GC_FUSE_BNK3_INTG_LOCK_OFFSET 0x128 #define GC_FUSE_BNK3_INTG_LOCK_DEFAULT 0x55555550 -#define GC_FUSE_FW_DEFINED_DATA_BLK0_OFFSET 0x128 +#define GC_FUSE_FW_DEFINED_DATA_BLK0_OFFSET 0x12c #define GC_FUSE_FW_DEFINED_DATA_BLK0_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_BLK1_OFFSET 0x12c +#define GC_FUSE_FW_DEFINED_DATA_BLK1_OFFSET 0x130 #define GC_FUSE_FW_DEFINED_DATA_BLK1_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_BLK2_OFFSET 0x130 +#define GC_FUSE_FW_DEFINED_DATA_BLK2_OFFSET 0x134 #define GC_FUSE_FW_DEFINED_DATA_BLK2_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_BLK3_OFFSET 0x134 +#define GC_FUSE_FW_DEFINED_DATA_BLK3_OFFSET 0x138 #define GC_FUSE_FW_DEFINED_DATA_BLK3_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_BLK4_OFFSET 0x138 +#define GC_FUSE_FW_DEFINED_DATA_BLK4_OFFSET 0x13c #define GC_FUSE_FW_DEFINED_DATA_BLK4_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_BLK5_OFFSET 0x13c +#define GC_FUSE_FW_DEFINED_DATA_BLK5_OFFSET 0x140 #define GC_FUSE_FW_DEFINED_DATA_BLK5_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_BLK6_OFFSET 0x140 +#define GC_FUSE_FW_DEFINED_DATA_BLK6_OFFSET 0x144 #define GC_FUSE_FW_DEFINED_DATA_BLK6_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_BLK7_OFFSET 0x144 +#define GC_FUSE_FW_DEFINED_DATA_BLK7_OFFSET 0x148 #define GC_FUSE_FW_DEFINED_DATA_BLK7_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_BLK8_OFFSET 0x148 +#define GC_FUSE_FW_DEFINED_DATA_BLK8_OFFSET 0x14c #define GC_FUSE_FW_DEFINED_DATA_BLK8_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_BLK9_OFFSET 0x14c +#define GC_FUSE_FW_DEFINED_DATA_BLK9_OFFSET 0x150 #define GC_FUSE_FW_DEFINED_DATA_BLK9_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_BLK10_OFFSET 0x150 +#define GC_FUSE_FW_DEFINED_DATA_BLK10_OFFSET 0x154 #define GC_FUSE_FW_DEFINED_DATA_BLK10_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_BLK11_OFFSET 0x154 +#define GC_FUSE_FW_DEFINED_DATA_BLK11_OFFSET 0x158 #define GC_FUSE_FW_DEFINED_DATA_BLK11_DEFAULT 0x55555500 -#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x158 +#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x15c #define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x15c +#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x160 #define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_DEFAULT 0x55555500 -#define GC_FUSE_RBOX_CLK10HZ_COUNT_OFFSET 0x160 +#define GC_FUSE_RBOX_CLK10HZ_COUNT_OFFSET 0x164 #define GC_FUSE_RBOX_CLK10HZ_COUNT_DEFAULT 0x55550000 -#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_OFFSET 0x164 +#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_OFFSET 0x168 #define GC_FUSE_RBOX_SHORT_DELAY_COUNT_DEFAULT 0x55550000 -#define GC_FUSE_RBOX_LONG_DELAY_COUNT_OFFSET 0x168 +#define GC_FUSE_RBOX_LONG_DELAY_COUNT_OFFSET 0x16c #define GC_FUSE_RBOX_LONG_DELAY_COUNT_DEFAULT 0x55555500 -#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_OFFSET 0x16c +#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_OFFSET 0x170 #define GC_FUSE_RBOX_DEBOUNCE_PERIOD_DEFAULT 0x55550000 -#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_OFFSET 0x170 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_OFFSET 0x174 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_OFFSET 0x174 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_OFFSET 0x178 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_OFFSET 0x178 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_OFFSET 0x17c #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_KEY_COMBO0_VAL_OFFSET 0x17c +#define GC_FUSE_RBOX_KEY_COMBO0_VAL_OFFSET 0x180 #define GC_FUSE_RBOX_KEY_COMBO0_VAL_DEFAULT 0x55555500 -#define GC_FUSE_RBOX_KEY_COMBO1_VAL_OFFSET 0x180 +#define GC_FUSE_RBOX_KEY_COMBO1_VAL_OFFSET 0x184 #define GC_FUSE_RBOX_KEY_COMBO1_VAL_DEFAULT 0x55555500 -#define GC_FUSE_RBOX_KEY_COMBO2_VAL_OFFSET 0x184 +#define GC_FUSE_RBOX_KEY_COMBO2_VAL_OFFSET 0x188 #define GC_FUSE_RBOX_KEY_COMBO2_VAL_DEFAULT 0x55555500 -#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_OFFSET 0x188 +#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_OFFSET 0x18c #define GC_FUSE_RBOX_KEY_COMBO0_HOLD_DEFAULT 0x55555500 -#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_OFFSET 0x18c +#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_OFFSET 0x190 #define GC_FUSE_RBOX_KEY_COMBO1_HOLD_DEFAULT 0x55555500 -#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_OFFSET 0x190 +#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_OFFSET 0x194 #define GC_FUSE_RBOX_KEY_COMBO2_HOLD_DEFAULT 0x55555500 -#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_OFFSET 0x194 +#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_OFFSET 0x198 #define GC_FUSE_RBOX_BLOCK_KEY0_SEL_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_OFFSET 0x198 +#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_OFFSET 0x19c #define GC_FUSE_RBOX_BLOCK_KEY1_SEL_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_OFFSET 0x19c +#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_OFFSET 0x1a0 #define GC_FUSE_RBOX_BLOCK_KEY0_VAL_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_OFFSET 0x1a0 +#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_OFFSET 0x1a4 #define GC_FUSE_RBOX_BLOCK_KEY1_VAL_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_POL_AC_PRESENT_OFFSET 0x1a4 +#define GC_FUSE_RBOX_POL_AC_PRESENT_OFFSET 0x1a8 #define GC_FUSE_RBOX_POL_AC_PRESENT_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_POL_PWRB_IN_OFFSET 0x1a8 +#define GC_FUSE_RBOX_POL_PWRB_IN_OFFSET 0x1ac #define GC_FUSE_RBOX_POL_PWRB_IN_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_POL_PWRB_OUT_OFFSET 0x1ac +#define GC_FUSE_RBOX_POL_PWRB_OUT_OFFSET 0x1b0 #define GC_FUSE_RBOX_POL_PWRB_OUT_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_POL_KEY0_IN_OFFSET 0x1b0 +#define GC_FUSE_RBOX_POL_KEY0_IN_OFFSET 0x1b4 #define GC_FUSE_RBOX_POL_KEY0_IN_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_POL_KEY0_OUT_OFFSET 0x1b4 +#define GC_FUSE_RBOX_POL_KEY0_OUT_OFFSET 0x1b8 #define GC_FUSE_RBOX_POL_KEY0_OUT_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_POL_KEY1_IN_OFFSET 0x1b8 +#define GC_FUSE_RBOX_POL_KEY1_IN_OFFSET 0x1bc #define GC_FUSE_RBOX_POL_KEY1_IN_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_POL_KEY1_OUT_OFFSET 0x1bc +#define GC_FUSE_RBOX_POL_KEY1_OUT_OFFSET 0x1c0 #define GC_FUSE_RBOX_POL_KEY1_OUT_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_POL_EC_RST_OFFSET 0x1c0 +#define GC_FUSE_RBOX_POL_EC_RST_OFFSET 0x1c4 #define GC_FUSE_RBOX_POL_EC_RST_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_POL_BATT_DISABLE_OFFSET 0x1c4 +#define GC_FUSE_RBOX_POL_BATT_DISABLE_OFFSET 0x1c8 #define GC_FUSE_RBOX_POL_BATT_DISABLE_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_TERM_AC_PRESENT_OFFSET 0x1c8 +#define GC_FUSE_RBOX_TERM_AC_PRESENT_OFFSET 0x1cc #define GC_FUSE_RBOX_TERM_AC_PRESENT_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_TERM_ENTERING_RW_OFFSET 0x1cc +#define GC_FUSE_RBOX_TERM_ENTERING_RW_OFFSET 0x1d0 #define GC_FUSE_RBOX_TERM_ENTERING_RW_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_TERM_PWRB_IN_OFFSET 0x1d0 +#define GC_FUSE_RBOX_TERM_PWRB_IN_OFFSET 0x1d4 #define GC_FUSE_RBOX_TERM_PWRB_IN_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_TERM_PWRB_OUT_OFFSET 0x1d4 +#define GC_FUSE_RBOX_TERM_PWRB_OUT_OFFSET 0x1d8 #define GC_FUSE_RBOX_TERM_PWRB_OUT_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_TERM_KEY0_IN_OFFSET 0x1d8 +#define GC_FUSE_RBOX_TERM_KEY0_IN_OFFSET 0x1dc #define GC_FUSE_RBOX_TERM_KEY0_IN_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_TERM_KEY0_OUT_OFFSET 0x1dc +#define GC_FUSE_RBOX_TERM_KEY0_OUT_OFFSET 0x1e0 #define GC_FUSE_RBOX_TERM_KEY0_OUT_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_TERM_KEY1_IN_OFFSET 0x1e0 +#define GC_FUSE_RBOX_TERM_KEY1_IN_OFFSET 0x1e4 #define GC_FUSE_RBOX_TERM_KEY1_IN_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_TERM_KEY1_OUT_OFFSET 0x1e4 +#define GC_FUSE_RBOX_TERM_KEY1_OUT_OFFSET 0x1e8 #define GC_FUSE_RBOX_TERM_KEY1_OUT_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_OFFSET 0x1e8 +#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_OFFSET 0x1ec #define GC_FUSE_RBOX_DRIVE_PWRB_OUT_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_OFFSET 0x1ec +#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_OFFSET 0x1f0 #define GC_FUSE_RBOX_DRIVE_KEY0_OUT_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_OFFSET 0x1f0 +#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_OFFSET 0x1f4 #define GC_FUSE_RBOX_DRIVE_KEY1_OUT_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_DRIVE_EC_RST_OFFSET 0x1f4 +#define GC_FUSE_RBOX_DRIVE_EC_RST_OFFSET 0x1f8 #define GC_FUSE_RBOX_DRIVE_EC_RST_DEFAULT 0x55555554 -#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_OFFSET 0x1f8 +#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_OFFSET 0x1fc #define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_DEFAULT 0x55555554 -#define GC_FUSE_BNK4_INTG_CHKSUM_OFFSET 0x1fc +#define GC_FUSE_BNK4_INTG_CHKSUM_OFFSET 0x200 #define GC_FUSE_BNK4_INTG_CHKSUM_DEFAULT 0x55000000 -#define GC_FUSE_BNK4_INTG_LOCK_OFFSET 0x200 +#define GC_FUSE_BNK4_INTG_LOCK_OFFSET 0x204 #define GC_FUSE_BNK4_INTG_LOCK_DEFAULT 0x55555550 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_OFFSET 0x204 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_OFFSET 0x208 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_OFFSET 0x208 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_OFFSET 0x20c #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_OFFSET 0x20c +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_OFFSET 0x210 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_OFFSET 0x210 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_OFFSET 0x214 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_OFFSET 0x214 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_OFFSET 0x218 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_OFFSET 0x218 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_OFFSET 0x21c #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_OFFSET 0x21c +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_OFFSET 0x220 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_OFFSET 0x220 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_OFFSET 0x224 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_OFFSET 0x224 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_OFFSET 0x228 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_OFFSET 0x228 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_OFFSET 0x22c #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_DEFAULT 0x55555500 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_OFFSET 0x22c +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_OFFSET 0x230 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_DEFAULT 0x55555500 -#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_OFFSET 0x230 +#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_OFFSET 0x234 #define GC_FUSE_PROG_BNK0_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_OFFSET 0x234 -#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_DEFAULT 0x0 -#define GC_FUSE_PROG_DS_GRP0_OFFSET 0x238 +#define GC_FUSE_PROG_BNK0_INTG_LOCK_OFFSET 0x238 +#define GC_FUSE_PROG_BNK0_INTG_LOCK_DEFAULT 0x0 +#define GC_FUSE_PROG_DS_GRP0_OFFSET 0x23c #define GC_FUSE_PROG_DS_GRP0_DEFAULT 0x0 -#define GC_FUSE_PROG_DS_GRP1_OFFSET 0x23c +#define GC_FUSE_PROG_DS_GRP1_OFFSET 0x240 #define GC_FUSE_PROG_DS_GRP1_DEFAULT 0x0 -#define GC_FUSE_PROG_DS_GRP2_OFFSET 0x240 +#define GC_FUSE_PROG_DS_GRP2_OFFSET 0x244 #define GC_FUSE_PROG_DS_GRP2_DEFAULT 0x0 -#define GC_FUSE_PROG_DEV_ID0_OFFSET 0x244 +#define GC_FUSE_PROG_DEV_ID0_OFFSET 0x248 #define GC_FUSE_PROG_DEV_ID0_DEFAULT 0x0 -#define GC_FUSE_PROG_DEV_ID1_OFFSET 0x248 +#define GC_FUSE_PROG_DEV_ID1_OFFSET 0x24c #define GC_FUSE_PROG_DEV_ID1_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_OFFSET 0x24c +#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_OFFSET 0x250 #define GC_FUSE_PROG_BNK1_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_OFFSET 0x250 -#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_DEFAULT 0x0 -#define GC_FUSE_PROG_LB0_POST_OVRD_OFFSET 0x254 +#define GC_FUSE_PROG_BNK1_INTG_LOCK_OFFSET 0x254 +#define GC_FUSE_PROG_BNK1_INTG_LOCK_DEFAULT 0x0 +#define GC_FUSE_PROG_LB0_POST_OVRD_OFFSET 0x258 #define GC_FUSE_PROG_LB0_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_PROG_LB0_POST_PATCNT_OFFSET 0x258 +#define GC_FUSE_PROG_LB0_POST_PATCNT_OFFSET 0x25c #define GC_FUSE_PROG_LB0_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_OFFSET 0x25c +#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_OFFSET 0x260 #define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_OFFSET 0x260 +#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_OFFSET 0x264 #define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_PROG_LB1_POST_OVRD_OFFSET 0x264 +#define GC_FUSE_PROG_LB1_POST_OVRD_OFFSET 0x268 #define GC_FUSE_PROG_LB1_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_PROG_LB1_POST_PATCNT_OFFSET 0x268 +#define GC_FUSE_PROG_LB1_POST_PATCNT_OFFSET 0x26c #define GC_FUSE_PROG_LB1_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_OFFSET 0x26c +#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_OFFSET 0x270 #define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_OFFSET 0x270 +#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_OFFSET 0x274 #define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_PROG_LB2_POST_OVRD_OFFSET 0x274 +#define GC_FUSE_PROG_LB2_POST_OVRD_OFFSET 0x278 #define GC_FUSE_PROG_LB2_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_PROG_LB2_POST_PATCNT_OFFSET 0x278 +#define GC_FUSE_PROG_LB2_POST_PATCNT_OFFSET 0x27c #define GC_FUSE_PROG_LB2_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_OFFSET 0x27c +#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_OFFSET 0x280 #define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_OFFSET 0x280 +#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_OFFSET 0x284 #define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_PROG_LB3_POST_OVRD_OFFSET 0x284 +#define GC_FUSE_PROG_LB3_POST_OVRD_OFFSET 0x288 #define GC_FUSE_PROG_LB3_POST_OVRD_DEFAULT 0x0 -#define GC_FUSE_PROG_LB3_POST_PATCNT_OFFSET 0x288 +#define GC_FUSE_PROG_LB3_POST_PATCNT_OFFSET 0x28c #define GC_FUSE_PROG_LB3_POST_PATCNT_DEFAULT 0x0 -#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_OFFSET 0x28c +#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_OFFSET 0x290 #define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_DEFAULT 0x0 -#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_OFFSET 0x290 +#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_OFFSET 0x294 #define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_DEFAULT 0x0 -#define GC_FUSE_PROG_MBIST_POST_SEQ_OFFSET 0x294 +#define GC_FUSE_PROG_MBIST_POST_SEQ_OFFSET 0x298 #define GC_FUSE_PROG_MBIST_POST_SEQ_DEFAULT 0x0 -#define GC_FUSE_PROG_LBIST_POST_SEQ_OFFSET 0x298 +#define GC_FUSE_PROG_LBIST_POST_SEQ_OFFSET 0x29c #define GC_FUSE_PROG_LBIST_POST_SEQ_DEFAULT 0x0 -#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_OFFSET 0x29c +#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_OFFSET 0x2a0 #define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_DEFAULT 0x0 -#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_OFFSET 0x2a0 +#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_OFFSET 0x2a4 #define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_DEFAULT 0x0 -#define GC_FUSE_PROG_TAP_DISABLE_OFFSET 0x2a4 +#define GC_FUSE_PROG_TAP_DISABLE_OFFSET 0x2a8 #define GC_FUSE_PROG_TAP_DISABLE_DEFAULT 0x0 -#define GC_FUSE_PROG_RNGBIST_AR_EN_OFFSET 0x2a8 +#define GC_FUSE_PROG_RNGBIST_AR_EN_OFFSET 0x2ac #define GC_FUSE_PROG_RNGBIST_AR_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_TESTMODE_KEYS_EN_OFFSET 0x2ac +#define GC_FUSE_PROG_TESTMODE_KEYS_EN_OFFSET 0x2b0 #define GC_FUSE_PROG_TESTMODE_KEYS_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_PKG_ID_OFFSET 0x2b0 +#define GC_FUSE_PROG_PKG_ID_OFFSET 0x2b4 #define GC_FUSE_PROG_PKG_ID_DEFAULT 0x0 -#define GC_FUSE_PROG_BIN_ID_OFFSET 0x2b4 +#define GC_FUSE_PROG_BIN_ID_OFFSET 0x2b8 #define GC_FUSE_PROG_BIN_ID_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_OFFSET 0x2b8 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_OFFSET 0x2bc #define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_OFFSET 0x2bc +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_OFFSET 0x2c0 #define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_OFFSET 0x2c0 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_OFFSET 0x2c4 #define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_OFFSET 0x2c4 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_OFFSET 0x2c8 #define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_OFFSET 0x2c8 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_OFFSET 0x2cc #define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_OFFSET 0x2cc +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_OFFSET 0x2d0 #define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_OFFSET 0x2d0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_OFFSET 0x2d4 #define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_OFFSET 0x2d4 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_OFFSET 0x2d8 #define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_OFFSET 0x2d8 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_OFFSET 0x2dc #define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_OFFSET 0x2dc +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_OFFSET 0x2e0 #define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_SEL_VREG_REG_EN_OFFSET 0x2e0 +#define GC_FUSE_PROG_SEL_VREG_REG_EN_OFFSET 0x2e4 #define GC_FUSE_PROG_SEL_VREG_REG_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_SEL_VREF_REG_OFFSET 0x2e4 +#define GC_FUSE_PROG_SEL_VREF_REG_OFFSET 0x2e8 #define GC_FUSE_PROG_SEL_VREF_REG_DEFAULT 0x0 -#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_OFFSET 0x2e8 +#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_OFFSET 0x2ec #define GC_FUSE_PROG_SEL_VREF_BATMON_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_SEL_VREF_BATMON_OFFSET 0x2ec +#define GC_FUSE_PROG_SEL_VREF_BATMON_OFFSET 0x2f0 #define GC_FUSE_PROG_SEL_VREF_BATMON_DEFAULT 0x0 -#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_OFFSET 0x2f0 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_OFFSET 0x2f4 #define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_X_OSC_LDO_CTRL_OFFSET 0x2f4 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_OFFSET 0x2f8 #define GC_FUSE_PROG_X_OSC_LDO_CTRL_DEFAULT 0x0 -#define GC_FUSE_PROG_EXT_XTAL_PDB_OFFSET 0x2f8 +#define GC_FUSE_PROG_EXT_XTAL_PDB_OFFSET 0x2fc #define GC_FUSE_PROG_EXT_XTAL_PDB_DEFAULT 0x0 -#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_OFFSET 0x2fc +#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_OFFSET 0x300 #define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_DEFAULT 0x0 -#define GC_FUSE_PROG_OBFUSCATION_EN_OFFSET 0x300 +#define GC_FUSE_PROG_OBFUSCATION_EN_OFFSET 0x304 #define GC_FUSE_PROG_OBFUSCATION_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_JITTER_CLK_EN_OFFSET 0x304 +#define GC_FUSE_PROG_JITTER_CLK_EN_OFFSET 0x308 #define GC_FUSE_PROG_JITTER_CLK_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS0_OFFSET 0x308 +#define GC_FUSE_PROG_OBS0_OFFSET 0x30c #define GC_FUSE_PROG_OBS0_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS1_OFFSET 0x30c +#define GC_FUSE_PROG_OBS1_OFFSET 0x310 #define GC_FUSE_PROG_OBS1_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS2_OFFSET 0x310 +#define GC_FUSE_PROG_OBS2_OFFSET 0x314 #define GC_FUSE_PROG_OBS2_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS3_OFFSET 0x314 +#define GC_FUSE_PROG_OBS3_OFFSET 0x318 #define GC_FUSE_PROG_OBS3_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS4_OFFSET 0x318 +#define GC_FUSE_PROG_OBS4_OFFSET 0x31c #define GC_FUSE_PROG_OBS4_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS5_OFFSET 0x31c +#define GC_FUSE_PROG_OBS5_OFFSET 0x320 #define GC_FUSE_PROG_OBS5_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS6_OFFSET 0x320 +#define GC_FUSE_PROG_OBS6_OFFSET 0x324 #define GC_FUSE_PROG_OBS6_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS7_OFFSET 0x324 +#define GC_FUSE_PROG_OBS7_OFFSET 0x328 #define GC_FUSE_PROG_OBS7_DEFAULT 0x0 -#define GC_FUSE_PROG_HIK_CREATE_LOCK_OFFSET 0x328 +#define GC_FUSE_PROG_HIK_CREATE_LOCK_OFFSET 0x32c #define GC_FUSE_PROG_HIK_CREATE_LOCK_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_OFFSET 0x32c +#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_OFFSET 0x330 #define GC_FUSE_PROG_BNK2_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK2_INTG_LOCK_OFFSET 0x330 +#define GC_FUSE_PROG_BNK2_INTG_LOCK_OFFSET 0x334 #define GC_FUSE_PROG_BNK2_INTG_LOCK_DEFAULT 0x0 -#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_OFFSET 0x334 +#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_OFFSET 0x338 #define GC_FUSE_PROG_TESTMODE_OTPW_DIS_DEFAULT 0x0 -#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_OFFSET 0x338 +#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_OFFSET 0x33c #define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_DEFAULT 0x0 -#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_OFFSET 0x33c +#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_OFFSET 0x340 #define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_DEFAULT 0x0 -#define GC_FUSE_PROG_ALERT_RSP_CFG_OFFSET 0x340 +#define GC_FUSE_PROG_ALERT_RSP_CFG_OFFSET 0x344 #define GC_FUSE_PROG_ALERT_RSP_CFG_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_OFFSET 0x344 +#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_OFFSET 0x348 #define GC_FUSE_PROG_BNK3_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK3_INTG_LOCK_OFFSET 0x348 +#define GC_FUSE_PROG_BNK3_INTG_LOCK_OFFSET 0x34c #define GC_FUSE_PROG_BNK3_INTG_LOCK_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_OFFSET 0x34c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_OFFSET 0x350 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_OFFSET 0x350 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_OFFSET 0x354 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_OFFSET 0x354 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_OFFSET 0x358 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_OFFSET 0x358 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_OFFSET 0x35c #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_OFFSET 0x35c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_OFFSET 0x360 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_OFFSET 0x360 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_OFFSET 0x364 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_OFFSET 0x364 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_OFFSET 0x368 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_OFFSET 0x368 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_OFFSET 0x36c #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_OFFSET 0x36c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_OFFSET 0x370 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_OFFSET 0x370 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_OFFSET 0x374 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_OFFSET 0x374 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_OFFSET 0x378 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_OFFSET 0x378 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_OFFSET 0x37c #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x37c +#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_OFFSET 0x380 #define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x380 +#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_OFFSET 0x384 #define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_OFFSET 0x384 +#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_OFFSET 0x388 #define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_OFFSET 0x388 +#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_OFFSET 0x38c #define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_OFFSET 0x38c +#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_OFFSET 0x390 #define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_OFFSET 0x390 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_OFFSET 0x394 #define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_OFFSET 0x394 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_OFFSET 0x398 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_OFFSET 0x398 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_OFFSET 0x39c #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_OFFSET 0x39c +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_OFFSET 0x3a0 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_OFFSET 0x3a0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_OFFSET 0x3a4 #define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_OFFSET 0x3a4 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_OFFSET 0x3a8 #define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_OFFSET 0x3a8 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_OFFSET 0x3ac #define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_OFFSET 0x3ac +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_OFFSET 0x3b0 #define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_OFFSET 0x3b0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_OFFSET 0x3b4 #define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_OFFSET 0x3b4 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_OFFSET 0x3b8 #define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_OFFSET 0x3b8 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_OFFSET 0x3bc #define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_OFFSET 0x3bc +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_OFFSET 0x3c0 #define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_OFFSET 0x3c0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_OFFSET 0x3c4 #define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_OFFSET 0x3c4 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_OFFSET 0x3c8 #define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_OFFSET 0x3c8 +#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_OFFSET 0x3cc #define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_OFFSET 0x3cc +#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_OFFSET 0x3d0 #define GC_FUSE_PROG_RBOX_POL_PWRB_IN_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_OFFSET 0x3d0 +#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_OFFSET 0x3d4 #define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_OFFSET 0x3d4 +#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_OFFSET 0x3d8 #define GC_FUSE_PROG_RBOX_POL_KEY0_IN_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_OFFSET 0x3d8 +#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_OFFSET 0x3dc #define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_OFFSET 0x3dc +#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_OFFSET 0x3e0 #define GC_FUSE_PROG_RBOX_POL_KEY1_IN_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_OFFSET 0x3e0 +#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_OFFSET 0x3e4 #define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_EC_RST_OFFSET 0x3e4 +#define GC_FUSE_PROG_RBOX_POL_EC_RST_OFFSET 0x3e8 #define GC_FUSE_PROG_RBOX_POL_EC_RST_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_OFFSET 0x3e8 +#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_OFFSET 0x3ec #define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_OFFSET 0x3ec +#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_OFFSET 0x3f0 #define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_OFFSET 0x3f0 +#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_OFFSET 0x3f4 #define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_OFFSET 0x3f4 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_OFFSET 0x3f8 #define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_OFFSET 0x3f8 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_OFFSET 0x3fc #define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_OFFSET 0x3fc +#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_OFFSET 0x400 #define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_OFFSET 0x400 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_OFFSET 0x404 #define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_OFFSET 0x404 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_OFFSET 0x408 #define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_OFFSET 0x408 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_OFFSET 0x40c #define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_OFFSET 0x40c +#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_OFFSET 0x410 #define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_OFFSET 0x410 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_OFFSET 0x414 #define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_OFFSET 0x414 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_OFFSET 0x418 #define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_OFFSET 0x418 +#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_OFFSET 0x41c #define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_OFFSET 0x41c +#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_OFFSET 0x420 #define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_OFFSET 0x420 +#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_OFFSET 0x424 #define GC_FUSE_PROG_BNK4_INTG_CHKSUM_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK4_INTG_LOCK_OFFSET 0x424 +#define GC_FUSE_PROG_BNK4_INTG_LOCK_OFFSET 0x428 #define GC_FUSE_PROG_BNK4_INTG_LOCK_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_OFFSET 0x428 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_OFFSET 0x42c #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_OFFSET 0x42c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_OFFSET 0x430 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_OFFSET 0x430 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_OFFSET 0x434 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_OFFSET 0x434 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_OFFSET 0x438 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_OFFSET 0x438 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_OFFSET 0x43c #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_OFFSET 0x43c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_OFFSET 0x440 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_OFFSET 0x440 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_OFFSET 0x444 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_OFFSET 0x444 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_OFFSET 0x448 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_OFFSET 0x448 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_OFFSET 0x44c #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_OFFSET 0x44c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_OFFSET 0x450 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_OFFSET 0x450 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_OFFSET 0x454 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_DEFAULT 0x0 #define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_OFFSET 0x0 #define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_DEFAULT 0x7 @@ -1635,181 +1643,233 @@ #define GC_GLOBALSEC_DUSB0_REGION2_CTRL_DEFAULT 0x0 #define GC_GLOBALSEC_DUSB0_REGION3_CTRL_OFFSET 0x6c #define GC_GLOBALSEC_DUSB0_REGION3_CTRL_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_D_REGION0_BASE_ADDR_OFFSET 0x70 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_OFFSET 0x70 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_OFFSET 0x74 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_OFFSET 0x78 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_OFFSET 0x7c +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_BULKERASE_CTRL_OFFSET 0x80 +#define GC_GLOBALSEC_FLASH0_BULKERASE_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_OFFSET 0x84 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_OFFSET 0x88 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_OFFSET 0x8c +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_OFFSET 0x90 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_BULKERASE_CTRL_OFFSET 0x94 +#define GC_GLOBALSEC_FLASH1_BULKERASE_CTRL_DEFAULT 0x0 +#define GC_GLOBALSEC_CPU0_D_REGION0_BASE_ADDR_OFFSET 0x98 #define GC_GLOBALSEC_CPU0_D_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_D_REGION0_SIZE_OFFSET 0x74 +#define GC_GLOBALSEC_CPU0_D_REGION0_SIZE_OFFSET 0x9c #define GC_GLOBALSEC_CPU0_D_REGION0_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_D_REGION1_BASE_ADDR_OFFSET 0x78 +#define GC_GLOBALSEC_CPU0_D_REGION1_BASE_ADDR_OFFSET 0xa0 #define GC_GLOBALSEC_CPU0_D_REGION1_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_D_REGION1_SIZE_OFFSET 0x7c +#define GC_GLOBALSEC_CPU0_D_REGION1_SIZE_OFFSET 0xa4 #define GC_GLOBALSEC_CPU0_D_REGION1_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_D_REGION2_BASE_ADDR_OFFSET 0x80 +#define GC_GLOBALSEC_CPU0_D_REGION2_BASE_ADDR_OFFSET 0xa8 #define GC_GLOBALSEC_CPU0_D_REGION2_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_D_REGION2_SIZE_OFFSET 0x84 +#define GC_GLOBALSEC_CPU0_D_REGION2_SIZE_OFFSET 0xac #define GC_GLOBALSEC_CPU0_D_REGION2_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_D_REGION3_BASE_ADDR_OFFSET 0x88 +#define GC_GLOBALSEC_CPU0_D_REGION3_BASE_ADDR_OFFSET 0xb0 #define GC_GLOBALSEC_CPU0_D_REGION3_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_D_REGION3_SIZE_OFFSET 0x8c +#define GC_GLOBALSEC_CPU0_D_REGION3_SIZE_OFFSET 0xb4 #define GC_GLOBALSEC_CPU0_D_REGION3_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_BASE_ADDR_OFFSET 0x90 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_BASE_ADDR_OFFSET 0xb8 #define GC_GLOBALSEC_CPU0_D_DAP_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_SIZE_OFFSET 0x94 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION0_SIZE_OFFSET 0xbc #define GC_GLOBALSEC_CPU0_D_DAP_REGION0_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_BASE_ADDR_OFFSET 0x98 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_BASE_ADDR_OFFSET 0xc0 #define GC_GLOBALSEC_CPU0_D_DAP_REGION1_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_SIZE_OFFSET 0x9c +#define GC_GLOBALSEC_CPU0_D_DAP_REGION1_SIZE_OFFSET 0xc4 #define GC_GLOBALSEC_CPU0_D_DAP_REGION1_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_BASE_ADDR_OFFSET 0xa0 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_BASE_ADDR_OFFSET 0xc8 #define GC_GLOBALSEC_CPU0_D_DAP_REGION2_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_SIZE_OFFSET 0xa4 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION2_SIZE_OFFSET 0xcc #define GC_GLOBALSEC_CPU0_D_DAP_REGION2_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_BASE_ADDR_OFFSET 0xa8 +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_BASE_ADDR_OFFSET 0xd0 #define GC_GLOBALSEC_CPU0_D_DAP_REGION3_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_SIZE_OFFSET 0xac +#define GC_GLOBALSEC_CPU0_D_DAP_REGION3_SIZE_OFFSET 0xd4 #define GC_GLOBALSEC_CPU0_D_DAP_REGION3_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_I_REGION0_BASE_ADDR_OFFSET 0xb0 +#define GC_GLOBALSEC_CPU0_I_REGION0_BASE_ADDR_OFFSET 0xd8 #define GC_GLOBALSEC_CPU0_I_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_REGION0_SIZE_OFFSET 0xb4 +#define GC_GLOBALSEC_CPU0_I_REGION0_SIZE_OFFSET 0xdc #define GC_GLOBALSEC_CPU0_I_REGION0_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_I_REGION1_BASE_ADDR_OFFSET 0xb8 +#define GC_GLOBALSEC_CPU0_I_REGION1_BASE_ADDR_OFFSET 0xe0 #define GC_GLOBALSEC_CPU0_I_REGION1_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_REGION1_SIZE_OFFSET 0xbc +#define GC_GLOBALSEC_CPU0_I_REGION1_SIZE_OFFSET 0xe4 #define GC_GLOBALSEC_CPU0_I_REGION1_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_I_REGION2_BASE_ADDR_OFFSET 0xc0 +#define GC_GLOBALSEC_CPU0_I_REGION2_BASE_ADDR_OFFSET 0xe8 #define GC_GLOBALSEC_CPU0_I_REGION2_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_REGION2_SIZE_OFFSET 0xc4 +#define GC_GLOBALSEC_CPU0_I_REGION2_SIZE_OFFSET 0xec #define GC_GLOBALSEC_CPU0_I_REGION2_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_I_REGION3_BASE_ADDR_OFFSET 0xc8 +#define GC_GLOBALSEC_CPU0_I_REGION3_BASE_ADDR_OFFSET 0xf0 #define GC_GLOBALSEC_CPU0_I_REGION3_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_REGION3_SIZE_OFFSET 0xcc +#define GC_GLOBALSEC_CPU0_I_REGION3_SIZE_OFFSET 0xf4 #define GC_GLOBALSEC_CPU0_I_REGION3_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_I_REGION4_BASE_ADDR_OFFSET 0xd0 +#define GC_GLOBALSEC_CPU0_I_REGION4_BASE_ADDR_OFFSET 0xf8 #define GC_GLOBALSEC_CPU0_I_REGION4_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_REGION4_SIZE_OFFSET 0xd4 +#define GC_GLOBALSEC_CPU0_I_REGION4_SIZE_OFFSET 0xfc #define GC_GLOBALSEC_CPU0_I_REGION4_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_I_REGION5_BASE_ADDR_OFFSET 0xd8 +#define GC_GLOBALSEC_CPU0_I_REGION5_BASE_ADDR_OFFSET 0x100 #define GC_GLOBALSEC_CPU0_I_REGION5_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_REGION5_SIZE_OFFSET 0xdc +#define GC_GLOBALSEC_CPU0_I_REGION5_SIZE_OFFSET 0x104 #define GC_GLOBALSEC_CPU0_I_REGION5_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_I_REGION6_BASE_ADDR_OFFSET 0xe0 +#define GC_GLOBALSEC_CPU0_I_REGION6_BASE_ADDR_OFFSET 0x108 #define GC_GLOBALSEC_CPU0_I_REGION6_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_REGION6_SIZE_OFFSET 0xe4 +#define GC_GLOBALSEC_CPU0_I_REGION6_SIZE_OFFSET 0x10c #define GC_GLOBALSEC_CPU0_I_REGION6_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_I_REGION7_BASE_ADDR_OFFSET 0xe8 +#define GC_GLOBALSEC_CPU0_I_REGION7_BASE_ADDR_OFFSET 0x110 #define GC_GLOBALSEC_CPU0_I_REGION7_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_REGION7_SIZE_OFFSET 0xec +#define GC_GLOBALSEC_CPU0_I_REGION7_SIZE_OFFSET 0x114 #define GC_GLOBALSEC_CPU0_I_REGION7_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DDMA0_REGION0_BASE_ADDR_OFFSET 0xf0 +#define GC_GLOBALSEC_DDMA0_REGION0_BASE_ADDR_OFFSET 0x118 #define GC_GLOBALSEC_DDMA0_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DDMA0_REGION0_SIZE_OFFSET 0xf4 +#define GC_GLOBALSEC_DDMA0_REGION0_SIZE_OFFSET 0x11c #define GC_GLOBALSEC_DDMA0_REGION0_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DDMA0_REGION1_BASE_ADDR_OFFSET 0xf8 +#define GC_GLOBALSEC_DDMA0_REGION1_BASE_ADDR_OFFSET 0x120 #define GC_GLOBALSEC_DDMA0_REGION1_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DDMA0_REGION1_SIZE_OFFSET 0xfc +#define GC_GLOBALSEC_DDMA0_REGION1_SIZE_OFFSET 0x124 #define GC_GLOBALSEC_DDMA0_REGION1_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DDMA0_REGION2_BASE_ADDR_OFFSET 0x100 +#define GC_GLOBALSEC_DDMA0_REGION2_BASE_ADDR_OFFSET 0x128 #define GC_GLOBALSEC_DDMA0_REGION2_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DDMA0_REGION2_SIZE_OFFSET 0x104 +#define GC_GLOBALSEC_DDMA0_REGION2_SIZE_OFFSET 0x12c #define GC_GLOBALSEC_DDMA0_REGION2_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DDMA0_REGION3_BASE_ADDR_OFFSET 0x108 +#define GC_GLOBALSEC_DDMA0_REGION3_BASE_ADDR_OFFSET 0x130 #define GC_GLOBALSEC_DDMA0_REGION3_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DDMA0_REGION3_SIZE_OFFSET 0x10c +#define GC_GLOBALSEC_DDMA0_REGION3_SIZE_OFFSET 0x134 #define GC_GLOBALSEC_DDMA0_REGION3_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DSPS0_REGION0_BASE_ADDR_OFFSET 0x110 +#define GC_GLOBALSEC_DSPS0_REGION0_BASE_ADDR_OFFSET 0x138 #define GC_GLOBALSEC_DSPS0_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DSPS0_REGION0_SIZE_OFFSET 0x114 +#define GC_GLOBALSEC_DSPS0_REGION0_SIZE_OFFSET 0x13c #define GC_GLOBALSEC_DSPS0_REGION0_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DSPS0_REGION1_BASE_ADDR_OFFSET 0x118 +#define GC_GLOBALSEC_DSPS0_REGION1_BASE_ADDR_OFFSET 0x140 #define GC_GLOBALSEC_DSPS0_REGION1_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DSPS0_REGION1_SIZE_OFFSET 0x11c +#define GC_GLOBALSEC_DSPS0_REGION1_SIZE_OFFSET 0x144 #define GC_GLOBALSEC_DSPS0_REGION1_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DSPS0_REGION2_BASE_ADDR_OFFSET 0x120 +#define GC_GLOBALSEC_DSPS0_REGION2_BASE_ADDR_OFFSET 0x148 #define GC_GLOBALSEC_DSPS0_REGION2_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DSPS0_REGION2_SIZE_OFFSET 0x124 +#define GC_GLOBALSEC_DSPS0_REGION2_SIZE_OFFSET 0x14c #define GC_GLOBALSEC_DSPS0_REGION2_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DSPS0_REGION3_BASE_ADDR_OFFSET 0x128 +#define GC_GLOBALSEC_DSPS0_REGION3_BASE_ADDR_OFFSET 0x150 #define GC_GLOBALSEC_DSPS0_REGION3_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DSPS0_REGION3_SIZE_OFFSET 0x12c +#define GC_GLOBALSEC_DSPS0_REGION3_SIZE_OFFSET 0x154 #define GC_GLOBALSEC_DSPS0_REGION3_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DUSB0_REGION0_BASE_ADDR_OFFSET 0x130 +#define GC_GLOBALSEC_DUSB0_REGION0_BASE_ADDR_OFFSET 0x158 #define GC_GLOBALSEC_DUSB0_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DUSB0_REGION0_SIZE_OFFSET 0x134 +#define GC_GLOBALSEC_DUSB0_REGION0_SIZE_OFFSET 0x15c #define GC_GLOBALSEC_DUSB0_REGION0_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DUSB0_REGION1_BASE_ADDR_OFFSET 0x138 +#define GC_GLOBALSEC_DUSB0_REGION1_BASE_ADDR_OFFSET 0x160 #define GC_GLOBALSEC_DUSB0_REGION1_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DUSB0_REGION1_SIZE_OFFSET 0x13c +#define GC_GLOBALSEC_DUSB0_REGION1_SIZE_OFFSET 0x164 #define GC_GLOBALSEC_DUSB0_REGION1_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DUSB0_REGION2_BASE_ADDR_OFFSET 0x140 +#define GC_GLOBALSEC_DUSB0_REGION2_BASE_ADDR_OFFSET 0x168 #define GC_GLOBALSEC_DUSB0_REGION2_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DUSB0_REGION2_SIZE_OFFSET 0x144 +#define GC_GLOBALSEC_DUSB0_REGION2_SIZE_OFFSET 0x16c #define GC_GLOBALSEC_DUSB0_REGION2_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_DUSB0_REGION3_BASE_ADDR_OFFSET 0x148 +#define GC_GLOBALSEC_DUSB0_REGION3_BASE_ADDR_OFFSET 0x170 #define GC_GLOBALSEC_DUSB0_REGION3_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_DUSB0_REGION3_SIZE_OFFSET 0x14c +#define GC_GLOBALSEC_DUSB0_REGION3_SIZE_OFFSET 0x174 #define GC_GLOBALSEC_DUSB0_REGION3_SIZE_DEFAULT 0xffffffff -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_OFFSET 0x150 +#define GC_GLOBALSEC_FLASH0_REGION0_BASE_ADDR_OFFSET 0x178 +#define GC_GLOBALSEC_FLASH0_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION0_SIZE_OFFSET 0x17c +#define GC_GLOBALSEC_FLASH0_REGION0_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_FLASH0_REGION1_BASE_ADDR_OFFSET 0x180 +#define GC_GLOBALSEC_FLASH0_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION1_SIZE_OFFSET 0x184 +#define GC_GLOBALSEC_FLASH0_REGION1_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_FLASH0_REGION2_BASE_ADDR_OFFSET 0x188 +#define GC_GLOBALSEC_FLASH0_REGION2_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION2_SIZE_OFFSET 0x18c +#define GC_GLOBALSEC_FLASH0_REGION2_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_FLASH0_REGION3_BASE_ADDR_OFFSET 0x190 +#define GC_GLOBALSEC_FLASH0_REGION3_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION3_SIZE_OFFSET 0x194 +#define GC_GLOBALSEC_FLASH0_REGION3_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_FLASH1_REGION0_BASE_ADDR_OFFSET 0x198 +#define GC_GLOBALSEC_FLASH1_REGION0_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION0_SIZE_OFFSET 0x19c +#define GC_GLOBALSEC_FLASH1_REGION0_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_FLASH1_REGION1_BASE_ADDR_OFFSET 0x1a0 +#define GC_GLOBALSEC_FLASH1_REGION1_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION1_SIZE_OFFSET 0x1a4 +#define GC_GLOBALSEC_FLASH1_REGION1_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_FLASH1_REGION2_BASE_ADDR_OFFSET 0x1a8 +#define GC_GLOBALSEC_FLASH1_REGION2_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION2_SIZE_OFFSET 0x1ac +#define GC_GLOBALSEC_FLASH1_REGION2_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_FLASH1_REGION3_BASE_ADDR_OFFSET 0x1b0 +#define GC_GLOBALSEC_FLASH1_REGION3_BASE_ADDR_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION3_SIZE_OFFSET 0x1b4 +#define GC_GLOBALSEC_FLASH1_REGION3_SIZE_DEFAULT 0xffffffff +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_OFFSET 0x1b8 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_BASE_ADDR_OFFSET 0x154 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_BASE_ADDR_OFFSET 0x1bc #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_SIZE_OFFSET 0x158 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_SIZE_OFFSET 0x1c0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_SIZE_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_OFFSET 0x15c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_OFFSET 0x1c4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_BASE_ADDR_OFFSET 0x160 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_BASE_ADDR_OFFSET 0x1c8 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_SIZE_OFFSET 0x164 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_SIZE_OFFSET 0x1cc #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_SIZE_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_OFFSET 0x168 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_OFFSET 0x1d0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_BASE_ADDR_OFFSET 0x16c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_BASE_ADDR_OFFSET 0x1d4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_SIZE_OFFSET 0x170 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_SIZE_OFFSET 0x1d8 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_SIZE_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_OFFSET 0x174 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_OFFSET 0x1dc #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_BASE_ADDR_OFFSET 0x178 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_BASE_ADDR_OFFSET 0x1e0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_SIZE_OFFSET 0x17c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_SIZE_OFFSET 0x1e4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_SIZE_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_OFFSET 0x180 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_OFFSET 0x1e8 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_BASE_ADDR_OFFSET 0x184 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_BASE_ADDR_OFFSET 0x1ec #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_SIZE_OFFSET 0x188 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_SIZE_OFFSET 0x1f0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_SIZE_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_OFFSET 0x18c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_OFFSET 0x1f4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_BASE_ADDR_OFFSET 0x190 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_BASE_ADDR_OFFSET 0x1f8 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_SIZE_OFFSET 0x194 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_SIZE_OFFSET 0x1fc #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_SIZE_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_OFFSET 0x198 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_OFFSET 0x200 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_BASE_ADDR_OFFSET 0x19c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_BASE_ADDR_OFFSET 0x204 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_SIZE_OFFSET 0x1a0 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_SIZE_OFFSET 0x208 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_SIZE_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_OFFSET 0x1a4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_OFFSET 0x20c #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_BASE_ADDR_OFFSET 0x1a8 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_BASE_ADDR_OFFSET 0x210 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_BASE_ADDR_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_SIZE_OFFSET 0x1ac +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_SIZE_OFFSET 0x214 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_SIZE_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_S_PERMISSION_DECREMENT_OFFSET 0x1b0 +#define GC_GLOBALSEC_CPU0_S_PERMISSION_DECREMENT_OFFSET 0x218 #define GC_GLOBALSEC_CPU0_S_PERMISSION_DECREMENT_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_S_PERMISSION_OFFSET 0x1b4 +#define GC_GLOBALSEC_CPU0_S_PERMISSION_OFFSET 0x21c #define GC_GLOBALSEC_CPU0_S_PERMISSION_DEFAULT 0x55 -#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_DECREMENT_OFFSET 0x1b8 +#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_DECREMENT_OFFSET 0x220 #define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_DECREMENT_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_OFFSET 0x1bc +#define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_OFFSET 0x224 #define GC_GLOBALSEC_CPU0_S_DAP_PERMISSION_DEFAULT 0x55 -#define GC_GLOBALSEC_DDMA0_PERMISSION_DECREMENT_OFFSET 0x1c0 +#define GC_GLOBALSEC_DDMA0_PERMISSION_DECREMENT_OFFSET 0x228 #define GC_GLOBALSEC_DDMA0_PERMISSION_DECREMENT_DEFAULT 0x0 -#define GC_GLOBALSEC_DDMA0_PERMISSION_OFFSET 0x1c4 +#define GC_GLOBALSEC_DDMA0_PERMISSION_OFFSET 0x22c #define GC_GLOBALSEC_DDMA0_PERMISSION_DEFAULT 0x55 -#define GC_GLOBALSEC_SOFTWARE_LVL_DECREMENT_OFFSET 0x1c8 +#define GC_GLOBALSEC_SOFTWARE_LVL_DECREMENT_OFFSET 0x230 #define GC_GLOBALSEC_SOFTWARE_LVL_DECREMENT_DEFAULT 0x0 -#define GC_GLOBALSEC_SOFTWARE_LVL_OFFSET 0x1cc +#define GC_GLOBALSEC_SOFTWARE_LVL_OFFSET 0x234 #define GC_GLOBALSEC_SOFTWARE_LVL_DEFAULT 0x55 #define GC_GLOBALSEC_SB_COMP_STATUS_OFFSET 0x1000 #define GC_GLOBALSEC_SB_COMP_STATUS_DEFAULT 0x0 @@ -1833,6 +1893,8 @@ #define GC_GLOBALSEC_SIG_UNLOCK_DEFAULT 0x0 #define GC_GLOBALSEC_INT_ERR_FLAGS_OFFSET 0x1028 #define GC_GLOBALSEC_INT_ERR_FLAGS_DEFAULT 0x0 +#define GC_GLOBALSEC_ALERT_CFG_LOCK_OFFSET 0x102c +#define GC_GLOBALSEC_ALERT_CFG_LOCK_DEFAULT 0x1 #define GC_GLOBALSEC_ALERT_FW_TRIGGER_OFFSET 0x4000 #define GC_GLOBALSEC_ALERT_FW_TRIGGER_DEFAULT 0xaa #define GC_GLOBALSEC_ALERT_INTR_STS0_OFFSET 0x4004 @@ -1940,7 +2002,7 @@ #define GC_GLOBALSEC_ANTEST_SEN_LSR_OUTPUT_OFFSET 0x40d0 #define GC_GLOBALSEC_ANTEST_SEN_LSR_OUTPUT_DEFAULT 0x0 #define GC_GLOBALSEC_VERSION_OFFSET 0x40d4 -#define GC_GLOBALSEC_VERSION_DEFAULT 0x26011ff3 +#define GC_GLOBALSEC_VERSION_DEFAULT 0x59010913 #define GC_GPIO_DATAIN_OFFSET 0x0 #define GC_GPIO_DATAIN_DEFAULT 0x0 #define GC_GPIO_DOUT_OFFSET 0x4 @@ -3429,9 +3491,11 @@ #define GC_KEYMGR_HKEY_FRR6_DEFAULT 0x0 #define GC_KEYMGR_HKEY_FRR7_OFFSET 0x331c #define GC_KEYMGR_HKEY_FRR7_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_OFFSET 0x3320 +#define GC_KEYMGR_FLASH_RCV_WIPE_OFFSET 0x3320 +#define GC_KEYMGR_FLASH_RCV_WIPE_DEFAULT 0x0 +#define GC_KEYMGR_HKEY_ERR_FLAGS_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_CTRL_OFFSET 0x3324 +#define GC_KEYMGR_HKEY_ERR_CTRL_OFFSET 0x3328 #define GC_KEYMGR_HKEY_ERR_CTRL_DEFAULT 0x0 #define GC_MAU_EN_OFFSET 0x0 #define GC_MAU_EN_DEFAULT 0x3 @@ -3663,83 +3727,81 @@ #define GC_PINMUX_SPI1_SPIMISO_SEL_DEFAULT 0x0 #define GC_PINMUX_SPI1_SPIMOSI_SEL_OFFSET 0x1b4 #define GC_PINMUX_SPI1_SPIMOSI_SEL_DEFAULT 0x0 -#define GC_PINMUX_SWDP0_TRACE2_SEL_OFFSET 0x1b8 -#define GC_PINMUX_SWDP0_TRACE2_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_OFFSET 0x1bc +#define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_OFFSET 0x1b8 #define GC_PINMUX_TEMP0_TST_ADC_CLK_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_OFFSET 0x1c0 +#define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_OFFSET 0x1bc #define GC_PINMUX_TEMP0_TST_ADC_HI_SER_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_OFFSET 0x1c4 +#define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_OFFSET 0x1c0 #define GC_PINMUX_TEMP0_TST_ADC_LO_SER_SEL_DEFAULT 0x0 -#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_OFFSET 0x1c8 +#define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_OFFSET 0x1c4 #define GC_PINMUX_TEMP0_TST_ADC_VLD_SER_SEL_DEFAULT 0x0 -#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_OFFSET 0x1cc +#define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_OFFSET 0x1c8 #define GC_PINMUX_TRNG0_TRNG_RO_DIV_SEL_DEFAULT 0x0 -#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_OFFSET 0x1d0 +#define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_OFFSET 0x1cc #define GC_PINMUX_TRNG0_TRNG_RO_REF_DIV_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_CTS_SEL_OFFSET 0x1d4 +#define GC_PINMUX_UART0_CTS_SEL_OFFSET 0x1d0 #define GC_PINMUX_UART0_CTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_RTS_SEL_OFFSET 0x1d8 +#define GC_PINMUX_UART0_RTS_SEL_OFFSET 0x1d4 #define GC_PINMUX_UART0_RTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_RX_SEL_OFFSET 0x1dc +#define GC_PINMUX_UART0_RX_SEL_OFFSET 0x1d8 #define GC_PINMUX_UART0_RX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART0_TX_SEL_OFFSET 0x1e0 +#define GC_PINMUX_UART0_TX_SEL_OFFSET 0x1dc #define GC_PINMUX_UART0_TX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_CTS_SEL_OFFSET 0x1e4 +#define GC_PINMUX_UART1_CTS_SEL_OFFSET 0x1e0 #define GC_PINMUX_UART1_CTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_RTS_SEL_OFFSET 0x1e8 +#define GC_PINMUX_UART1_RTS_SEL_OFFSET 0x1e4 #define GC_PINMUX_UART1_RTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_RX_SEL_OFFSET 0x1ec +#define GC_PINMUX_UART1_RX_SEL_OFFSET 0x1e8 #define GC_PINMUX_UART1_RX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART1_TX_SEL_OFFSET 0x1f0 +#define GC_PINMUX_UART1_TX_SEL_OFFSET 0x1ec #define GC_PINMUX_UART1_TX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_CTS_SEL_OFFSET 0x1f4 +#define GC_PINMUX_UART2_CTS_SEL_OFFSET 0x1f0 #define GC_PINMUX_UART2_CTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_RTS_SEL_OFFSET 0x1f8 +#define GC_PINMUX_UART2_RTS_SEL_OFFSET 0x1f4 #define GC_PINMUX_UART2_RTS_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_RX_SEL_OFFSET 0x1fc +#define GC_PINMUX_UART2_RX_SEL_OFFSET 0x1f8 #define GC_PINMUX_UART2_RX_SEL_DEFAULT 0x0 -#define GC_PINMUX_UART2_TX_SEL_OFFSET 0x200 +#define GC_PINMUX_UART2_TX_SEL_OFFSET 0x1fc #define GC_PINMUX_UART2_TX_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x204 +#define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_OFFSET 0x200 #define GC_PINMUX_USB0_EXT_DM_PULLUP_EN_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x208 +#define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_OFFSET 0x204 #define GC_PINMUX_USB0_EXT_DP_RPU1_ENB_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x20c +#define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_OFFSET 0x208 #define GC_PINMUX_USB0_EXT_DP_RPU2_ENB_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x210 +#define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_OFFSET 0x20c #define GC_PINMUX_USB0_EXT_FS_EDGE_SEL_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x214 +#define GC_PINMUX_USB0_EXT_RX_DMI_SEL_OFFSET 0x210 #define GC_PINMUX_USB0_EXT_RX_DMI_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x218 +#define GC_PINMUX_USB0_EXT_RX_DPI_SEL_OFFSET 0x214 #define GC_PINMUX_USB0_EXT_RX_DPI_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x21c +#define GC_PINMUX_USB0_EXT_RX_RCV_SEL_OFFSET 0x218 #define GC_PINMUX_USB0_EXT_RX_RCV_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x220 +#define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_OFFSET 0x21c #define GC_PINMUX_USB0_EXT_SUSPENDB_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x224 +#define GC_PINMUX_USB0_EXT_TX_DMO_SEL_OFFSET 0x220 #define GC_PINMUX_USB0_EXT_TX_DMO_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x228 +#define GC_PINMUX_USB0_EXT_TX_DPO_SEL_OFFSET 0x224 #define GC_PINMUX_USB0_EXT_TX_DPO_SEL_DEFAULT 0x0 -#define GC_PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x22c +#define GC_PINMUX_USB0_EXT_TX_OEB_SEL_OFFSET 0x228 #define GC_PINMUX_USB0_EXT_TX_OEB_SEL_DEFAULT 0x0 -#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x230 +#define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_OFFSET 0x22c #define GC_PINMUX_VOLT0_TST_NEG_GLITCH_DET_SEL_DEFAULT 0x0 -#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET 0x234 +#define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_OFFSET 0x230 #define GC_PINMUX_VOLT0_TST_POS_GLITCH_DET_SEL_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_OFFSET 0x23c +#define GC_PINMUX_EXITEN1_OFFSET 0x238 #define GC_PINMUX_EXITEN1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_OFFSET 0x244 +#define GC_PINMUX_EXITEDGE1_OFFSET 0x240 #define GC_PINMUX_EXITEDGE1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_OFFSET 0x24c +#define GC_PINMUX_EXITINV1_OFFSET 0x248 #define GC_PINMUX_EXITINV1_DEFAULT 0x0 -#define GC_PINMUX_HOLD_OFFSET 0x250 +#define GC_PINMUX_HOLD_OFFSET 0x24c #define GC_PINMUX_HOLD_DEFAULT 0x0 #define GC_PMU_RESET_OFFSET 0x0 #define GC_PMU_RESET_DEFAULT 0x3 @@ -3813,37 +3875,37 @@ #define GC_PMU_RST1_OFFSET 0x88 #define GC_PMU_RST1_DEFAULT 0x0 #define GC_PMU_PWRDN_SCRATCH0_OFFSET 0x8c -#define GC_PMU_PWRDN_SCRATCH0_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH0_DEFAULT 0x782cb40d #define GC_PMU_PWRDN_SCRATCH1_OFFSET 0x90 -#define GC_PMU_PWRDN_SCRATCH1_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH1_DEFAULT 0x16e754df #define GC_PMU_PWRDN_SCRATCH2_OFFSET 0x94 -#define GC_PMU_PWRDN_SCRATCH2_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH2_DEFAULT 0x28215e3d #define GC_PMU_PWRDN_SCRATCH3_OFFSET 0x98 -#define GC_PMU_PWRDN_SCRATCH3_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH3_DEFAULT 0x63f5b1c3 #define GC_PMU_PWRDN_SCRATCH4_OFFSET 0x9c -#define GC_PMU_PWRDN_SCRATCH4_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH4_DEFAULT 0x79616de3 #define GC_PMU_PWRDN_SCRATCH5_OFFSET 0xa0 -#define GC_PMU_PWRDN_SCRATCH5_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH5_DEFAULT 0x6fcfdb2f #define GC_PMU_PWRDN_SCRATCH6_OFFSET 0xa4 -#define GC_PMU_PWRDN_SCRATCH6_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH6_DEFAULT 0x9c29ca51 #define GC_PMU_PWRDN_SCRATCH7_OFFSET 0xa8 -#define GC_PMU_PWRDN_SCRATCH7_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH7_DEFAULT 0x54705f86 #define GC_PMU_PWRDN_SCRATCH8_OFFSET 0xac -#define GC_PMU_PWRDN_SCRATCH8_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH8_DEFAULT 0x18dc796a #define GC_PMU_PWRDN_SCRATCH9_OFFSET 0xb0 -#define GC_PMU_PWRDN_SCRATCH9_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH9_DEFAULT 0x2151631d #define GC_PMU_PWRDN_SCRATCH10_OFFSET 0xb4 -#define GC_PMU_PWRDN_SCRATCH10_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH10_DEFAULT 0x55718a7a #define GC_PMU_PWRDN_SCRATCH11_OFFSET 0xb8 -#define GC_PMU_PWRDN_SCRATCH11_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH11_DEFAULT 0x30593b87 #define GC_PMU_PWRDN_SCRATCH12_OFFSET 0xbc -#define GC_PMU_PWRDN_SCRATCH12_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH12_DEFAULT 0x3cfac3fd #define GC_PMU_PWRDN_SCRATCH13_OFFSET 0xc0 -#define GC_PMU_PWRDN_SCRATCH13_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH13_DEFAULT 0x6f376a2 #define GC_PMU_PWRDN_SCRATCH14_OFFSET 0xc4 -#define GC_PMU_PWRDN_SCRATCH14_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH14_DEFAULT 0x2f8d2bbf #define GC_PMU_PWRDN_SCRATCH15_OFFSET 0xc8 -#define GC_PMU_PWRDN_SCRATCH15_DEFAULT 0x0 +#define GC_PMU_PWRDN_SCRATCH15_DEFAULT 0x3a92efe4 #define GC_PMU_PWRDN_SCRATCH16_OFFSET 0xcc #define GC_PMU_PWRDN_SCRATCH16_DEFAULT 0x0 #define GC_PMU_PWRDN_SCRATCH17_OFFSET 0xd0 @@ -3878,30 +3940,28 @@ #define GC_PMU_PWRDN_SCRATCH31_DEFAULT 0x0 #define GC_PMU_PWRDN_SCRATCH_LOCK_OFFSET 0x10c #define GC_PMU_PWRDN_SCRATCH_LOCK_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_OFFSET 0x110 +#define GC_PMU_PWRDN_SCRATCH_LOCK1_OFFSET 0x110 +#define GC_PMU_PWRDN_SCRATCH_LOCK1_DEFAULT 0x0 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_OFFSET 0x114 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH0_OFFSET 0x114 +#define GC_PMU_LONG_LIFE_SCRATCH0_OFFSET 0x118 #define GC_PMU_LONG_LIFE_SCRATCH0_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH1_OFFSET 0x118 +#define GC_PMU_LONG_LIFE_SCRATCH1_OFFSET 0x11c #define GC_PMU_LONG_LIFE_SCRATCH1_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH2_OFFSET 0x11c +#define GC_PMU_LONG_LIFE_SCRATCH2_OFFSET 0x120 #define GC_PMU_LONG_LIFE_SCRATCH2_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH3_OFFSET 0x120 +#define GC_PMU_LONG_LIFE_SCRATCH3_OFFSET 0x124 #define GC_PMU_LONG_LIFE_SCRATCH3_DEFAULT 0x0 -#define GC_PMU_INT_ENABLE_OFFSET 0x124 +#define GC_PMU_INT_ENABLE_OFFSET 0x128 #define GC_PMU_INT_ENABLE_DEFAULT 0x0 -#define GC_PMU_INT_STATE_OFFSET 0x128 +#define GC_PMU_INT_STATE_OFFSET 0x12c #define GC_PMU_INT_STATE_DEFAULT 0x0 -#define GC_PMU_INT_TEST_OFFSET 0x12c +#define GC_PMU_INT_TEST_OFFSET 0x130 #define GC_PMU_INT_TEST_DEFAULT 0x0 #define GC_PMU_ANTEST_TOP_CTRL_OFFSET 0x1008 #define GC_PMU_ANTEST_TOP_CTRL_DEFAULT 0x3 #define GC_PMU_ANTEST_REGDIG_OFFSET 0x1010 #define GC_PMU_ANTEST_REGDIG_DEFAULT 0x0 -#define GC_PMU_ANTEST_FUSE_OFFSET 0x1018 -#define GC_PMU_ANTEST_FUSE_DEFAULT 0x0 -#define GC_PMU_ANTEST_XO_OFFSET 0x101c -#define GC_PMU_ANTEST_XO_DEFAULT 0x0 #define GC_PMU_TESTBUS_CTRL_OFFSET 0x2000 #define GC_PMU_TESTBUS_CTRL_DEFAULT 0x0 #define GC_PMU_CHIP_ID_OFFSET 0x1fff8 @@ -4307,11 +4367,11 @@ #define GC_SWDP_HEADER_MD5SUM_OFFSET 0x28 #define GC_SWDP_HEADER_MD5SUM_DEFAULT 0x0 #define GC_SWDP_P4_LAST_SYNC_OFFSET 0x2c -#define GC_SWDP_P4_LAST_SYNC_DEFAULT 0x12019 +#define GC_SWDP_P4_LAST_SYNC_DEFAULT 0x123bb #define GC_SWDP_BUILD_DATE_OFFSET 0x30 -#define GC_SWDP_BUILD_DATE_DEFAULT 0x1337a8d +#define GC_SWDP_BUILD_DATE_DEFAULT 0x1337add #define GC_SWDP_BUILD_TIME_OFFSET 0x34 -#define GC_SWDP_BUILD_TIME_DEFAULT 0x54d3 +#define GC_SWDP_BUILD_TIME_DEFAULT 0xa2f1 #define GC_SWDP_A1_DIO8_OFFSET 0x38 #define GC_SWDP_A1_DIO8_DEFAULT 0x0 #define GC_SWDP_A1_CHANNEL_SEL_OFFSET 0x3c @@ -5090,14 +5150,16 @@ #define GC_USB_DOEPDMAB15_DEFAULT 0x0 #define GC_USB_DFIFO_OFFSET 0x20000 #define GC_VOLT_VERSION_OFFSET 0x0 -#define GC_VOLT_VERSION_DEFAULT 0x4011f6d -#define GC_VOLT_ANALOG_CONTROL_OFFSET 0x4 +#define GC_VOLT_VERSION_DEFAULT 0x50121be +#define GC_VOLT_ANALOG_POWER_DOWN_B_OFFSET 0x4 +#define GC_VOLT_ANALOG_POWER_DOWN_B_DEFAULT 0x0 +#define GC_VOLT_ANALOG_CONTROL_OFFSET 0x8 #define GC_VOLT_ANALOG_CONTROL_DEFAULT 0xb916 -#define GC_VOLT_CONFIG_OFFSET 0x8 +#define GC_VOLT_CONFIG_OFFSET 0xc #define GC_VOLT_CONFIG_DEFAULT 0x0 -#define GC_VOLT_GLITCH_DET_CTR_STATE_OFFSET 0xc +#define GC_VOLT_GLITCH_DET_CTR_STATE_OFFSET 0x10 #define GC_VOLT_GLITCH_DET_CTR_STATE_DEFAULT 0x0 -#define GC_VOLT_ILLEGAL_VALS_CTR_STATE_OFFSET 0x10 +#define GC_VOLT_ILLEGAL_VALS_CTR_STATE_OFFSET 0x14 #define GC_VOLT_ILLEGAL_VALS_CTR_STATE_DEFAULT 0x0 #define GC_WATCHDOG_WDOGLOAD_OFFSET 0x0 #define GC_WATCHDOG_WDOGLOAD_DEFAULT 0xffffffff @@ -5142,7 +5204,7 @@ #define GC_WATCHDOG_WDOGPCELLID3_OFFSET 0xffc #define GC_WATCHDOG_WDOGPCELLID3_DEFAULT 0xb1 #define GC_XO_VERSION_OFFSET 0x0 -#define GC_XO_VERSION_DEFAULT 0x15011e43 +#define GC_XO_VERSION_DEFAULT 0x160121be #define GC_XO_CFG_WR_EN_OFFSET 0x4 #define GC_XO_CFG_WR_EN_DEFAULT 0x1 #define GC_XO_CLK_JTR_CTRL_OFFSET 0x8 @@ -5398,17 +5460,15 @@ #define GC_XO_OSC_XTL_FSM_DEFAULT 0x0 #define GC_XO_OSC_XTL_FSM_CFG_OFFSET 0x1fc #define GC_XO_OSC_XTL_FSM_CFG_DEFAULT 0xd7488 -#define GC_XO_OSC_SETHOLD_OFFSET 0x200 -#define GC_XO_OSC_SETHOLD_DEFAULT 0x0 -#define GC_XO_OSC_CLRHOLD_OFFSET 0x204 -#define GC_XO_OSC_CLRHOLD_DEFAULT 0x0 -#define GC_XO_OSC_TEST_OFFSET 0x208 +#define GC_XO_OSC_TEST_OFFSET 0x200 #define GC_XO_OSC_TEST_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_OFFSET 0x20c +#define GC_XO_ANTEST_CTRL_OFFSET 0x204 +#define GC_XO_ANTEST_CTRL_DEFAULT 0x0 +#define GC_XO_DXO_INT_ENABLE_OFFSET 0x208 #define GC_XO_DXO_INT_ENABLE_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_OFFSET 0x210 +#define GC_XO_DXO_INT_STATE_OFFSET 0x20c #define GC_XO_DXO_INT_STATE_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_OFFSET 0x214 +#define GC_XO_DXO_INT_TEST_OFFSET 0x210 #define GC_XO_DXO_INT_TEST_DEFAULT 0x0 #define GC_M3_ITM_STIM0_OFFSET 0x0 #define GC_M3_ITM_STIM0_DEFAULT 0x0 @@ -5984,12 +6044,12 @@ #define GC_CRYPTO_VERSION_CHANGE_LSB 0x0 #define GC_CRYPTO_VERSION_CHANGE_MASK 0xffffff #define GC_CRYPTO_VERSION_CHANGE_SIZE 0x18 -#define GC_CRYPTO_VERSION_CHANGE_DEFAULT 0x11ed5 +#define GC_CRYPTO_VERSION_CHANGE_DEFAULT 0x122a1 #define GC_CRYPTO_VERSION_CHANGE_OFFSET 0x0 #define GC_CRYPTO_VERSION_REVISION_LSB 0x18 #define GC_CRYPTO_VERSION_REVISION_MASK 0xff000000 #define GC_CRYPTO_VERSION_REVISION_SIZE 0x8 -#define GC_CRYPTO_VERSION_REVISION_DEFAULT 0x28 +#define GC_CRYPTO_VERSION_REVISION_DEFAULT 0x29 #define GC_CRYPTO_VERSION_REVISION_OFFSET 0x0 #define GC_CRYPTO_CONTROL_RESET_LSB 0x0 #define GC_CRYPTO_CONTROL_RESET_MASK 0x1 @@ -6121,6 +6181,11 @@ #define GC_CRYPTO_INT_ENABLE_PGM_FAULT_SIZE 0x1 #define GC_CRYPTO_INT_ENABLE_PGM_FAULT_DEFAULT 0x0 #define GC_CRYPTO_INT_ENABLE_PGM_FAULT_OFFSET 0x14 +#define GC_CRYPTO_INT_ENABLE_MOD_OPERAND_OUT_OF_RANGE_LSB 0xb +#define GC_CRYPTO_INT_ENABLE_MOD_OPERAND_OUT_OF_RANGE_MASK 0x800 +#define GC_CRYPTO_INT_ENABLE_MOD_OPERAND_OUT_OF_RANGE_SIZE 0x1 +#define GC_CRYPTO_INT_ENABLE_MOD_OPERAND_OUT_OF_RANGE_DEFAULT 0x0 +#define GC_CRYPTO_INT_ENABLE_MOD_OPERAND_OUT_OF_RANGE_OFFSET 0x14 #define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_LSB 0x0 #define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_MASK 0x1 #define GC_CRYPTO_INT_STATE_HOST_CMD_RECV_SIZE 0x1 @@ -6176,6 +6241,11 @@ #define GC_CRYPTO_INT_STATE_PGM_FAULT_SIZE 0x1 #define GC_CRYPTO_INT_STATE_PGM_FAULT_DEFAULT 0x0 #define GC_CRYPTO_INT_STATE_PGM_FAULT_OFFSET 0x18 +#define GC_CRYPTO_INT_STATE_MOD_OPERAND_OUT_OF_RANGE_LSB 0xb +#define GC_CRYPTO_INT_STATE_MOD_OPERAND_OUT_OF_RANGE_MASK 0x800 +#define GC_CRYPTO_INT_STATE_MOD_OPERAND_OUT_OF_RANGE_SIZE 0x1 +#define GC_CRYPTO_INT_STATE_MOD_OPERAND_OUT_OF_RANGE_DEFAULT 0x0 +#define GC_CRYPTO_INT_STATE_MOD_OPERAND_OUT_OF_RANGE_OFFSET 0x18 #define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_LSB 0x0 #define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_MASK 0x1 #define GC_CRYPTO_INT_TEST_HOST_CMD_RECV_SIZE 0x1 @@ -6231,6 +6301,11 @@ #define GC_CRYPTO_INT_TEST_PGM_FAULT_SIZE 0x1 #define GC_CRYPTO_INT_TEST_PGM_FAULT_DEFAULT 0x0 #define GC_CRYPTO_INT_TEST_PGM_FAULT_OFFSET 0x1c +#define GC_CRYPTO_INT_TEST_MOD_OPERAND_OUT_OF_RANGE_LSB 0xb +#define GC_CRYPTO_INT_TEST_MOD_OPERAND_OUT_OF_RANGE_MASK 0x800 +#define GC_CRYPTO_INT_TEST_MOD_OPERAND_OUT_OF_RANGE_SIZE 0x1 +#define GC_CRYPTO_INT_TEST_MOD_OPERAND_OUT_OF_RANGE_DEFAULT 0x0 +#define GC_CRYPTO_INT_TEST_MOD_OPERAND_OUT_OF_RANGE_OFFSET 0x1c #define GC_CRYPTO_HOST_CMD_INSTR_LSB 0x0 #define GC_CRYPTO_HOST_CMD_INSTR_MASK 0xffffffff #define GC_CRYPTO_HOST_CMD_INSTR_SIZE 0x20 @@ -6296,31 +6371,36 @@ #define GC_CRYPTO_RAND_STALL_CTL_FREQ_SIZE 0x2 #define GC_CRYPTO_RAND_STALL_CTL_FREQ_DEFAULT 0x2 #define GC_CRYPTO_RAND_STALL_CTL_FREQ_OFFSET 0x30 +#define GC_CRYPTO_RAND256_SHIFT_EN_LSB 0x0 +#define GC_CRYPTO_RAND256_SHIFT_EN_MASK 0x1 +#define GC_CRYPTO_RAND256_SHIFT_EN_SIZE 0x1 +#define GC_CRYPTO_RAND256_SHIFT_EN_DEFAULT 0x1 +#define GC_CRYPTO_RAND256_SHIFT_EN_OFFSET 0x34 #define GC_CRYPTO_PGM_LFSR_SIG_LSB 0x0 #define GC_CRYPTO_PGM_LFSR_SIG_MASK 0xffffff #define GC_CRYPTO_PGM_LFSR_SIG_SIZE 0x18 #define GC_CRYPTO_PGM_LFSR_SIG_DEFAULT 0x0 -#define GC_CRYPTO_PGM_LFSR_SIG_OFFSET 0x40 +#define GC_CRYPTO_PGM_LFSR_SIG_OFFSET 0x44 #define GC_CRYPTO_DEBUG_BRKPT0_PC_LSB 0x0 #define GC_CRYPTO_DEBUG_BRKPT0_PC_MASK 0x3ff #define GC_CRYPTO_DEBUG_BRKPT0_PC_SIZE 0xa #define GC_CRYPTO_DEBUG_BRKPT0_PC_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT0_PC_OFFSET 0x44 +#define GC_CRYPTO_DEBUG_BRKPT0_PC_OFFSET 0x48 #define GC_CRYPTO_DEBUG_BRKPT0_EN_LSB 0x1f #define GC_CRYPTO_DEBUG_BRKPT0_EN_MASK 0x80000000 #define GC_CRYPTO_DEBUG_BRKPT0_EN_SIZE 0x1 #define GC_CRYPTO_DEBUG_BRKPT0_EN_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT0_EN_OFFSET 0x44 +#define GC_CRYPTO_DEBUG_BRKPT0_EN_OFFSET 0x48 #define GC_CRYPTO_DEBUG_BRKPT1_PC_LSB 0x0 #define GC_CRYPTO_DEBUG_BRKPT1_PC_MASK 0x3ff #define GC_CRYPTO_DEBUG_BRKPT1_PC_SIZE 0xa #define GC_CRYPTO_DEBUG_BRKPT1_PC_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT1_PC_OFFSET 0x48 +#define GC_CRYPTO_DEBUG_BRKPT1_PC_OFFSET 0x4c #define GC_CRYPTO_DEBUG_BRKPT1_EN_LSB 0x1f #define GC_CRYPTO_DEBUG_BRKPT1_EN_MASK 0x80000000 #define GC_CRYPTO_DEBUG_BRKPT1_EN_SIZE 0x1 #define GC_CRYPTO_DEBUG_BRKPT1_EN_DEFAULT 0x0 -#define GC_CRYPTO_DEBUG_BRKPT1_EN_OFFSET 0x48 +#define GC_CRYPTO_DEBUG_BRKPT1_EN_OFFSET 0x4c #define GC_DMA_VERSION_CHANGE_LSB 0x0 #define GC_DMA_VERSION_CHANGE_MASK 0xffffff #define GC_DMA_VERSION_CHANGE_SIZE 0x18 @@ -7381,1346 +7461,1366 @@ #define GC_FUSE_FPGA_MODEL_CTRL_ERASE_SIZE 0x1 #define GC_FUSE_FPGA_MODEL_CTRL_ERASE_DEFAULT 0x0 #define GC_FUSE_FPGA_MODEL_CTRL_ERASE_OFFSET 0x10 +#define GC_FUSE_ANTEST_EN_SW0_LSB 0x0 +#define GC_FUSE_ANTEST_EN_SW0_MASK 0x1 +#define GC_FUSE_ANTEST_EN_SW0_SIZE 0x1 +#define GC_FUSE_ANTEST_EN_SW0_DEFAULT 0x0 +#define GC_FUSE_ANTEST_EN_SW0_OFFSET 0x28 +#define GC_FUSE_ANTEST_EN_SW1_LSB 0x1 +#define GC_FUSE_ANTEST_EN_SW1_MASK 0x2 +#define GC_FUSE_ANTEST_EN_SW1_SIZE 0x1 +#define GC_FUSE_ANTEST_EN_SW1_DEFAULT 0x0 +#define GC_FUSE_ANTEST_EN_SW1_OFFSET 0x28 +#define GC_FUSE_ANTEST_EN_SW2_LSB 0x2 +#define GC_FUSE_ANTEST_EN_SW2_MASK 0x4 +#define GC_FUSE_ANTEST_EN_SW2_SIZE 0x1 +#define GC_FUSE_ANTEST_EN_SW2_DEFAULT 0x0 +#define GC_FUSE_ANTEST_EN_SW2_OFFSET 0x28 +#define GC_FUSE_ANTEST_EN_SW3_LSB 0x3 +#define GC_FUSE_ANTEST_EN_SW3_MASK 0x8 +#define GC_FUSE_ANTEST_EN_SW3_SIZE 0x1 +#define GC_FUSE_ANTEST_EN_SW3_DEFAULT 0x0 +#define GC_FUSE_ANTEST_EN_SW3_OFFSET 0x28 #define GC_FUSE_VERSION_CHANGE_LSB 0x0 #define GC_FUSE_VERSION_CHANGE_MASK 0xffffff #define GC_FUSE_VERSION_CHANGE_SIZE 0x18 -#define GC_FUSE_VERSION_CHANGE_DEFAULT 0x11cd4 -#define GC_FUSE_VERSION_CHANGE_OFFSET 0x28 +#define GC_FUSE_VERSION_CHANGE_DEFAULT 0x12324 +#define GC_FUSE_VERSION_CHANGE_OFFSET 0x2c #define GC_FUSE_VERSION_REVISION_LSB 0x18 #define GC_FUSE_VERSION_REVISION_MASK 0xff000000 #define GC_FUSE_VERSION_REVISION_SIZE 0x8 -#define GC_FUSE_VERSION_REVISION_DEFAULT 0xf -#define GC_FUSE_VERSION_REVISION_OFFSET 0x28 +#define GC_FUSE_VERSION_REVISION_DEFAULT 0x12 +#define GC_FUSE_VERSION_REVISION_OFFSET 0x2c #define GC_FUSE_BNK0_INTG_CHKSUM_VAL_LSB 0x0 #define GC_FUSE_BNK0_INTG_CHKSUM_VAL_MASK 0xffffff #define GC_FUSE_BNK0_INTG_CHKSUM_VAL_SIZE 0x18 #define GC_FUSE_BNK0_INTG_CHKSUM_VAL_DEFAULT 0x0 -#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_OFFSET 0x2c -#define GC_FUSE_BNK0_INTG_N_WR_LOCK_VAL_LSB 0x0 -#define GC_FUSE_BNK0_INTG_N_WR_LOCK_VAL_MASK 0x7 -#define GC_FUSE_BNK0_INTG_N_WR_LOCK_VAL_SIZE 0x3 -#define GC_FUSE_BNK0_INTG_N_WR_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_BNK0_INTG_N_WR_LOCK_VAL_OFFSET 0x30 +#define GC_FUSE_BNK0_INTG_CHKSUM_VAL_OFFSET 0x30 +#define GC_FUSE_BNK0_INTG_LOCK_VAL_LSB 0x0 +#define GC_FUSE_BNK0_INTG_LOCK_VAL_MASK 0x7 +#define GC_FUSE_BNK0_INTG_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_BNK0_INTG_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK0_INTG_LOCK_VAL_OFFSET 0x34 #define GC_FUSE_DS_GRP0_VAL_LSB 0x0 #define GC_FUSE_DS_GRP0_VAL_MASK 0x1ff #define GC_FUSE_DS_GRP0_VAL_SIZE 0x9 #define GC_FUSE_DS_GRP0_VAL_DEFAULT 0x0 -#define GC_FUSE_DS_GRP0_VAL_OFFSET 0x34 +#define GC_FUSE_DS_GRP0_VAL_OFFSET 0x38 #define GC_FUSE_DS_GRP1_VAL_LSB 0x0 #define GC_FUSE_DS_GRP1_VAL_MASK 0x1ff #define GC_FUSE_DS_GRP1_VAL_SIZE 0x9 #define GC_FUSE_DS_GRP1_VAL_DEFAULT 0x0 -#define GC_FUSE_DS_GRP1_VAL_OFFSET 0x38 +#define GC_FUSE_DS_GRP1_VAL_OFFSET 0x3c #define GC_FUSE_DS_GRP2_VAL_LSB 0x0 #define GC_FUSE_DS_GRP2_VAL_MASK 0x1ff #define GC_FUSE_DS_GRP2_VAL_SIZE 0x9 #define GC_FUSE_DS_GRP2_VAL_DEFAULT 0x0 -#define GC_FUSE_DS_GRP2_VAL_OFFSET 0x3c +#define GC_FUSE_DS_GRP2_VAL_OFFSET 0x40 #define GC_FUSE_DEV_ID0_VAL_LSB 0x0 #define GC_FUSE_DEV_ID0_VAL_MASK 0xffffffff #define GC_FUSE_DEV_ID0_VAL_SIZE 0x20 #define GC_FUSE_DEV_ID0_VAL_DEFAULT 0x0 -#define GC_FUSE_DEV_ID0_VAL_OFFSET 0x40 +#define GC_FUSE_DEV_ID0_VAL_OFFSET 0x44 #define GC_FUSE_DEV_ID1_VAL_LSB 0x0 #define GC_FUSE_DEV_ID1_VAL_MASK 0xffffffff #define GC_FUSE_DEV_ID1_VAL_SIZE 0x20 #define GC_FUSE_DEV_ID1_VAL_DEFAULT 0x0 -#define GC_FUSE_DEV_ID1_VAL_OFFSET 0x44 +#define GC_FUSE_DEV_ID1_VAL_OFFSET 0x48 #define GC_FUSE_BNK1_INTG_CHKSUM_VAL_LSB 0x0 #define GC_FUSE_BNK1_INTG_CHKSUM_VAL_MASK 0xffffff #define GC_FUSE_BNK1_INTG_CHKSUM_VAL_SIZE 0x18 #define GC_FUSE_BNK1_INTG_CHKSUM_VAL_DEFAULT 0x0 -#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_OFFSET 0x48 -#define GC_FUSE_BNK1_INTG_N_WR_LOCK_VAL_LSB 0x0 -#define GC_FUSE_BNK1_INTG_N_WR_LOCK_VAL_MASK 0x7 -#define GC_FUSE_BNK1_INTG_N_WR_LOCK_VAL_SIZE 0x3 -#define GC_FUSE_BNK1_INTG_N_WR_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_BNK1_INTG_N_WR_LOCK_VAL_OFFSET 0x4c +#define GC_FUSE_BNK1_INTG_CHKSUM_VAL_OFFSET 0x4c +#define GC_FUSE_BNK1_INTG_LOCK_VAL_LSB 0x0 +#define GC_FUSE_BNK1_INTG_LOCK_VAL_MASK 0x7 +#define GC_FUSE_BNK1_INTG_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_BNK1_INTG_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_BNK1_INTG_LOCK_VAL_OFFSET 0x50 #define GC_FUSE_LB0_POST_OVRD_VAL_LSB 0x0 #define GC_FUSE_LB0_POST_OVRD_VAL_MASK 0x7 #define GC_FUSE_LB0_POST_OVRD_VAL_SIZE 0x3 #define GC_FUSE_LB0_POST_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_LB0_POST_OVRD_VAL_OFFSET 0x50 +#define GC_FUSE_LB0_POST_OVRD_VAL_OFFSET 0x54 #define GC_FUSE_LB0_POST_PATCNT_VAL_LSB 0x0 #define GC_FUSE_LB0_POST_PATCNT_VAL_MASK 0x3 #define GC_FUSE_LB0_POST_PATCNT_VAL_SIZE 0x2 #define GC_FUSE_LB0_POST_PATCNT_VAL_DEFAULT 0x0 -#define GC_FUSE_LB0_POST_PATCNT_VAL_OFFSET 0x54 +#define GC_FUSE_LB0_POST_PATCNT_VAL_OFFSET 0x58 #define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_LSB 0x0 #define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_MASK 0x7 #define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_SIZE 0x3 #define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_OFFSET 0x58 +#define GC_FUSE_LB0_POST_WARMUP_OVRD_VAL_OFFSET 0x5c #define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_LSB 0x0 #define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_MASK 0x3 #define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_SIZE 0x2 #define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_DEFAULT 0x0 -#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_OFFSET 0x5c +#define GC_FUSE_LB0_POST_WARMUP_CNT_VAL_OFFSET 0x60 #define GC_FUSE_LB1_POST_OVRD_VAL_LSB 0x0 #define GC_FUSE_LB1_POST_OVRD_VAL_MASK 0x7 #define GC_FUSE_LB1_POST_OVRD_VAL_SIZE 0x3 #define GC_FUSE_LB1_POST_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_LB1_POST_OVRD_VAL_OFFSET 0x60 +#define GC_FUSE_LB1_POST_OVRD_VAL_OFFSET 0x64 #define GC_FUSE_LB1_POST_PATCNT_VAL_LSB 0x0 #define GC_FUSE_LB1_POST_PATCNT_VAL_MASK 0x3 #define GC_FUSE_LB1_POST_PATCNT_VAL_SIZE 0x2 #define GC_FUSE_LB1_POST_PATCNT_VAL_DEFAULT 0x0 -#define GC_FUSE_LB1_POST_PATCNT_VAL_OFFSET 0x64 +#define GC_FUSE_LB1_POST_PATCNT_VAL_OFFSET 0x68 #define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_LSB 0x0 #define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_MASK 0x7 #define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_SIZE 0x3 #define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_OFFSET 0x68 +#define GC_FUSE_LB1_POST_WARMUP_OVRD_VAL_OFFSET 0x6c #define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_LSB 0x0 #define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_MASK 0x3 #define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_SIZE 0x2 #define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_DEFAULT 0x0 -#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_OFFSET 0x6c +#define GC_FUSE_LB1_POST_WARMUP_CNT_VAL_OFFSET 0x70 #define GC_FUSE_LB2_POST_OVRD_VAL_LSB 0x0 #define GC_FUSE_LB2_POST_OVRD_VAL_MASK 0x7 #define GC_FUSE_LB2_POST_OVRD_VAL_SIZE 0x3 #define GC_FUSE_LB2_POST_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_LB2_POST_OVRD_VAL_OFFSET 0x70 +#define GC_FUSE_LB2_POST_OVRD_VAL_OFFSET 0x74 #define GC_FUSE_LB2_POST_PATCNT_VAL_LSB 0x0 #define GC_FUSE_LB2_POST_PATCNT_VAL_MASK 0x3 #define GC_FUSE_LB2_POST_PATCNT_VAL_SIZE 0x2 #define GC_FUSE_LB2_POST_PATCNT_VAL_DEFAULT 0x0 -#define GC_FUSE_LB2_POST_PATCNT_VAL_OFFSET 0x74 +#define GC_FUSE_LB2_POST_PATCNT_VAL_OFFSET 0x78 #define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_LSB 0x0 #define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_MASK 0x7 #define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_SIZE 0x3 #define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_OFFSET 0x78 +#define GC_FUSE_LB2_POST_WARMUP_OVRD_VAL_OFFSET 0x7c #define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_LSB 0x0 #define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_MASK 0x3 #define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_SIZE 0x2 #define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_DEFAULT 0x0 -#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_OFFSET 0x7c +#define GC_FUSE_LB2_POST_WARMUP_CNT_VAL_OFFSET 0x80 #define GC_FUSE_LB3_POST_OVRD_VAL_LSB 0x0 #define GC_FUSE_LB3_POST_OVRD_VAL_MASK 0x7 #define GC_FUSE_LB3_POST_OVRD_VAL_SIZE 0x3 #define GC_FUSE_LB3_POST_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_LB3_POST_OVRD_VAL_OFFSET 0x80 +#define GC_FUSE_LB3_POST_OVRD_VAL_OFFSET 0x84 #define GC_FUSE_LB3_POST_PATCNT_VAL_LSB 0x0 #define GC_FUSE_LB3_POST_PATCNT_VAL_MASK 0x3 #define GC_FUSE_LB3_POST_PATCNT_VAL_SIZE 0x2 #define GC_FUSE_LB3_POST_PATCNT_VAL_DEFAULT 0x0 -#define GC_FUSE_LB3_POST_PATCNT_VAL_OFFSET 0x84 +#define GC_FUSE_LB3_POST_PATCNT_VAL_OFFSET 0x88 #define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_LSB 0x0 #define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_MASK 0x7 #define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_SIZE 0x3 #define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_OFFSET 0x88 +#define GC_FUSE_LB3_POST_WARMUP_OVRD_VAL_OFFSET 0x8c #define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_LSB 0x0 #define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_MASK 0x3 #define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_SIZE 0x2 #define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_DEFAULT 0x0 -#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_OFFSET 0x8c +#define GC_FUSE_LB3_POST_WARMUP_CNT_VAL_OFFSET 0x90 #define GC_FUSE_MBIST_POST_SEQ_VAL_LSB 0x0 #define GC_FUSE_MBIST_POST_SEQ_VAL_MASK 0x1ffffff #define GC_FUSE_MBIST_POST_SEQ_VAL_SIZE 0x19 #define GC_FUSE_MBIST_POST_SEQ_VAL_DEFAULT 0x0 -#define GC_FUSE_MBIST_POST_SEQ_VAL_OFFSET 0x90 +#define GC_FUSE_MBIST_POST_SEQ_VAL_OFFSET 0x94 #define GC_FUSE_LBIST_POST_SEQ_VAL_LSB 0x0 #define GC_FUSE_LBIST_POST_SEQ_VAL_MASK 0xffff #define GC_FUSE_LBIST_POST_SEQ_VAL_SIZE 0x10 #define GC_FUSE_LBIST_POST_SEQ_VAL_DEFAULT 0x0 -#define GC_FUSE_LBIST_POST_SEQ_VAL_OFFSET 0x94 +#define GC_FUSE_LBIST_POST_SEQ_VAL_OFFSET 0x98 #define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_LSB 0x0 #define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_MASK 0x7 #define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_SIZE 0x3 #define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_DEFAULT 0x0 -#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_OFFSET 0x98 +#define GC_FUSE_LBIST_VIA_TAP_DIS_VAL_OFFSET 0x9c #define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_LSB 0x0 #define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_MASK 0x7 #define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_SIZE 0x3 #define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_DEFAULT 0x0 -#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_OFFSET 0x9c +#define GC_FUSE_MBIST_VIA_TAP_DIS_VAL_OFFSET 0xa0 #define GC_FUSE_TAP_DISABLE_VAL_LSB 0x0 #define GC_FUSE_TAP_DISABLE_VAL_MASK 0x7 #define GC_FUSE_TAP_DISABLE_VAL_SIZE 0x3 #define GC_FUSE_TAP_DISABLE_VAL_DEFAULT 0x0 -#define GC_FUSE_TAP_DISABLE_VAL_OFFSET 0xa0 +#define GC_FUSE_TAP_DISABLE_VAL_OFFSET 0xa4 #define GC_FUSE_RNGBIST_AR_EN_VAL_LSB 0x0 #define GC_FUSE_RNGBIST_AR_EN_VAL_MASK 0x7 #define GC_FUSE_RNGBIST_AR_EN_VAL_SIZE 0x3 #define GC_FUSE_RNGBIST_AR_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_RNGBIST_AR_EN_VAL_OFFSET 0xa4 +#define GC_FUSE_RNGBIST_AR_EN_VAL_OFFSET 0xa8 #define GC_FUSE_TESTMODE_KEYS_EN_VAL_LSB 0x0 #define GC_FUSE_TESTMODE_KEYS_EN_VAL_MASK 0x7 #define GC_FUSE_TESTMODE_KEYS_EN_VAL_SIZE 0x3 #define GC_FUSE_TESTMODE_KEYS_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_TESTMODE_KEYS_EN_VAL_OFFSET 0xa8 +#define GC_FUSE_TESTMODE_KEYS_EN_VAL_OFFSET 0xac #define GC_FUSE_PKG_ID_VAL_LSB 0x0 #define GC_FUSE_PKG_ID_VAL_MASK 0x7 #define GC_FUSE_PKG_ID_VAL_SIZE 0x3 #define GC_FUSE_PKG_ID_VAL_DEFAULT 0x0 -#define GC_FUSE_PKG_ID_VAL_OFFSET 0xac +#define GC_FUSE_PKG_ID_VAL_OFFSET 0xb0 #define GC_FUSE_BIN_ID_VAL_LSB 0x0 #define GC_FUSE_BIN_ID_VAL_MASK 0x7 #define GC_FUSE_BIN_ID_VAL_SIZE 0x3 #define GC_FUSE_BIN_ID_VAL_DEFAULT 0x0 -#define GC_FUSE_BIN_ID_VAL_OFFSET 0xb0 +#define GC_FUSE_BIN_ID_VAL_OFFSET 0xb4 #define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_LSB 0x0 #define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_MASK 0xff #define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_SIZE 0x8 #define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_DEFAULT 0x0 -#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_OFFSET 0xb4 +#define GC_FUSE_RC_JTR_OSC48_CC_TRIM_VAL_OFFSET 0xb8 #define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_LSB 0x0 #define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_MASK 0x7 #define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_SIZE 0x3 #define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_OFFSET 0xb8 +#define GC_FUSE_RC_JTR_OSC48_CC_EN_VAL_OFFSET 0xbc #define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_LSB 0x0 #define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_MASK 0xff #define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_SIZE 0x8 #define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_DEFAULT 0x0 -#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_OFFSET 0xbc +#define GC_FUSE_RC_JTR_OSC60_CC_TRIM_VAL_OFFSET 0xc0 #define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_LSB 0x0 #define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_MASK 0x7 #define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_SIZE 0x3 #define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_OFFSET 0xc0 +#define GC_FUSE_RC_JTR_OSC60_CC_EN_VAL_OFFSET 0xc4 #define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_LSB 0x0 #define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_MASK 0xff #define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_SIZE 0x8 #define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_DEFAULT 0x0 -#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_OFFSET 0xc4 +#define GC_FUSE_RC_TIMER_OSC48_CC_TRIM_VAL_OFFSET 0xc8 #define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_LSB 0x0 #define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_MASK 0x7 #define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_SIZE 0x3 #define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_OFFSET 0xc8 +#define GC_FUSE_RC_TIMER_OSC48_CC_EN_VAL_OFFSET 0xcc #define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_LSB 0x0 #define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_MASK 0x1f #define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_SIZE 0x5 #define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_DEFAULT 0x0 -#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_OFFSET 0xcc +#define GC_FUSE_RC_TIMER_OSC48_FC_TRIM_VAL_OFFSET 0xd0 #define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_LSB 0x0 #define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_MASK 0x7 #define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_SIZE 0x3 #define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_OFFSET 0xd0 +#define GC_FUSE_RC_TIMER_OSC48_FC_EN_VAL_OFFSET 0xd4 #define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_VAL_LSB 0x0 #define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_VAL_MASK 0xff #define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_VAL_SIZE 0x8 #define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_VAL_DEFAULT 0x0 -#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_VAL_OFFSET 0xd4 +#define GC_FUSE_RC_RTC_OSC32K_CC_TRIM_VAL_OFFSET 0xd8 #define GC_FUSE_RC_RTC_OSC32K_CC_EN_VAL_LSB 0x0 #define GC_FUSE_RC_RTC_OSC32K_CC_EN_VAL_MASK 0x7 #define GC_FUSE_RC_RTC_OSC32K_CC_EN_VAL_SIZE 0x3 #define GC_FUSE_RC_RTC_OSC32K_CC_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_RC_RTC_OSC32K_CC_EN_VAL_OFFSET 0xd8 +#define GC_FUSE_RC_RTC_OSC32K_CC_EN_VAL_OFFSET 0xdc #define GC_FUSE_SEL_VREG_REG_EN_VAL_LSB 0x0 #define GC_FUSE_SEL_VREG_REG_EN_VAL_MASK 0x7 #define GC_FUSE_SEL_VREG_REG_EN_VAL_SIZE 0x3 #define GC_FUSE_SEL_VREG_REG_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_SEL_VREG_REG_EN_VAL_OFFSET 0xdc +#define GC_FUSE_SEL_VREG_REG_EN_VAL_OFFSET 0xe0 #define GC_FUSE_SEL_VREF_REG_VAL_LSB 0x0 #define GC_FUSE_SEL_VREF_REG_VAL_MASK 0xf #define GC_FUSE_SEL_VREF_REG_VAL_SIZE 0x4 #define GC_FUSE_SEL_VREF_REG_VAL_DEFAULT 0x0 -#define GC_FUSE_SEL_VREF_REG_VAL_OFFSET 0xe0 +#define GC_FUSE_SEL_VREF_REG_VAL_OFFSET 0xe4 #define GC_FUSE_SEL_VREF_BATMON_EN_VAL_LSB 0x0 #define GC_FUSE_SEL_VREF_BATMON_EN_VAL_MASK 0x7 #define GC_FUSE_SEL_VREF_BATMON_EN_VAL_SIZE 0x3 #define GC_FUSE_SEL_VREF_BATMON_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_OFFSET 0xe4 +#define GC_FUSE_SEL_VREF_BATMON_EN_VAL_OFFSET 0xe8 #define GC_FUSE_SEL_VREF_BATMON_VAL_LSB 0x0 #define GC_FUSE_SEL_VREF_BATMON_VAL_MASK 0x7 #define GC_FUSE_SEL_VREF_BATMON_VAL_SIZE 0x3 #define GC_FUSE_SEL_VREF_BATMON_VAL_DEFAULT 0x0 -#define GC_FUSE_SEL_VREF_BATMON_VAL_OFFSET 0xe8 +#define GC_FUSE_SEL_VREF_BATMON_VAL_OFFSET 0xec #define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_LSB 0x0 #define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_MASK 0x7 #define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_SIZE 0x3 #define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_OFFSET 0xec +#define GC_FUSE_X_OSC_LDO_CTRL_EN_VAL_OFFSET 0xf0 #define GC_FUSE_X_OSC_LDO_CTRL_VAL_LSB 0x0 #define GC_FUSE_X_OSC_LDO_CTRL_VAL_MASK 0xf #define GC_FUSE_X_OSC_LDO_CTRL_VAL_SIZE 0x4 #define GC_FUSE_X_OSC_LDO_CTRL_VAL_DEFAULT 0x0 -#define GC_FUSE_X_OSC_LDO_CTRL_VAL_OFFSET 0xf0 +#define GC_FUSE_X_OSC_LDO_CTRL_VAL_OFFSET 0xf4 #define GC_FUSE_EXT_XTAL_PDB_VAL_LSB 0x0 #define GC_FUSE_EXT_XTAL_PDB_VAL_MASK 0x3 #define GC_FUSE_EXT_XTAL_PDB_VAL_SIZE 0x2 #define GC_FUSE_EXT_XTAL_PDB_VAL_DEFAULT 0x0 -#define GC_FUSE_EXT_XTAL_PDB_VAL_OFFSET 0xf4 +#define GC_FUSE_EXT_XTAL_PDB_VAL_OFFSET 0xf8 #define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_LSB 0x0 #define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_MASK 0x7 #define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_SIZE 0x3 #define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_DEFAULT 0x0 -#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_OFFSET 0xf8 +#define GC_FUSE_DIS_EXT_XTAL_CLK_TREE_VAL_OFFSET 0xfc #define GC_FUSE_OBFUSCATION_EN_VAL_LSB 0x0 #define GC_FUSE_OBFUSCATION_EN_VAL_MASK 0x7 #define GC_FUSE_OBFUSCATION_EN_VAL_SIZE 0x3 #define GC_FUSE_OBFUSCATION_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_OBFUSCATION_EN_VAL_OFFSET 0xfc +#define GC_FUSE_OBFUSCATION_EN_VAL_OFFSET 0x100 #define GC_FUSE_JITTER_CLK_EN_VAL_LSB 0x0 #define GC_FUSE_JITTER_CLK_EN_VAL_MASK 0x7 #define GC_FUSE_JITTER_CLK_EN_VAL_SIZE 0x3 #define GC_FUSE_JITTER_CLK_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_JITTER_CLK_EN_VAL_OFFSET 0x100 +#define GC_FUSE_JITTER_CLK_EN_VAL_OFFSET 0x104 #define GC_FUSE_HIK_CREATE_LOCK_VAL_LSB 0x0 #define GC_FUSE_HIK_CREATE_LOCK_VAL_MASK 0x7 #define GC_FUSE_HIK_CREATE_LOCK_VAL_SIZE 0x3 #define GC_FUSE_HIK_CREATE_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_HIK_CREATE_LOCK_VAL_OFFSET 0x104 +#define GC_FUSE_HIK_CREATE_LOCK_VAL_OFFSET 0x108 #define GC_FUSE_BNK2_INTG_CHKSUM_VAL_LSB 0x0 #define GC_FUSE_BNK2_INTG_CHKSUM_VAL_MASK 0xffffff #define GC_FUSE_BNK2_INTG_CHKSUM_VAL_SIZE 0x18 #define GC_FUSE_BNK2_INTG_CHKSUM_VAL_DEFAULT 0x0 -#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_OFFSET 0x108 +#define GC_FUSE_BNK2_INTG_CHKSUM_VAL_OFFSET 0x10c #define GC_FUSE_BNK2_INTG_LOCK_VAL_LSB 0x0 #define GC_FUSE_BNK2_INTG_LOCK_VAL_MASK 0x7 #define GC_FUSE_BNK2_INTG_LOCK_VAL_SIZE 0x3 #define GC_FUSE_BNK2_INTG_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_BNK2_INTG_LOCK_VAL_OFFSET 0x10c +#define GC_FUSE_BNK2_INTG_LOCK_VAL_OFFSET 0x110 #define GC_FUSE_TESTMODE_OTPW_DIS_VAL_LSB 0x0 #define GC_FUSE_TESTMODE_OTPW_DIS_VAL_MASK 0x7 #define GC_FUSE_TESTMODE_OTPW_DIS_VAL_SIZE 0x3 #define GC_FUSE_TESTMODE_OTPW_DIS_VAL_DEFAULT 0x0 -#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_OFFSET 0x110 +#define GC_FUSE_TESTMODE_OTPW_DIS_VAL_OFFSET 0x114 #define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_LSB 0x0 #define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_MASK 0x7 #define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_SIZE 0x3 #define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_OFFSET 0x114 +#define GC_FUSE_HKEY_WDOG_TIMER_EN_VAL_OFFSET 0x118 #define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_LSB 0x0 #define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_MASK 0x7 #define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_SIZE 0x3 #define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_OFFSET 0x118 +#define GC_FUSE_FLASH_PERSO_PAGE_LOCK_VAL_OFFSET 0x11c #define GC_FUSE_ALERT_RSP_CFG_VAL_LSB 0x0 #define GC_FUSE_ALERT_RSP_CFG_VAL_MASK 0xff #define GC_FUSE_ALERT_RSP_CFG_VAL_SIZE 0x8 #define GC_FUSE_ALERT_RSP_CFG_VAL_DEFAULT 0x0 -#define GC_FUSE_ALERT_RSP_CFG_VAL_OFFSET 0x11c +#define GC_FUSE_ALERT_RSP_CFG_VAL_OFFSET 0x120 #define GC_FUSE_BNK3_INTG_CHKSUM_VAL_LSB 0x0 #define GC_FUSE_BNK3_INTG_CHKSUM_VAL_MASK 0xffffff #define GC_FUSE_BNK3_INTG_CHKSUM_VAL_SIZE 0x18 #define GC_FUSE_BNK3_INTG_CHKSUM_VAL_DEFAULT 0x0 -#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_OFFSET 0x120 +#define GC_FUSE_BNK3_INTG_CHKSUM_VAL_OFFSET 0x124 #define GC_FUSE_BNK3_INTG_LOCK_VAL_LSB 0x0 #define GC_FUSE_BNK3_INTG_LOCK_VAL_MASK 0x7 #define GC_FUSE_BNK3_INTG_LOCK_VAL_SIZE 0x3 #define GC_FUSE_BNK3_INTG_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_BNK3_INTG_LOCK_VAL_OFFSET 0x124 +#define GC_FUSE_BNK3_INTG_LOCK_VAL_OFFSET 0x128 #define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_OFFSET 0x128 +#define GC_FUSE_FW_DEFINED_DATA_BLK0_VAL_OFFSET 0x12c #define GC_FUSE_FW_DEFINED_DATA_BLK1_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK1_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK1_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK1_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK1_VAL_OFFSET 0x12c +#define GC_FUSE_FW_DEFINED_DATA_BLK1_VAL_OFFSET 0x130 #define GC_FUSE_FW_DEFINED_DATA_BLK2_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK2_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK2_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK2_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK2_VAL_OFFSET 0x130 +#define GC_FUSE_FW_DEFINED_DATA_BLK2_VAL_OFFSET 0x134 #define GC_FUSE_FW_DEFINED_DATA_BLK3_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK3_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK3_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK3_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK3_VAL_OFFSET 0x134 +#define GC_FUSE_FW_DEFINED_DATA_BLK3_VAL_OFFSET 0x138 #define GC_FUSE_FW_DEFINED_DATA_BLK4_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK4_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK4_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK4_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK4_VAL_OFFSET 0x138 +#define GC_FUSE_FW_DEFINED_DATA_BLK4_VAL_OFFSET 0x13c #define GC_FUSE_FW_DEFINED_DATA_BLK5_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK5_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK5_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK5_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK5_VAL_OFFSET 0x13c +#define GC_FUSE_FW_DEFINED_DATA_BLK5_VAL_OFFSET 0x140 #define GC_FUSE_FW_DEFINED_DATA_BLK6_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK6_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK6_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK6_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK6_VAL_OFFSET 0x140 +#define GC_FUSE_FW_DEFINED_DATA_BLK6_VAL_OFFSET 0x144 #define GC_FUSE_FW_DEFINED_DATA_BLK7_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK7_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK7_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK7_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK7_VAL_OFFSET 0x144 +#define GC_FUSE_FW_DEFINED_DATA_BLK7_VAL_OFFSET 0x148 #define GC_FUSE_FW_DEFINED_DATA_BLK8_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK8_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK8_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK8_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK8_VAL_OFFSET 0x148 +#define GC_FUSE_FW_DEFINED_DATA_BLK8_VAL_OFFSET 0x14c #define GC_FUSE_FW_DEFINED_DATA_BLK9_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK9_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK9_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK9_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK9_VAL_OFFSET 0x14c +#define GC_FUSE_FW_DEFINED_DATA_BLK9_VAL_OFFSET 0x150 #define GC_FUSE_FW_DEFINED_DATA_BLK10_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK10_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK10_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK10_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK10_VAL_OFFSET 0x150 +#define GC_FUSE_FW_DEFINED_DATA_BLK10_VAL_OFFSET 0x154 #define GC_FUSE_FW_DEFINED_DATA_BLK11_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_BLK11_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_BLK11_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_BLK11_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_BLK11_VAL_OFFSET 0x154 +#define GC_FUSE_FW_DEFINED_DATA_BLK11_VAL_OFFSET 0x158 #define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_LSB 0x0 #define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_MASK 0x1 #define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_SIZE 0x1 #define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_OFFSET 0x158 +#define GC_FUSE_RBOX_MODE_DBG_OVRD_DIS_VAL_OFFSET 0x15c #define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_LSB 0x0 #define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_MASK 0x7f #define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_SIZE 0x7 #define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_OFFSET 0x15c +#define GC_FUSE_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_OFFSET 0x160 #define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_LSB 0x0 #define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_MASK 0xffff #define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_SIZE 0x10 #define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_OFFSET 0x160 +#define GC_FUSE_RBOX_CLK10HZ_COUNT_VAL_OFFSET 0x164 #define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_LSB 0x0 #define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_MASK 0xffff #define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_SIZE 0x10 #define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_OFFSET 0x164 +#define GC_FUSE_RBOX_SHORT_DELAY_COUNT_VAL_OFFSET 0x168 #define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_LSB 0x0 #define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_MASK 0xff #define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_SIZE 0x8 #define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_OFFSET 0x168 +#define GC_FUSE_RBOX_LONG_DELAY_COUNT_VAL_OFFSET 0x16c #define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_LSB 0x0 #define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_MASK 0xffff #define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_SIZE 0x10 #define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_OFFSET 0x16c +#define GC_FUSE_RBOX_DEBOUNCE_PERIOD_VAL_OFFSET 0x170 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_LSB 0x0 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_MASK 0x1 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_SIZE 0x1 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_OFFSET 0x170 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_OFFSET 0x174 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_LSB 0x0 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_MASK 0x1 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_SIZE 0x1 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_OFFSET 0x174 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_OFFSET 0x178 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_LSB 0x0 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_MASK 0x1 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_SIZE 0x1 #define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_OFFSET 0x178 +#define GC_FUSE_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_OFFSET 0x17c #define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_LSB 0x0 #define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_MASK 0xff #define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_SIZE 0x8 #define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_OFFSET 0x17c +#define GC_FUSE_RBOX_KEY_COMBO0_VAL_VAL_OFFSET 0x180 #define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_LSB 0x0 #define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_MASK 0xff #define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_SIZE 0x8 #define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_OFFSET 0x180 +#define GC_FUSE_RBOX_KEY_COMBO1_VAL_VAL_OFFSET 0x184 #define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_LSB 0x0 #define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_MASK 0xff #define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_SIZE 0x8 #define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_OFFSET 0x184 +#define GC_FUSE_RBOX_KEY_COMBO2_VAL_VAL_OFFSET 0x188 #define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_LSB 0x0 #define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_MASK 0xff #define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_SIZE 0x8 #define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_OFFSET 0x188 +#define GC_FUSE_RBOX_KEY_COMBO0_HOLD_VAL_OFFSET 0x18c #define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_LSB 0x0 #define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_MASK 0xff #define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_SIZE 0x8 #define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_OFFSET 0x18c +#define GC_FUSE_RBOX_KEY_COMBO1_HOLD_VAL_OFFSET 0x190 #define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_LSB 0x0 #define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_MASK 0xff #define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_SIZE 0x8 #define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_OFFSET 0x190 +#define GC_FUSE_RBOX_KEY_COMBO2_HOLD_VAL_OFFSET 0x194 #define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_LSB 0x0 #define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_MASK 0x1 #define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_SIZE 0x1 #define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_OFFSET 0x194 +#define GC_FUSE_RBOX_BLOCK_KEY0_SEL_VAL_OFFSET 0x198 #define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_LSB 0x0 #define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_MASK 0x1 #define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_SIZE 0x1 #define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_OFFSET 0x198 +#define GC_FUSE_RBOX_BLOCK_KEY1_SEL_VAL_OFFSET 0x19c #define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_LSB 0x0 #define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_MASK 0x1 #define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_SIZE 0x1 #define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_OFFSET 0x19c +#define GC_FUSE_RBOX_BLOCK_KEY0_VAL_VAL_OFFSET 0x1a0 #define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_LSB 0x0 #define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_MASK 0x1 #define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_SIZE 0x1 #define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_OFFSET 0x1a0 +#define GC_FUSE_RBOX_BLOCK_KEY1_VAL_VAL_OFFSET 0x1a4 #define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_LSB 0x0 #define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_MASK 0x1 #define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_SIZE 0x1 #define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_OFFSET 0x1a4 +#define GC_FUSE_RBOX_POL_AC_PRESENT_VAL_OFFSET 0x1a8 #define GC_FUSE_RBOX_POL_PWRB_IN_VAL_LSB 0x0 #define GC_FUSE_RBOX_POL_PWRB_IN_VAL_MASK 0x1 #define GC_FUSE_RBOX_POL_PWRB_IN_VAL_SIZE 0x1 #define GC_FUSE_RBOX_POL_PWRB_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_OFFSET 0x1a8 +#define GC_FUSE_RBOX_POL_PWRB_IN_VAL_OFFSET 0x1ac #define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_LSB 0x0 #define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_MASK 0x1 #define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_SIZE 0x1 #define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_OFFSET 0x1ac +#define GC_FUSE_RBOX_POL_PWRB_OUT_VAL_OFFSET 0x1b0 #define GC_FUSE_RBOX_POL_KEY0_IN_VAL_LSB 0x0 #define GC_FUSE_RBOX_POL_KEY0_IN_VAL_MASK 0x1 #define GC_FUSE_RBOX_POL_KEY0_IN_VAL_SIZE 0x1 #define GC_FUSE_RBOX_POL_KEY0_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_OFFSET 0x1b0 +#define GC_FUSE_RBOX_POL_KEY0_IN_VAL_OFFSET 0x1b4 #define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_LSB 0x0 #define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_MASK 0x1 #define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_SIZE 0x1 #define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_OFFSET 0x1b4 +#define GC_FUSE_RBOX_POL_KEY0_OUT_VAL_OFFSET 0x1b8 #define GC_FUSE_RBOX_POL_KEY1_IN_VAL_LSB 0x0 #define GC_FUSE_RBOX_POL_KEY1_IN_VAL_MASK 0x1 #define GC_FUSE_RBOX_POL_KEY1_IN_VAL_SIZE 0x1 #define GC_FUSE_RBOX_POL_KEY1_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_OFFSET 0x1b8 +#define GC_FUSE_RBOX_POL_KEY1_IN_VAL_OFFSET 0x1bc #define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_LSB 0x0 #define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_MASK 0x1 #define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_SIZE 0x1 #define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_OFFSET 0x1bc +#define GC_FUSE_RBOX_POL_KEY1_OUT_VAL_OFFSET 0x1c0 #define GC_FUSE_RBOX_POL_EC_RST_VAL_LSB 0x0 #define GC_FUSE_RBOX_POL_EC_RST_VAL_MASK 0x1 #define GC_FUSE_RBOX_POL_EC_RST_VAL_SIZE 0x1 #define GC_FUSE_RBOX_POL_EC_RST_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_EC_RST_VAL_OFFSET 0x1c0 +#define GC_FUSE_RBOX_POL_EC_RST_VAL_OFFSET 0x1c4 #define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_LSB 0x0 #define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_MASK 0x1 #define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_SIZE 0x1 #define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_OFFSET 0x1c4 +#define GC_FUSE_RBOX_POL_BATT_DISABLE_VAL_OFFSET 0x1c8 #define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_LSB 0x0 #define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_MASK 0x3 #define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_SIZE 0x2 #define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_OFFSET 0x1c8 +#define GC_FUSE_RBOX_TERM_AC_PRESENT_VAL_OFFSET 0x1cc #define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_LSB 0x0 #define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_MASK 0x3 #define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_SIZE 0x2 #define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_OFFSET 0x1cc +#define GC_FUSE_RBOX_TERM_ENTERING_RW_VAL_OFFSET 0x1d0 #define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_LSB 0x0 #define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_MASK 0x3 #define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_SIZE 0x2 #define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_OFFSET 0x1d0 +#define GC_FUSE_RBOX_TERM_PWRB_IN_VAL_OFFSET 0x1d4 #define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_LSB 0x0 #define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_MASK 0x3 #define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_SIZE 0x2 #define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_OFFSET 0x1d4 +#define GC_FUSE_RBOX_TERM_PWRB_OUT_VAL_OFFSET 0x1d8 #define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_LSB 0x0 #define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_MASK 0x3 #define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_SIZE 0x2 #define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_OFFSET 0x1d8 +#define GC_FUSE_RBOX_TERM_KEY0_IN_VAL_OFFSET 0x1dc #define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_LSB 0x0 #define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_MASK 0x3 #define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_SIZE 0x2 #define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_OFFSET 0x1dc +#define GC_FUSE_RBOX_TERM_KEY0_OUT_VAL_OFFSET 0x1e0 #define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_LSB 0x0 #define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_MASK 0x3 #define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_SIZE 0x2 #define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_OFFSET 0x1e0 +#define GC_FUSE_RBOX_TERM_KEY1_IN_VAL_OFFSET 0x1e4 #define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_LSB 0x0 #define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_MASK 0x3 #define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_SIZE 0x2 #define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_OFFSET 0x1e4 +#define GC_FUSE_RBOX_TERM_KEY1_OUT_VAL_OFFSET 0x1e8 #define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_LSB 0x0 #define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_MASK 0x3 #define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_SIZE 0x2 #define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_OFFSET 0x1e8 +#define GC_FUSE_RBOX_DRIVE_PWRB_OUT_VAL_OFFSET 0x1ec #define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_LSB 0x0 #define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_MASK 0x3 #define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_SIZE 0x2 #define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_OFFSET 0x1ec +#define GC_FUSE_RBOX_DRIVE_KEY0_OUT_VAL_OFFSET 0x1f0 #define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_LSB 0x0 #define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_MASK 0x3 #define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_SIZE 0x2 #define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_OFFSET 0x1f0 +#define GC_FUSE_RBOX_DRIVE_KEY1_OUT_VAL_OFFSET 0x1f4 #define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_LSB 0x0 #define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_MASK 0x3 #define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_SIZE 0x2 #define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_OFFSET 0x1f4 +#define GC_FUSE_RBOX_DRIVE_EC_RST_VAL_OFFSET 0x1f8 #define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_LSB 0x0 #define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_MASK 0x3 #define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_SIZE 0x2 #define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_DEFAULT 0x0 -#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_OFFSET 0x1f8 +#define GC_FUSE_RBOX_DRIVE_BATT_DISABLE_VAL_OFFSET 0x1fc #define GC_FUSE_BNK4_INTG_CHKSUM_VAL_LSB 0x0 #define GC_FUSE_BNK4_INTG_CHKSUM_VAL_MASK 0xffffff #define GC_FUSE_BNK4_INTG_CHKSUM_VAL_SIZE 0x18 #define GC_FUSE_BNK4_INTG_CHKSUM_VAL_DEFAULT 0x0 -#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_OFFSET 0x1fc +#define GC_FUSE_BNK4_INTG_CHKSUM_VAL_OFFSET 0x200 #define GC_FUSE_BNK4_INTG_LOCK_VAL_LSB 0x0 #define GC_FUSE_BNK4_INTG_LOCK_VAL_MASK 0x7 #define GC_FUSE_BNK4_INTG_LOCK_VAL_SIZE 0x3 #define GC_FUSE_BNK4_INTG_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_BNK4_INTG_LOCK_VAL_OFFSET 0x200 +#define GC_FUSE_BNK4_INTG_LOCK_VAL_OFFSET 0x204 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_OFFSET 0x204 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK0_VAL_OFFSET 0x208 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_OFFSET 0x208 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK1_VAL_OFFSET 0x20c #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_OFFSET 0x20c +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK2_VAL_OFFSET 0x210 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_OFFSET 0x210 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK3_VAL_OFFSET 0x214 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_OFFSET 0x214 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK4_VAL_OFFSET 0x218 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_OFFSET 0x218 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK5_VAL_OFFSET 0x21c #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_OFFSET 0x21c +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK6_VAL_OFFSET 0x220 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_VAL_OFFSET 0x220 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK7_VAL_OFFSET 0x224 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_VAL_OFFSET 0x224 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK8_VAL_OFFSET 0x228 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_VAL_MASK 0xff #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_VAL_SIZE 0x8 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_VAL_OFFSET 0x228 +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK9_VAL_OFFSET 0x22c #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_VAL_LSB 0x0 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_VAL_MASK 0x7f #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_VAL_SIZE 0x7 #define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_VAL_DEFAULT 0x0 -#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_VAL_OFFSET 0x22c +#define GC_FUSE_FW_DEFINED_DATA_EXTRA_BLK10_VAL_OFFSET 0x230 #define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_LSB 0x0 #define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_MASK 0xffffff #define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_SIZE 0x18 #define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_OFFSET 0x230 -#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_VAL_LSB 0x0 -#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_VAL_MASK 0x7 -#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_VAL_SIZE 0x3 -#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK0_INTG_N_WR_LOCK_VAL_OFFSET 0x234 +#define GC_FUSE_PROG_BNK0_INTG_CHKSUM_VAL_OFFSET 0x234 +#define GC_FUSE_PROG_BNK0_INTG_LOCK_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK0_INTG_LOCK_VAL_MASK 0x7 +#define GC_FUSE_PROG_BNK0_INTG_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_PROG_BNK0_INTG_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK0_INTG_LOCK_VAL_OFFSET 0x238 #define GC_FUSE_PROG_DS_GRP0_VAL_LSB 0x0 #define GC_FUSE_PROG_DS_GRP0_VAL_MASK 0x1ff #define GC_FUSE_PROG_DS_GRP0_VAL_SIZE 0x9 #define GC_FUSE_PROG_DS_GRP0_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_DS_GRP0_VAL_OFFSET 0x238 +#define GC_FUSE_PROG_DS_GRP0_VAL_OFFSET 0x23c #define GC_FUSE_PROG_DS_GRP1_VAL_LSB 0x0 #define GC_FUSE_PROG_DS_GRP1_VAL_MASK 0x1ff #define GC_FUSE_PROG_DS_GRP1_VAL_SIZE 0x9 #define GC_FUSE_PROG_DS_GRP1_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_DS_GRP1_VAL_OFFSET 0x23c +#define GC_FUSE_PROG_DS_GRP1_VAL_OFFSET 0x240 #define GC_FUSE_PROG_DS_GRP2_VAL_LSB 0x0 #define GC_FUSE_PROG_DS_GRP2_VAL_MASK 0x1ff #define GC_FUSE_PROG_DS_GRP2_VAL_SIZE 0x9 #define GC_FUSE_PROG_DS_GRP2_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_DS_GRP2_VAL_OFFSET 0x240 +#define GC_FUSE_PROG_DS_GRP2_VAL_OFFSET 0x244 #define GC_FUSE_PROG_DEV_ID0_VAL_LSB 0x0 #define GC_FUSE_PROG_DEV_ID0_VAL_MASK 0xffffffff #define GC_FUSE_PROG_DEV_ID0_VAL_SIZE 0x20 #define GC_FUSE_PROG_DEV_ID0_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_DEV_ID0_VAL_OFFSET 0x244 +#define GC_FUSE_PROG_DEV_ID0_VAL_OFFSET 0x248 #define GC_FUSE_PROG_DEV_ID1_VAL_LSB 0x0 #define GC_FUSE_PROG_DEV_ID1_VAL_MASK 0xffffffff #define GC_FUSE_PROG_DEV_ID1_VAL_SIZE 0x20 #define GC_FUSE_PROG_DEV_ID1_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_DEV_ID1_VAL_OFFSET 0x248 +#define GC_FUSE_PROG_DEV_ID1_VAL_OFFSET 0x24c #define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_LSB 0x0 #define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_MASK 0xffffff #define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_SIZE 0x18 #define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_OFFSET 0x24c -#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_VAL_LSB 0x0 -#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_VAL_MASK 0x7 -#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_VAL_SIZE 0x3 -#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK1_INTG_N_WR_LOCK_VAL_OFFSET 0x250 +#define GC_FUSE_PROG_BNK1_INTG_CHKSUM_VAL_OFFSET 0x250 +#define GC_FUSE_PROG_BNK1_INTG_LOCK_VAL_LSB 0x0 +#define GC_FUSE_PROG_BNK1_INTG_LOCK_VAL_MASK 0x7 +#define GC_FUSE_PROG_BNK1_INTG_LOCK_VAL_SIZE 0x3 +#define GC_FUSE_PROG_BNK1_INTG_LOCK_VAL_DEFAULT 0x0 +#define GC_FUSE_PROG_BNK1_INTG_LOCK_VAL_OFFSET 0x254 #define GC_FUSE_PROG_LB0_POST_OVRD_VAL_LSB 0x0 #define GC_FUSE_PROG_LB0_POST_OVRD_VAL_MASK 0x7 #define GC_FUSE_PROG_LB0_POST_OVRD_VAL_SIZE 0x3 #define GC_FUSE_PROG_LB0_POST_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_OFFSET 0x254 +#define GC_FUSE_PROG_LB0_POST_OVRD_VAL_OFFSET 0x258 #define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_LSB 0x0 #define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_MASK 0x3 #define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_SIZE 0x2 #define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_OFFSET 0x258 +#define GC_FUSE_PROG_LB0_POST_PATCNT_VAL_OFFSET 0x25c #define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_LSB 0x0 #define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_MASK 0x7 #define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_SIZE 0x3 #define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_OFFSET 0x25c +#define GC_FUSE_PROG_LB0_POST_WARMUP_OVRD_VAL_OFFSET 0x260 #define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_LSB 0x0 #define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_MASK 0x3 #define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_SIZE 0x2 #define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_OFFSET 0x260 +#define GC_FUSE_PROG_LB0_POST_WARMUP_CNT_VAL_OFFSET 0x264 #define GC_FUSE_PROG_LB1_POST_OVRD_VAL_LSB 0x0 #define GC_FUSE_PROG_LB1_POST_OVRD_VAL_MASK 0x7 #define GC_FUSE_PROG_LB1_POST_OVRD_VAL_SIZE 0x3 #define GC_FUSE_PROG_LB1_POST_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_OFFSET 0x264 +#define GC_FUSE_PROG_LB1_POST_OVRD_VAL_OFFSET 0x268 #define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_LSB 0x0 #define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_MASK 0x3 #define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_SIZE 0x2 #define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_OFFSET 0x268 +#define GC_FUSE_PROG_LB1_POST_PATCNT_VAL_OFFSET 0x26c #define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_LSB 0x0 #define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_MASK 0x7 #define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_SIZE 0x3 #define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_OFFSET 0x26c +#define GC_FUSE_PROG_LB1_POST_WARMUP_OVRD_VAL_OFFSET 0x270 #define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_LSB 0x0 #define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_MASK 0x3 #define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_SIZE 0x2 #define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_OFFSET 0x270 +#define GC_FUSE_PROG_LB1_POST_WARMUP_CNT_VAL_OFFSET 0x274 #define GC_FUSE_PROG_LB2_POST_OVRD_VAL_LSB 0x0 #define GC_FUSE_PROG_LB2_POST_OVRD_VAL_MASK 0x7 #define GC_FUSE_PROG_LB2_POST_OVRD_VAL_SIZE 0x3 #define GC_FUSE_PROG_LB2_POST_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_OFFSET 0x274 +#define GC_FUSE_PROG_LB2_POST_OVRD_VAL_OFFSET 0x278 #define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_LSB 0x0 #define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_MASK 0x3 #define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_SIZE 0x2 #define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_OFFSET 0x278 +#define GC_FUSE_PROG_LB2_POST_PATCNT_VAL_OFFSET 0x27c #define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_LSB 0x0 #define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_MASK 0x7 #define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_SIZE 0x3 #define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_OFFSET 0x27c +#define GC_FUSE_PROG_LB2_POST_WARMUP_OVRD_VAL_OFFSET 0x280 #define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_LSB 0x0 #define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_MASK 0x3 #define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_SIZE 0x2 #define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_OFFSET 0x280 +#define GC_FUSE_PROG_LB2_POST_WARMUP_CNT_VAL_OFFSET 0x284 #define GC_FUSE_PROG_LB3_POST_OVRD_VAL_LSB 0x0 #define GC_FUSE_PROG_LB3_POST_OVRD_VAL_MASK 0x7 #define GC_FUSE_PROG_LB3_POST_OVRD_VAL_SIZE 0x3 #define GC_FUSE_PROG_LB3_POST_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_OFFSET 0x284 +#define GC_FUSE_PROG_LB3_POST_OVRD_VAL_OFFSET 0x288 #define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_LSB 0x0 #define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_MASK 0x3 #define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_SIZE 0x2 #define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_OFFSET 0x288 +#define GC_FUSE_PROG_LB3_POST_PATCNT_VAL_OFFSET 0x28c #define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_LSB 0x0 #define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_MASK 0x7 #define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_SIZE 0x3 #define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_OFFSET 0x28c +#define GC_FUSE_PROG_LB3_POST_WARMUP_OVRD_VAL_OFFSET 0x290 #define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_LSB 0x0 #define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_MASK 0x3 #define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_SIZE 0x2 #define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_OFFSET 0x290 +#define GC_FUSE_PROG_LB3_POST_WARMUP_CNT_VAL_OFFSET 0x294 #define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_LSB 0x0 #define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_MASK 0x1ffffff #define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_SIZE 0x19 #define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_OFFSET 0x294 +#define GC_FUSE_PROG_MBIST_POST_SEQ_VAL_OFFSET 0x298 #define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_LSB 0x0 #define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_MASK 0xffff #define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_SIZE 0x10 #define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_OFFSET 0x298 +#define GC_FUSE_PROG_LBIST_POST_SEQ_VAL_OFFSET 0x29c #define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_LSB 0x0 #define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_MASK 0x7 #define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_SIZE 0x3 #define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_OFFSET 0x29c +#define GC_FUSE_PROG_LBIST_VIA_TAP_DIS_VAL_OFFSET 0x2a0 #define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_LSB 0x0 #define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_MASK 0x7 #define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_SIZE 0x3 #define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_OFFSET 0x2a0 +#define GC_FUSE_PROG_MBIST_VIA_TAP_DIS_VAL_OFFSET 0x2a4 #define GC_FUSE_PROG_TAP_DISABLE_VAL_LSB 0x0 #define GC_FUSE_PROG_TAP_DISABLE_VAL_MASK 0x7 #define GC_FUSE_PROG_TAP_DISABLE_VAL_SIZE 0x3 #define GC_FUSE_PROG_TAP_DISABLE_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_TAP_DISABLE_VAL_OFFSET 0x2a4 +#define GC_FUSE_PROG_TAP_DISABLE_VAL_OFFSET 0x2a8 #define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_OFFSET 0x2a8 +#define GC_FUSE_PROG_RNGBIST_AR_EN_VAL_OFFSET 0x2ac #define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_OFFSET 0x2ac +#define GC_FUSE_PROG_TESTMODE_KEYS_EN_VAL_OFFSET 0x2b0 #define GC_FUSE_PROG_PKG_ID_VAL_LSB 0x0 #define GC_FUSE_PROG_PKG_ID_VAL_MASK 0x7 #define GC_FUSE_PROG_PKG_ID_VAL_SIZE 0x3 #define GC_FUSE_PROG_PKG_ID_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_PKG_ID_VAL_OFFSET 0x2b0 +#define GC_FUSE_PROG_PKG_ID_VAL_OFFSET 0x2b4 #define GC_FUSE_PROG_BIN_ID_VAL_LSB 0x0 #define GC_FUSE_PROG_BIN_ID_VAL_MASK 0x7 #define GC_FUSE_PROG_BIN_ID_VAL_SIZE 0x3 #define GC_FUSE_PROG_BIN_ID_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_BIN_ID_VAL_OFFSET 0x2b4 +#define GC_FUSE_PROG_BIN_ID_VAL_OFFSET 0x2b8 #define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_LSB 0x0 #define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_MASK 0xff #define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_SIZE 0x8 #define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_OFFSET 0x2b8 +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_TRIM_VAL_OFFSET 0x2bc #define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_OFFSET 0x2bc +#define GC_FUSE_PROG_RC_JTR_OSC48_CC_EN_VAL_OFFSET 0x2c0 #define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_LSB 0x0 #define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_MASK 0xff #define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_SIZE 0x8 #define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_OFFSET 0x2c0 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_TRIM_VAL_OFFSET 0x2c4 #define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_OFFSET 0x2c4 +#define GC_FUSE_PROG_RC_JTR_OSC60_CC_EN_VAL_OFFSET 0x2c8 #define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_LSB 0x0 #define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_MASK 0xff #define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_SIZE 0x8 #define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_OFFSET 0x2c8 +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_TRIM_VAL_OFFSET 0x2cc #define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_OFFSET 0x2cc +#define GC_FUSE_PROG_RC_TIMER_OSC48_CC_EN_VAL_OFFSET 0x2d0 #define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_LSB 0x0 #define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_MASK 0x1f #define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_SIZE 0x5 #define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_OFFSET 0x2d0 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_TRIM_VAL_OFFSET 0x2d4 #define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_OFFSET 0x2d4 +#define GC_FUSE_PROG_RC_TIMER_OSC48_FC_EN_VAL_OFFSET 0x2d8 #define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_VAL_LSB 0x0 #define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_VAL_MASK 0xff #define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_VAL_SIZE 0x8 #define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_VAL_OFFSET 0x2d8 +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_TRIM_VAL_OFFSET 0x2dc #define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_VAL_OFFSET 0x2dc +#define GC_FUSE_PROG_RC_RTC_OSC32K_CC_EN_VAL_OFFSET 0x2e0 #define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_OFFSET 0x2e0 +#define GC_FUSE_PROG_SEL_VREG_REG_EN_VAL_OFFSET 0x2e4 #define GC_FUSE_PROG_SEL_VREF_REG_VAL_LSB 0x0 #define GC_FUSE_PROG_SEL_VREF_REG_VAL_MASK 0xf #define GC_FUSE_PROG_SEL_VREF_REG_VAL_SIZE 0x4 #define GC_FUSE_PROG_SEL_VREF_REG_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_SEL_VREF_REG_VAL_OFFSET 0x2e4 +#define GC_FUSE_PROG_SEL_VREF_REG_VAL_OFFSET 0x2e8 #define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_OFFSET 0x2e8 +#define GC_FUSE_PROG_SEL_VREF_BATMON_EN_VAL_OFFSET 0x2ec #define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_LSB 0x0 #define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_MASK 0x7 #define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_SIZE 0x3 #define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_OFFSET 0x2ec +#define GC_FUSE_PROG_SEL_VREF_BATMON_VAL_OFFSET 0x2f0 #define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_OFFSET 0x2f0 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_EN_VAL_OFFSET 0x2f4 #define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_LSB 0x0 #define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_MASK 0xf #define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_SIZE 0x4 #define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_OFFSET 0x2f4 +#define GC_FUSE_PROG_X_OSC_LDO_CTRL_VAL_OFFSET 0x2f8 #define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_LSB 0x0 #define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_MASK 0x3 #define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_SIZE 0x2 #define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_OFFSET 0x2f8 +#define GC_FUSE_PROG_EXT_XTAL_PDB_VAL_OFFSET 0x2fc #define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_LSB 0x0 #define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_MASK 0x7 #define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_SIZE 0x3 #define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_OFFSET 0x2fc +#define GC_FUSE_PROG_DIS_EXT_XTAL_CLK_TREE_VAL_OFFSET 0x300 #define GC_FUSE_PROG_OBFUSCATION_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_OBFUSCATION_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_OBFUSCATION_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_OBFUSCATION_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_OFFSET 0x300 +#define GC_FUSE_PROG_OBFUSCATION_EN_VAL_OFFSET 0x304 #define GC_FUSE_PROG_JITTER_CLK_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_JITTER_CLK_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_JITTER_CLK_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_JITTER_CLK_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_JITTER_CLK_EN_VAL_OFFSET 0x304 +#define GC_FUSE_PROG_JITTER_CLK_EN_VAL_OFFSET 0x308 #define GC_FUSE_PROG_OBS0_VAL_LSB 0x0 #define GC_FUSE_PROG_OBS0_VAL_MASK 0xffffffff #define GC_FUSE_PROG_OBS0_VAL_SIZE 0x20 #define GC_FUSE_PROG_OBS0_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS0_VAL_OFFSET 0x308 +#define GC_FUSE_PROG_OBS0_VAL_OFFSET 0x30c #define GC_FUSE_PROG_OBS1_VAL_LSB 0x0 #define GC_FUSE_PROG_OBS1_VAL_MASK 0xffffffff #define GC_FUSE_PROG_OBS1_VAL_SIZE 0x20 #define GC_FUSE_PROG_OBS1_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS1_VAL_OFFSET 0x30c +#define GC_FUSE_PROG_OBS1_VAL_OFFSET 0x310 #define GC_FUSE_PROG_OBS2_VAL_LSB 0x0 #define GC_FUSE_PROG_OBS2_VAL_MASK 0xffffffff #define GC_FUSE_PROG_OBS2_VAL_SIZE 0x20 #define GC_FUSE_PROG_OBS2_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS2_VAL_OFFSET 0x310 +#define GC_FUSE_PROG_OBS2_VAL_OFFSET 0x314 #define GC_FUSE_PROG_OBS3_VAL_LSB 0x0 #define GC_FUSE_PROG_OBS3_VAL_MASK 0xffffffff #define GC_FUSE_PROG_OBS3_VAL_SIZE 0x20 #define GC_FUSE_PROG_OBS3_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS3_VAL_OFFSET 0x314 +#define GC_FUSE_PROG_OBS3_VAL_OFFSET 0x318 #define GC_FUSE_PROG_OBS4_VAL_LSB 0x0 #define GC_FUSE_PROG_OBS4_VAL_MASK 0xffffffff #define GC_FUSE_PROG_OBS4_VAL_SIZE 0x20 #define GC_FUSE_PROG_OBS4_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS4_VAL_OFFSET 0x318 +#define GC_FUSE_PROG_OBS4_VAL_OFFSET 0x31c #define GC_FUSE_PROG_OBS5_VAL_LSB 0x0 #define GC_FUSE_PROG_OBS5_VAL_MASK 0xffffffff #define GC_FUSE_PROG_OBS5_VAL_SIZE 0x20 #define GC_FUSE_PROG_OBS5_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS5_VAL_OFFSET 0x31c +#define GC_FUSE_PROG_OBS5_VAL_OFFSET 0x320 #define GC_FUSE_PROG_OBS6_VAL_LSB 0x0 #define GC_FUSE_PROG_OBS6_VAL_MASK 0xffffffff #define GC_FUSE_PROG_OBS6_VAL_SIZE 0x20 #define GC_FUSE_PROG_OBS6_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS6_VAL_OFFSET 0x320 +#define GC_FUSE_PROG_OBS6_VAL_OFFSET 0x324 #define GC_FUSE_PROG_OBS7_VAL_LSB 0x0 #define GC_FUSE_PROG_OBS7_VAL_MASK 0xffffffff #define GC_FUSE_PROG_OBS7_VAL_SIZE 0x20 #define GC_FUSE_PROG_OBS7_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_OBS7_VAL_OFFSET 0x324 +#define GC_FUSE_PROG_OBS7_VAL_OFFSET 0x328 #define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_LSB 0x0 #define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_MASK 0x7 #define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_SIZE 0x3 #define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_OFFSET 0x328 +#define GC_FUSE_PROG_HIK_CREATE_LOCK_VAL_OFFSET 0x32c #define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_LSB 0x0 #define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_MASK 0xffffff #define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_SIZE 0x18 #define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_OFFSET 0x32c +#define GC_FUSE_PROG_BNK2_INTG_CHKSUM_VAL_OFFSET 0x330 #define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_LSB 0x0 #define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_MASK 0x7 #define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_SIZE 0x3 #define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_OFFSET 0x330 +#define GC_FUSE_PROG_BNK2_INTG_LOCK_VAL_OFFSET 0x334 #define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_LSB 0x0 #define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_MASK 0x7 #define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_SIZE 0x3 #define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_OFFSET 0x334 +#define GC_FUSE_PROG_TESTMODE_OTPW_DIS_VAL_OFFSET 0x338 #define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_LSB 0x0 #define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_MASK 0x7 #define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_SIZE 0x3 #define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_OFFSET 0x338 +#define GC_FUSE_PROG_HKEY_WDOG_TIMER_EN_VAL_OFFSET 0x33c #define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_LSB 0x0 #define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_MASK 0x7 #define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_SIZE 0x3 #define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_OFFSET 0x33c +#define GC_FUSE_PROG_FLASH_PERSO_PAGE_LOCK_VAL_OFFSET 0x340 #define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_LSB 0x0 #define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_MASK 0xff #define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_SIZE 0x8 #define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_OFFSET 0x340 +#define GC_FUSE_PROG_ALERT_RSP_CFG_VAL_OFFSET 0x344 #define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_LSB 0x0 #define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_MASK 0xffffff #define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_SIZE 0x18 #define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_OFFSET 0x344 +#define GC_FUSE_PROG_BNK3_INTG_CHKSUM_VAL_OFFSET 0x348 #define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_LSB 0x0 #define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_MASK 0x7 #define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_SIZE 0x3 #define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_OFFSET 0x348 +#define GC_FUSE_PROG_BNK3_INTG_LOCK_VAL_OFFSET 0x34c #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_OFFSET 0x34c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK0_VAL_OFFSET 0x350 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_VAL_OFFSET 0x350 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK1_VAL_OFFSET 0x354 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_VAL_OFFSET 0x354 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK2_VAL_OFFSET 0x358 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_VAL_OFFSET 0x358 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK3_VAL_OFFSET 0x35c #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_VAL_OFFSET 0x35c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK4_VAL_OFFSET 0x360 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_VAL_OFFSET 0x360 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK5_VAL_OFFSET 0x364 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_VAL_OFFSET 0x364 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK6_VAL_OFFSET 0x368 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_VAL_OFFSET 0x368 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK7_VAL_OFFSET 0x36c #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_VAL_OFFSET 0x36c +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK8_VAL_OFFSET 0x370 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_VAL_OFFSET 0x370 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK9_VAL_OFFSET 0x374 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_VAL_OFFSET 0x374 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK10_VAL_OFFSET 0x378 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_VAL_OFFSET 0x378 +#define GC_FUSE_PROG_FW_DEFINED_DATA_BLK11_VAL_OFFSET 0x37c #define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_OFFSET 0x37c +#define GC_FUSE_PROG_RBOX_MODE_DBG_OVRD_DIS_VAL_OFFSET 0x380 #define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_MASK 0x7f #define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_SIZE 0x7 #define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_OFFSET 0x380 +#define GC_FUSE_PROG_RBOX_MODE_OUTPUT_OVRD_DIS_VAL_OFFSET 0x384 #define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_MASK 0xffff #define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_SIZE 0x10 #define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_OFFSET 0x384 +#define GC_FUSE_PROG_RBOX_CLK10HZ_COUNT_VAL_OFFSET 0x388 #define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_MASK 0xffff #define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_SIZE 0x10 #define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_OFFSET 0x388 +#define GC_FUSE_PROG_RBOX_SHORT_DELAY_COUNT_VAL_OFFSET 0x38c #define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_MASK 0xff #define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_SIZE 0x8 #define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_OFFSET 0x38c +#define GC_FUSE_PROG_RBOX_LONG_DELAY_COUNT_VAL_OFFSET 0x390 #define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_MASK 0xffff #define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_SIZE 0x10 #define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_OFFSET 0x390 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_PERIOD_VAL_OFFSET 0x394 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_OFFSET 0x394 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_PWRB_VAL_OFFSET 0x398 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_OFFSET 0x398 +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY0_VAL_OFFSET 0x39c #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_OFFSET 0x39c +#define GC_FUSE_PROG_RBOX_DEBOUNCE_BYPASS_KEY1_VAL_OFFSET 0x3a0 #define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_MASK 0xff #define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_SIZE 0x8 #define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_OFFSET 0x3a0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_VAL_VAL_OFFSET 0x3a4 #define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_MASK 0xff #define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_SIZE 0x8 #define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_OFFSET 0x3a4 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_VAL_VAL_OFFSET 0x3a8 #define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_MASK 0xff #define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_SIZE 0x8 #define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_OFFSET 0x3a8 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_VAL_VAL_OFFSET 0x3ac #define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_MASK 0xff #define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_SIZE 0x8 #define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_OFFSET 0x3ac +#define GC_FUSE_PROG_RBOX_KEY_COMBO0_HOLD_VAL_OFFSET 0x3b0 #define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_MASK 0xff #define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_SIZE 0x8 #define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_OFFSET 0x3b0 +#define GC_FUSE_PROG_RBOX_KEY_COMBO1_HOLD_VAL_OFFSET 0x3b4 #define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_MASK 0xff #define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_SIZE 0x8 #define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_OFFSET 0x3b4 +#define GC_FUSE_PROG_RBOX_KEY_COMBO2_HOLD_VAL_OFFSET 0x3b8 #define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_OFFSET 0x3b8 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_SEL_VAL_OFFSET 0x3bc #define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_OFFSET 0x3bc +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_SEL_VAL_OFFSET 0x3c0 #define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_OFFSET 0x3c0 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY0_VAL_VAL_OFFSET 0x3c4 #define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_OFFSET 0x3c4 +#define GC_FUSE_PROG_RBOX_BLOCK_KEY1_VAL_VAL_OFFSET 0x3c8 #define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_OFFSET 0x3c8 +#define GC_FUSE_PROG_RBOX_POL_AC_PRESENT_VAL_OFFSET 0x3cc #define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_OFFSET 0x3cc +#define GC_FUSE_PROG_RBOX_POL_PWRB_IN_VAL_OFFSET 0x3d0 #define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_OFFSET 0x3d0 +#define GC_FUSE_PROG_RBOX_POL_PWRB_OUT_VAL_OFFSET 0x3d4 #define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_OFFSET 0x3d4 +#define GC_FUSE_PROG_RBOX_POL_KEY0_IN_VAL_OFFSET 0x3d8 #define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_OFFSET 0x3d8 +#define GC_FUSE_PROG_RBOX_POL_KEY0_OUT_VAL_OFFSET 0x3dc #define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_OFFSET 0x3dc +#define GC_FUSE_PROG_RBOX_POL_KEY1_IN_VAL_OFFSET 0x3e0 #define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_OFFSET 0x3e0 +#define GC_FUSE_PROG_RBOX_POL_KEY1_OUT_VAL_OFFSET 0x3e4 #define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_OFFSET 0x3e4 +#define GC_FUSE_PROG_RBOX_POL_EC_RST_VAL_OFFSET 0x3e8 #define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_MASK 0x1 #define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_SIZE 0x1 #define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_OFFSET 0x3e8 +#define GC_FUSE_PROG_RBOX_POL_BATT_DISABLE_VAL_OFFSET 0x3ec #define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_OFFSET 0x3ec +#define GC_FUSE_PROG_RBOX_TERM_AC_PRESENT_VAL_OFFSET 0x3f0 #define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_OFFSET 0x3f0 +#define GC_FUSE_PROG_RBOX_TERM_ENTERING_RW_VAL_OFFSET 0x3f4 #define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_OFFSET 0x3f4 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_IN_VAL_OFFSET 0x3f8 #define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_OFFSET 0x3f8 +#define GC_FUSE_PROG_RBOX_TERM_PWRB_OUT_VAL_OFFSET 0x3fc #define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_OFFSET 0x3fc +#define GC_FUSE_PROG_RBOX_TERM_KEY0_IN_VAL_OFFSET 0x400 #define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_OFFSET 0x400 +#define GC_FUSE_PROG_RBOX_TERM_KEY0_OUT_VAL_OFFSET 0x404 #define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_OFFSET 0x404 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_IN_VAL_OFFSET 0x408 #define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_OFFSET 0x408 +#define GC_FUSE_PROG_RBOX_TERM_KEY1_OUT_VAL_OFFSET 0x40c #define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_OFFSET 0x40c +#define GC_FUSE_PROG_RBOX_DRIVE_PWRB_OUT_VAL_OFFSET 0x410 #define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_OFFSET 0x410 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY0_OUT_VAL_OFFSET 0x414 #define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_OFFSET 0x414 +#define GC_FUSE_PROG_RBOX_DRIVE_KEY1_OUT_VAL_OFFSET 0x418 #define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_OFFSET 0x418 +#define GC_FUSE_PROG_RBOX_DRIVE_EC_RST_VAL_OFFSET 0x41c #define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_LSB 0x0 #define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_MASK 0x3 #define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_SIZE 0x2 #define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_OFFSET 0x41c +#define GC_FUSE_PROG_RBOX_DRIVE_BATT_DISABLE_VAL_OFFSET 0x420 #define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_LSB 0x0 #define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_MASK 0xffffff #define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_SIZE 0x18 #define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_OFFSET 0x420 +#define GC_FUSE_PROG_BNK4_INTG_CHKSUM_VAL_OFFSET 0x424 #define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_LSB 0x0 #define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_MASK 0x7 #define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_SIZE 0x3 #define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_OFFSET 0x424 +#define GC_FUSE_PROG_BNK4_INTG_LOCK_VAL_OFFSET 0x428 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_OFFSET 0x428 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK0_VAL_OFFSET 0x42c #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_OFFSET 0x42c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK1_VAL_OFFSET 0x430 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_OFFSET 0x430 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK2_VAL_OFFSET 0x434 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_OFFSET 0x434 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK3_VAL_OFFSET 0x438 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_OFFSET 0x438 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK4_VAL_OFFSET 0x43c #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_OFFSET 0x43c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK5_VAL_OFFSET 0x440 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_OFFSET 0x440 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK6_VAL_OFFSET 0x444 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_VAL_OFFSET 0x444 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK7_VAL_OFFSET 0x448 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_VAL_OFFSET 0x448 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK8_VAL_OFFSET 0x44c #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_VAL_MASK 0xff #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_VAL_SIZE 0x8 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_VAL_OFFSET 0x44c +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK9_VAL_OFFSET 0x450 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_VAL_LSB 0x0 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_VAL_MASK 0x7f #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_VAL_SIZE 0x7 #define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_VAL_DEFAULT 0x0 -#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_VAL_OFFSET 0x450 +#define GC_FUSE_PROG_FW_DEFINED_DATA_EXTRA_BLK10_VAL_OFFSET 0x454 #define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_LSB 0x0 #define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_MASK 0x1 #define GC_GLOBALSEC_CPU0_D_REGION0_CTRL_EN_SIZE 0x1 @@ -9141,126 +9241,246 @@ #define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_SIZE 0x1 #define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_DEFAULT 0x0 #define GC_GLOBALSEC_DUSB0_REGION3_CTRL_WR_EN_OFFSET 0x6c +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_EN_OFFSET 0x70 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_RD_EN_OFFSET 0x70 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION0_CTRL_WR_EN_OFFSET 0x70 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_EN_OFFSET 0x74 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_RD_EN_OFFSET 0x74 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION1_CTRL_WR_EN_OFFSET 0x74 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_EN_OFFSET 0x78 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_RD_EN_OFFSET 0x78 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION2_CTRL_WR_EN_OFFSET 0x78 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_EN_OFFSET 0x7c +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_RD_EN_OFFSET 0x7c +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH0_REGION3_CTRL_WR_EN_OFFSET 0x7c +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_EN_OFFSET 0x84 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_RD_EN_OFFSET 0x84 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION0_CTRL_WR_EN_OFFSET 0x84 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_EN_OFFSET 0x88 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_RD_EN_OFFSET 0x88 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION1_CTRL_WR_EN_OFFSET 0x88 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_EN_OFFSET 0x8c +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_RD_EN_OFFSET 0x8c +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION2_CTRL_WR_EN_OFFSET 0x8c +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_EN_LSB 0x0 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_EN_MASK 0x1 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_EN_OFFSET 0x90 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_RD_EN_LSB 0x1 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_RD_EN_MASK 0x2 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_RD_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_RD_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_RD_EN_OFFSET 0x90 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_WR_EN_LSB 0x2 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_WR_EN_MASK 0x4 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_WR_EN_SIZE 0x1 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_WR_EN_DEFAULT 0x0 +#define GC_GLOBALSEC_FLASH1_REGION3_CTRL_WR_EN_OFFSET 0x90 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_LSB 0x0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_MASK 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_OFFSET 0x150 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_EN_OFFSET 0x1b8 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_LSB 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_MASK 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_OFFSET 0x150 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_RD_EN_OFFSET 0x1b8 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_LSB 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_MASK 0x4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_OFFSET 0x150 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION0_CTRL_WR_EN_OFFSET 0x1b8 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_LSB 0x0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_MASK 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_OFFSET 0x15c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_EN_OFFSET 0x1c4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_LSB 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_MASK 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_OFFSET 0x15c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_RD_EN_OFFSET 0x1c4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_LSB 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_MASK 0x4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_OFFSET 0x15c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION1_CTRL_WR_EN_OFFSET 0x1c4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_LSB 0x0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_MASK 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_OFFSET 0x168 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_EN_OFFSET 0x1d0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_LSB 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_MASK 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_OFFSET 0x168 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_RD_EN_OFFSET 0x1d0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_LSB 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_MASK 0x4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_OFFSET 0x168 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION2_CTRL_WR_EN_OFFSET 0x1d0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_LSB 0x0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_MASK 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_OFFSET 0x174 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_EN_OFFSET 0x1dc #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_LSB 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_MASK 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_OFFSET 0x174 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_RD_EN_OFFSET 0x1dc #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_LSB 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_MASK 0x4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_OFFSET 0x174 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION3_CTRL_WR_EN_OFFSET 0x1dc #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_LSB 0x0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_MASK 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_OFFSET 0x180 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_EN_OFFSET 0x1e8 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_LSB 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_MASK 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_OFFSET 0x180 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_RD_EN_OFFSET 0x1e8 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_LSB 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_MASK 0x4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_OFFSET 0x180 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION4_CTRL_WR_EN_OFFSET 0x1e8 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_LSB 0x0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_MASK 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_OFFSET 0x18c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_EN_OFFSET 0x1f4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_LSB 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_MASK 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_OFFSET 0x18c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_RD_EN_OFFSET 0x1f4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_LSB 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_MASK 0x4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_OFFSET 0x18c +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION5_CTRL_WR_EN_OFFSET 0x1f4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_LSB 0x0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_MASK 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_OFFSET 0x198 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_EN_OFFSET 0x200 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_LSB 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_MASK 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_OFFSET 0x198 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_RD_EN_OFFSET 0x200 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_LSB 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_MASK 0x4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_OFFSET 0x198 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION6_CTRL_WR_EN_OFFSET 0x200 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_LSB 0x0 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_MASK 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_OFFSET 0x1a4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_EN_OFFSET 0x20c #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_LSB 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_MASK 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_OFFSET 0x1a4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_RD_EN_OFFSET 0x20c #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_LSB 0x2 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_MASK 0x4 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_SIZE 0x1 #define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_DEFAULT 0x0 -#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_OFFSET 0x1a4 +#define GC_GLOBALSEC_CPU0_I_STAGING_REGION7_CTRL_WR_EN_OFFSET 0x20c #define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_LSB 0x0 #define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_MASK 0x1 #define GC_GLOBALSEC_SB_COMP_STATUS_SB_BL_SIG_MATCH_SIZE 0x1 @@ -11174,12 +11394,12 @@ #define GC_GLOBALSEC_VERSION_CHANGE_LSB 0x0 #define GC_GLOBALSEC_VERSION_CHANGE_MASK 0xffffff #define GC_GLOBALSEC_VERSION_CHANGE_SIZE 0x18 -#define GC_GLOBALSEC_VERSION_CHANGE_DEFAULT 0x11ff3 +#define GC_GLOBALSEC_VERSION_CHANGE_DEFAULT 0x10913 #define GC_GLOBALSEC_VERSION_CHANGE_OFFSET 0x40d4 #define GC_GLOBALSEC_VERSION_REVISION_LSB 0x18 #define GC_GLOBALSEC_VERSION_REVISION_MASK 0xff000000 #define GC_GLOBALSEC_VERSION_REVISION_SIZE 0x8 -#define GC_GLOBALSEC_VERSION_REVISION_DEFAULT 0x26 +#define GC_GLOBALSEC_VERSION_REVISION_DEFAULT 0x59 #define GC_GLOBALSEC_VERSION_REVISION_OFFSET 0x40d4 #define GC_I2C_CTRL_PHASESTEPS_P0_LSB 0x0 #define GC_I2C_CTRL_PHASESTEPS_P0_MASK 0x3f @@ -12355,112 +12575,112 @@ #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_MASK 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_0S_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_1S_ERR_LSB 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_1S_ERR_MASK 0x2 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_1S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_1S_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_1S_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_ALL_1S_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_SLOT_VLD_ERR_LSB 0x2 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_SLOT_VLD_ERR_MASK 0x4 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_SLOT_VLD_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_AES_SLOT_VLD_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_SLOT_VLD_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_AES_SLOT_VLD_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ADDR_ERR_LSB 0x3 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ADDR_ERR_MASK 0x8 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ADDR_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ADDR_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ADDR_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ADDR_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_0S_ERR_LSB 0x4 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_0S_ERR_MASK 0x10 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_0S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_0S_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_0S_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_0S_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_LSB 0x5 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_MASK 0x20 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_DIGEST_ALL_1S_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_LSB 0x6 #define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_MASK 0x40 #define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_OVFL_GEN_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_LSB 0x7 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_MASK 0x80 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_0S_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_LSB 0x8 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_MASK 0x100 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_ALL_1S_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_LSB 0x9 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_MASK 0x200 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SHA_SLOT_VLD_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_LSB 0xa #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_MASK 0x400 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_CMP_FAIL_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_LSB 0xb #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_MASK 0x800 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_GEN_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_LSB 0xc #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_MASK 0x1000 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_SLOT_WRG_ID_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_LSB 0xd #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_MASK 0x2000 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_0S_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_LSB 0xe #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_MASK 0x4000 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_PW_ALL_1S_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_LSB 0xf #define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_MASK 0x8000 #define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_UNLOCK_TRYS_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_LSB 0x10 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_MASK 0x10000 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_FBS_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_LSB 0x11 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_MASK 0x20000 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_OFFSET 0x3320 +#define GC_KEYMGR_HKEY_ERR_FLAGS_FLASH_RSR_ERR_OFFSET 0x3324 #define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_LSB 0x0 #define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_MASK 0x1 #define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_OFFSET 0x3324 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG0_CHK_EN_OFFSET 0x3328 #define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_LSB 0x1 #define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_MASK 0x2 #define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_OFFSET 0x3324 +#define GC_KEYMGR_HKEY_ERR_CTRL_LONG1_CHK_EN_OFFSET 0x3328 #define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_LSB 0x2 #define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_MASK 0x4 #define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_OFFSET 0x3324 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG0_CHK_EN_OFFSET 0x3328 #define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_LSB 0x3 #define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_MASK 0x8 #define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_SIZE 0x1 #define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_DEFAULT 0x0 -#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_OFFSET 0x3324 +#define GC_KEYMGR_HKEY_ERR_CTRL_TM_LONG1_CHK_EN_OFFSET 0x3328 #define GC_MAU_EN_SYSIBUS_LSB 0x0 #define GC_MAU_EN_SYSIBUS_MASK 0x1 #define GC_MAU_EN_SYSIBUS_SIZE 0x1 @@ -13320,482 +13540,482 @@ #define GC_PINMUX_EXITEN0_DIOM0_MASK 0x1 #define GC_PINMUX_EXITEN0_DIOM0_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM0_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOM0_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOM1_LSB 0x1 #define GC_PINMUX_EXITEN0_DIOM1_MASK 0x2 #define GC_PINMUX_EXITEN0_DIOM1_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM1_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOM1_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOM2_LSB 0x2 #define GC_PINMUX_EXITEN0_DIOM2_MASK 0x4 #define GC_PINMUX_EXITEN0_DIOM2_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM2_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM2_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOM2_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOM3_LSB 0x3 #define GC_PINMUX_EXITEN0_DIOM3_MASK 0x8 #define GC_PINMUX_EXITEN0_DIOM3_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM3_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM3_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOM3_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOM4_LSB 0x4 #define GC_PINMUX_EXITEN0_DIOM4_MASK 0x10 #define GC_PINMUX_EXITEN0_DIOM4_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOM4_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOM4_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOM4_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA0_LSB 0x5 #define GC_PINMUX_EXITEN0_DIOA0_MASK 0x20 #define GC_PINMUX_EXITEN0_DIOA0_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA0_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA0_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA1_LSB 0x6 #define GC_PINMUX_EXITEN0_DIOA1_MASK 0x40 #define GC_PINMUX_EXITEN0_DIOA1_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA1_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA1_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA2_LSB 0x7 #define GC_PINMUX_EXITEN0_DIOA2_MASK 0x80 #define GC_PINMUX_EXITEN0_DIOA2_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA2_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA2_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA2_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA3_LSB 0x8 #define GC_PINMUX_EXITEN0_DIOA3_MASK 0x100 #define GC_PINMUX_EXITEN0_DIOA3_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA3_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA3_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA3_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA4_LSB 0x9 #define GC_PINMUX_EXITEN0_DIOA4_MASK 0x200 #define GC_PINMUX_EXITEN0_DIOA4_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA4_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA4_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA4_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA5_LSB 0xa #define GC_PINMUX_EXITEN0_DIOA5_MASK 0x400 #define GC_PINMUX_EXITEN0_DIOA5_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA5_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA5_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA5_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA6_LSB 0xb #define GC_PINMUX_EXITEN0_DIOA6_MASK 0x800 #define GC_PINMUX_EXITEN0_DIOA6_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA6_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA6_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA6_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA7_LSB 0xc #define GC_PINMUX_EXITEN0_DIOA7_MASK 0x1000 #define GC_PINMUX_EXITEN0_DIOA7_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA7_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA7_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA7_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA8_LSB 0xd #define GC_PINMUX_EXITEN0_DIOA8_MASK 0x2000 #define GC_PINMUX_EXITEN0_DIOA8_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA8_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA8_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA8_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA9_LSB 0xe #define GC_PINMUX_EXITEN0_DIOA9_MASK 0x4000 #define GC_PINMUX_EXITEN0_DIOA9_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA9_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA9_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA9_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA10_LSB 0xf #define GC_PINMUX_EXITEN0_DIOA10_MASK 0x8000 #define GC_PINMUX_EXITEN0_DIOA10_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA10_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA10_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA10_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA11_LSB 0x10 #define GC_PINMUX_EXITEN0_DIOA11_MASK 0x10000 #define GC_PINMUX_EXITEN0_DIOA11_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA11_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA11_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA11_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA12_LSB 0x11 #define GC_PINMUX_EXITEN0_DIOA12_MASK 0x20000 #define GC_PINMUX_EXITEN0_DIOA12_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA12_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA12_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA12_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA13_LSB 0x12 #define GC_PINMUX_EXITEN0_DIOA13_MASK 0x40000 #define GC_PINMUX_EXITEN0_DIOA13_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA13_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA13_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA13_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOA14_LSB 0x13 #define GC_PINMUX_EXITEN0_DIOA14_MASK 0x80000 #define GC_PINMUX_EXITEN0_DIOA14_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOA14_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOA14_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOA14_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOB0_LSB 0x14 #define GC_PINMUX_EXITEN0_DIOB0_MASK 0x100000 #define GC_PINMUX_EXITEN0_DIOB0_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB0_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOB0_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOB1_LSB 0x15 #define GC_PINMUX_EXITEN0_DIOB1_MASK 0x200000 #define GC_PINMUX_EXITEN0_DIOB1_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB1_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOB1_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOB2_LSB 0x16 #define GC_PINMUX_EXITEN0_DIOB2_MASK 0x400000 #define GC_PINMUX_EXITEN0_DIOB2_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB2_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB2_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOB2_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOB3_LSB 0x17 #define GC_PINMUX_EXITEN0_DIOB3_MASK 0x800000 #define GC_PINMUX_EXITEN0_DIOB3_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB3_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB3_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOB3_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOB4_LSB 0x18 #define GC_PINMUX_EXITEN0_DIOB4_MASK 0x1000000 #define GC_PINMUX_EXITEN0_DIOB4_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB4_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB4_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOB4_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOB5_LSB 0x19 #define GC_PINMUX_EXITEN0_DIOB5_MASK 0x2000000 #define GC_PINMUX_EXITEN0_DIOB5_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB5_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB5_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOB5_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOB6_LSB 0x1a #define GC_PINMUX_EXITEN0_DIOB6_MASK 0x4000000 #define GC_PINMUX_EXITEN0_DIOB6_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB6_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB6_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOB6_OFFSET 0x234 #define GC_PINMUX_EXITEN0_DIOB7_LSB 0x1b #define GC_PINMUX_EXITEN0_DIOB7_MASK 0x8000000 #define GC_PINMUX_EXITEN0_DIOB7_SIZE 0x1 #define GC_PINMUX_EXITEN0_DIOB7_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_DIOB7_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_DIOB7_OFFSET 0x234 #define GC_PINMUX_EXITEN0_SWDPTRACE_LSB 0x1c #define GC_PINMUX_EXITEN0_SWDPTRACE_MASK 0x10000000 #define GC_PINMUX_EXITEN0_SWDPTRACE_SIZE 0x1 #define GC_PINMUX_EXITEN0_SWDPTRACE_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_SWDPTRACE_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_SWDPTRACE_OFFSET 0x234 #define GC_PINMUX_EXITEN0_SWDPDATA_LSB 0x1d #define GC_PINMUX_EXITEN0_SWDPDATA_MASK 0x20000000 #define GC_PINMUX_EXITEN0_SWDPDATA_SIZE 0x1 #define GC_PINMUX_EXITEN0_SWDPDATA_DEFAULT 0x0 -#define GC_PINMUX_EXITEN0_SWDPDATA_OFFSET 0x238 +#define GC_PINMUX_EXITEN0_SWDPDATA_OFFSET 0x234 #define GC_PINMUX_EXITEN1_VIO0_LSB 0x3 #define GC_PINMUX_EXITEN1_VIO0_MASK 0x8 #define GC_PINMUX_EXITEN1_VIO0_SIZE 0x1 #define GC_PINMUX_EXITEN1_VIO0_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_VIO0_OFFSET 0x23c +#define GC_PINMUX_EXITEN1_VIO0_OFFSET 0x238 #define GC_PINMUX_EXITEN1_VIO1_LSB 0x4 #define GC_PINMUX_EXITEN1_VIO1_MASK 0x10 #define GC_PINMUX_EXITEN1_VIO1_SIZE 0x1 #define GC_PINMUX_EXITEN1_VIO1_DEFAULT 0x0 -#define GC_PINMUX_EXITEN1_VIO1_OFFSET 0x23c +#define GC_PINMUX_EXITEN1_VIO1_OFFSET 0x238 #define GC_PINMUX_EXITEDGE0_DIOM0_LSB 0x0 #define GC_PINMUX_EXITEDGE0_DIOM0_MASK 0x1 #define GC_PINMUX_EXITEDGE0_DIOM0_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM0_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOM0_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOM1_LSB 0x1 #define GC_PINMUX_EXITEDGE0_DIOM1_MASK 0x2 #define GC_PINMUX_EXITEDGE0_DIOM1_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM1_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOM1_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOM2_LSB 0x2 #define GC_PINMUX_EXITEDGE0_DIOM2_MASK 0x4 #define GC_PINMUX_EXITEDGE0_DIOM2_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM2_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM2_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOM2_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOM3_LSB 0x3 #define GC_PINMUX_EXITEDGE0_DIOM3_MASK 0x8 #define GC_PINMUX_EXITEDGE0_DIOM3_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM3_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM3_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOM3_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOM4_LSB 0x4 #define GC_PINMUX_EXITEDGE0_DIOM4_MASK 0x10 #define GC_PINMUX_EXITEDGE0_DIOM4_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOM4_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOM4_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOM4_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA0_LSB 0x5 #define GC_PINMUX_EXITEDGE0_DIOA0_MASK 0x20 #define GC_PINMUX_EXITEDGE0_DIOA0_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA0_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA0_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA1_LSB 0x6 #define GC_PINMUX_EXITEDGE0_DIOA1_MASK 0x40 #define GC_PINMUX_EXITEDGE0_DIOA1_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA1_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA1_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA2_LSB 0x7 #define GC_PINMUX_EXITEDGE0_DIOA2_MASK 0x80 #define GC_PINMUX_EXITEDGE0_DIOA2_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA2_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA2_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA2_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA3_LSB 0x8 #define GC_PINMUX_EXITEDGE0_DIOA3_MASK 0x100 #define GC_PINMUX_EXITEDGE0_DIOA3_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA3_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA3_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA3_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA4_LSB 0x9 #define GC_PINMUX_EXITEDGE0_DIOA4_MASK 0x200 #define GC_PINMUX_EXITEDGE0_DIOA4_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA4_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA4_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA4_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA5_LSB 0xa #define GC_PINMUX_EXITEDGE0_DIOA5_MASK 0x400 #define GC_PINMUX_EXITEDGE0_DIOA5_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA5_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA5_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA5_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA6_LSB 0xb #define GC_PINMUX_EXITEDGE0_DIOA6_MASK 0x800 #define GC_PINMUX_EXITEDGE0_DIOA6_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA6_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA6_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA6_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA7_LSB 0xc #define GC_PINMUX_EXITEDGE0_DIOA7_MASK 0x1000 #define GC_PINMUX_EXITEDGE0_DIOA7_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA7_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA7_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA7_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA8_LSB 0xd #define GC_PINMUX_EXITEDGE0_DIOA8_MASK 0x2000 #define GC_PINMUX_EXITEDGE0_DIOA8_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA8_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA8_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA8_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA9_LSB 0xe #define GC_PINMUX_EXITEDGE0_DIOA9_MASK 0x4000 #define GC_PINMUX_EXITEDGE0_DIOA9_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA9_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA9_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA9_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA10_LSB 0xf #define GC_PINMUX_EXITEDGE0_DIOA10_MASK 0x8000 #define GC_PINMUX_EXITEDGE0_DIOA10_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA10_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA10_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA10_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA11_LSB 0x10 #define GC_PINMUX_EXITEDGE0_DIOA11_MASK 0x10000 #define GC_PINMUX_EXITEDGE0_DIOA11_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA11_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA11_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA11_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA12_LSB 0x11 #define GC_PINMUX_EXITEDGE0_DIOA12_MASK 0x20000 #define GC_PINMUX_EXITEDGE0_DIOA12_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA12_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA12_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA12_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA13_LSB 0x12 #define GC_PINMUX_EXITEDGE0_DIOA13_MASK 0x40000 #define GC_PINMUX_EXITEDGE0_DIOA13_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA13_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA13_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA13_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOA14_LSB 0x13 #define GC_PINMUX_EXITEDGE0_DIOA14_MASK 0x80000 #define GC_PINMUX_EXITEDGE0_DIOA14_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOA14_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOA14_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOA14_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOB0_LSB 0x14 #define GC_PINMUX_EXITEDGE0_DIOB0_MASK 0x100000 #define GC_PINMUX_EXITEDGE0_DIOB0_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB0_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOB0_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOB1_LSB 0x15 #define GC_PINMUX_EXITEDGE0_DIOB1_MASK 0x200000 #define GC_PINMUX_EXITEDGE0_DIOB1_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB1_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOB1_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOB2_LSB 0x16 #define GC_PINMUX_EXITEDGE0_DIOB2_MASK 0x400000 #define GC_PINMUX_EXITEDGE0_DIOB2_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB2_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB2_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOB2_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOB3_LSB 0x17 #define GC_PINMUX_EXITEDGE0_DIOB3_MASK 0x800000 #define GC_PINMUX_EXITEDGE0_DIOB3_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB3_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB3_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOB3_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOB4_LSB 0x18 #define GC_PINMUX_EXITEDGE0_DIOB4_MASK 0x1000000 #define GC_PINMUX_EXITEDGE0_DIOB4_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB4_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB4_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOB4_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOB5_LSB 0x19 #define GC_PINMUX_EXITEDGE0_DIOB5_MASK 0x2000000 #define GC_PINMUX_EXITEDGE0_DIOB5_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB5_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB5_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOB5_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOB6_LSB 0x1a #define GC_PINMUX_EXITEDGE0_DIOB6_MASK 0x4000000 #define GC_PINMUX_EXITEDGE0_DIOB6_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB6_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB6_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOB6_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_DIOB7_LSB 0x1b #define GC_PINMUX_EXITEDGE0_DIOB7_MASK 0x8000000 #define GC_PINMUX_EXITEDGE0_DIOB7_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_DIOB7_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_DIOB7_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_DIOB7_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_SWDPTRACE_LSB 0x1c #define GC_PINMUX_EXITEDGE0_SWDPTRACE_MASK 0x10000000 #define GC_PINMUX_EXITEDGE0_SWDPTRACE_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_SWDPTRACE_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_SWDPTRACE_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_SWDPTRACE_OFFSET 0x23c #define GC_PINMUX_EXITEDGE0_SWDPDATA_LSB 0x1d #define GC_PINMUX_EXITEDGE0_SWDPDATA_MASK 0x20000000 #define GC_PINMUX_EXITEDGE0_SWDPDATA_SIZE 0x1 #define GC_PINMUX_EXITEDGE0_SWDPDATA_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE0_SWDPDATA_OFFSET 0x240 +#define GC_PINMUX_EXITEDGE0_SWDPDATA_OFFSET 0x23c #define GC_PINMUX_EXITEDGE1_VIO0_LSB 0x3 #define GC_PINMUX_EXITEDGE1_VIO0_MASK 0x8 #define GC_PINMUX_EXITEDGE1_VIO0_SIZE 0x1 #define GC_PINMUX_EXITEDGE1_VIO0_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_VIO0_OFFSET 0x244 +#define GC_PINMUX_EXITEDGE1_VIO0_OFFSET 0x240 #define GC_PINMUX_EXITEDGE1_VIO1_LSB 0x4 #define GC_PINMUX_EXITEDGE1_VIO1_MASK 0x10 #define GC_PINMUX_EXITEDGE1_VIO1_SIZE 0x1 #define GC_PINMUX_EXITEDGE1_VIO1_DEFAULT 0x0 -#define GC_PINMUX_EXITEDGE1_VIO1_OFFSET 0x244 +#define GC_PINMUX_EXITEDGE1_VIO1_OFFSET 0x240 #define GC_PINMUX_EXITINV0_DIOM0_LSB 0x0 #define GC_PINMUX_EXITINV0_DIOM0_MASK 0x1 #define GC_PINMUX_EXITINV0_DIOM0_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM0_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOM0_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOM1_LSB 0x1 #define GC_PINMUX_EXITINV0_DIOM1_MASK 0x2 #define GC_PINMUX_EXITINV0_DIOM1_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM1_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOM1_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOM2_LSB 0x2 #define GC_PINMUX_EXITINV0_DIOM2_MASK 0x4 #define GC_PINMUX_EXITINV0_DIOM2_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM2_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM2_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOM2_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOM3_LSB 0x3 #define GC_PINMUX_EXITINV0_DIOM3_MASK 0x8 #define GC_PINMUX_EXITINV0_DIOM3_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM3_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM3_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOM3_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOM4_LSB 0x4 #define GC_PINMUX_EXITINV0_DIOM4_MASK 0x10 #define GC_PINMUX_EXITINV0_DIOM4_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOM4_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOM4_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOM4_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA0_LSB 0x5 #define GC_PINMUX_EXITINV0_DIOA0_MASK 0x20 #define GC_PINMUX_EXITINV0_DIOA0_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA0_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA0_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA1_LSB 0x6 #define GC_PINMUX_EXITINV0_DIOA1_MASK 0x40 #define GC_PINMUX_EXITINV0_DIOA1_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA1_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA1_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA2_LSB 0x7 #define GC_PINMUX_EXITINV0_DIOA2_MASK 0x80 #define GC_PINMUX_EXITINV0_DIOA2_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA2_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA2_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA2_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA3_LSB 0x8 #define GC_PINMUX_EXITINV0_DIOA3_MASK 0x100 #define GC_PINMUX_EXITINV0_DIOA3_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA3_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA3_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA3_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA4_LSB 0x9 #define GC_PINMUX_EXITINV0_DIOA4_MASK 0x200 #define GC_PINMUX_EXITINV0_DIOA4_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA4_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA4_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA4_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA5_LSB 0xa #define GC_PINMUX_EXITINV0_DIOA5_MASK 0x400 #define GC_PINMUX_EXITINV0_DIOA5_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA5_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA5_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA5_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA6_LSB 0xb #define GC_PINMUX_EXITINV0_DIOA6_MASK 0x800 #define GC_PINMUX_EXITINV0_DIOA6_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA6_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA6_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA6_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA7_LSB 0xc #define GC_PINMUX_EXITINV0_DIOA7_MASK 0x1000 #define GC_PINMUX_EXITINV0_DIOA7_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA7_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA7_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA7_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA8_LSB 0xd #define GC_PINMUX_EXITINV0_DIOA8_MASK 0x2000 #define GC_PINMUX_EXITINV0_DIOA8_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA8_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA8_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA8_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA9_LSB 0xe #define GC_PINMUX_EXITINV0_DIOA9_MASK 0x4000 #define GC_PINMUX_EXITINV0_DIOA9_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA9_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA9_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA9_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA10_LSB 0xf #define GC_PINMUX_EXITINV0_DIOA10_MASK 0x8000 #define GC_PINMUX_EXITINV0_DIOA10_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA10_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA10_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA10_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA11_LSB 0x10 #define GC_PINMUX_EXITINV0_DIOA11_MASK 0x10000 #define GC_PINMUX_EXITINV0_DIOA11_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA11_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA11_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA11_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA12_LSB 0x11 #define GC_PINMUX_EXITINV0_DIOA12_MASK 0x20000 #define GC_PINMUX_EXITINV0_DIOA12_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA12_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA12_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA12_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA13_LSB 0x12 #define GC_PINMUX_EXITINV0_DIOA13_MASK 0x40000 #define GC_PINMUX_EXITINV0_DIOA13_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA13_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA13_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA13_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOA14_LSB 0x13 #define GC_PINMUX_EXITINV0_DIOA14_MASK 0x80000 #define GC_PINMUX_EXITINV0_DIOA14_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOA14_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOA14_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOA14_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOB0_LSB 0x14 #define GC_PINMUX_EXITINV0_DIOB0_MASK 0x100000 #define GC_PINMUX_EXITINV0_DIOB0_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB0_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOB0_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOB1_LSB 0x15 #define GC_PINMUX_EXITINV0_DIOB1_MASK 0x200000 #define GC_PINMUX_EXITINV0_DIOB1_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB1_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOB1_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOB2_LSB 0x16 #define GC_PINMUX_EXITINV0_DIOB2_MASK 0x400000 #define GC_PINMUX_EXITINV0_DIOB2_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB2_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB2_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOB2_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOB3_LSB 0x17 #define GC_PINMUX_EXITINV0_DIOB3_MASK 0x800000 #define GC_PINMUX_EXITINV0_DIOB3_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB3_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB3_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOB3_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOB4_LSB 0x18 #define GC_PINMUX_EXITINV0_DIOB4_MASK 0x1000000 #define GC_PINMUX_EXITINV0_DIOB4_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB4_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB4_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOB4_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOB5_LSB 0x19 #define GC_PINMUX_EXITINV0_DIOB5_MASK 0x2000000 #define GC_PINMUX_EXITINV0_DIOB5_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB5_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB5_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOB5_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOB6_LSB 0x1a #define GC_PINMUX_EXITINV0_DIOB6_MASK 0x4000000 #define GC_PINMUX_EXITINV0_DIOB6_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB6_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB6_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOB6_OFFSET 0x244 #define GC_PINMUX_EXITINV0_DIOB7_LSB 0x1b #define GC_PINMUX_EXITINV0_DIOB7_MASK 0x8000000 #define GC_PINMUX_EXITINV0_DIOB7_SIZE 0x1 #define GC_PINMUX_EXITINV0_DIOB7_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_DIOB7_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_DIOB7_OFFSET 0x244 #define GC_PINMUX_EXITINV0_SWDPTRACE_LSB 0x1c #define GC_PINMUX_EXITINV0_SWDPTRACE_MASK 0x10000000 #define GC_PINMUX_EXITINV0_SWDPTRACE_SIZE 0x1 #define GC_PINMUX_EXITINV0_SWDPTRACE_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_SWDPTRACE_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_SWDPTRACE_OFFSET 0x244 #define GC_PINMUX_EXITINV0_SWDPDATA_LSB 0x1d #define GC_PINMUX_EXITINV0_SWDPDATA_MASK 0x20000000 #define GC_PINMUX_EXITINV0_SWDPDATA_SIZE 0x1 #define GC_PINMUX_EXITINV0_SWDPDATA_DEFAULT 0x0 -#define GC_PINMUX_EXITINV0_SWDPDATA_OFFSET 0x248 +#define GC_PINMUX_EXITINV0_SWDPDATA_OFFSET 0x244 #define GC_PINMUX_EXITINV1_VIO0_LSB 0x3 #define GC_PINMUX_EXITINV1_VIO0_MASK 0x8 #define GC_PINMUX_EXITINV1_VIO0_SIZE 0x1 #define GC_PINMUX_EXITINV1_VIO0_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_VIO0_OFFSET 0x24c +#define GC_PINMUX_EXITINV1_VIO0_OFFSET 0x248 #define GC_PINMUX_EXITINV1_VIO1_LSB 0x4 #define GC_PINMUX_EXITINV1_VIO1_MASK 0x10 #define GC_PINMUX_EXITINV1_VIO1_SIZE 0x1 #define GC_PINMUX_EXITINV1_VIO1_DEFAULT 0x0 -#define GC_PINMUX_EXITINV1_VIO1_OFFSET 0x24c +#define GC_PINMUX_EXITINV1_VIO1_OFFSET 0x248 #define GC_PMU_RESET_PORESETB1_LSB 0x0 #define GC_PMU_RESET_PORESETB1_MASK 0x1 #define GC_PMU_RESET_PORESETB1_SIZE 0x1 @@ -15413,37 +15633,37 @@ #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_MASK 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_OFFSET 0x110 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG0_OFFSET 0x114 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_LSB 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_MASK 0x2 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_OFFSET 0x110 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG1_OFFSET 0x114 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_LSB 0x2 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_MASK 0x4 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_OFFSET 0x110 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG2_OFFSET 0x114 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_LSB 0x3 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_MASK 0x8 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_SIZE 0x1 #define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_DEFAULT 0x0 -#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_OFFSET 0x110 +#define GC_PMU_LONG_LIFE_SCRATCH_WR_EN_REG3_OFFSET 0x114 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_LSB 0x0 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_MASK 0x1 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_SIZE 0x1 #define GC_PMU_INT_ENABLE_INTR_WAKEUP_DEFAULT 0x0 -#define GC_PMU_INT_ENABLE_INTR_WAKEUP_OFFSET 0x124 +#define GC_PMU_INT_ENABLE_INTR_WAKEUP_OFFSET 0x128 #define GC_PMU_INT_STATE_INTR_WAKEUP_LSB 0x0 #define GC_PMU_INT_STATE_INTR_WAKEUP_MASK 0x1 #define GC_PMU_INT_STATE_INTR_WAKEUP_SIZE 0x1 #define GC_PMU_INT_STATE_INTR_WAKEUP_DEFAULT 0x0 -#define GC_PMU_INT_STATE_INTR_WAKEUP_OFFSET 0x128 +#define GC_PMU_INT_STATE_INTR_WAKEUP_OFFSET 0x12c #define GC_PMU_INT_TEST_INTR_WAKEUP_LSB 0x0 #define GC_PMU_INT_TEST_INTR_WAKEUP_MASK 0x1 #define GC_PMU_INT_TEST_INTR_WAKEUP_SIZE 0x1 #define GC_PMU_INT_TEST_INTR_WAKEUP_DEFAULT 0x0 -#define GC_PMU_INT_TEST_INTR_WAKEUP_OFFSET 0x12c +#define GC_PMU_INT_TEST_INTR_WAKEUP_OFFSET 0x130 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_LSB 0x0 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_MASK 0x1 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_PAD_ENB_SIZE 0x1 @@ -15454,11 +15674,6 @@ #define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_SIZE 0x1 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_DEFAULT 0x1 #define GC_PMU_ANTEST_TOP_CTRL_ATEST_CLAMP_EN_OFFSET 0x1008 -#define GC_PMU_ANTEST_XO_LDO_EN_LSB 0x0 -#define GC_PMU_ANTEST_XO_LDO_EN_MASK 0x1 -#define GC_PMU_ANTEST_XO_LDO_EN_SIZE 0x1 -#define GC_PMU_ANTEST_XO_LDO_EN_DEFAULT 0x0 -#define GC_PMU_ANTEST_XO_LDO_EN_OFFSET 0x101c #define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_LSB 0x0 #define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_MASK 0xf #define GC_PMU_TESTBUS_CTRL_TEST_MUX_CTRL_SIZE 0x4 @@ -25122,43 +25337,43 @@ #define GC_VOLT_VERSION_CHANGE_LSB 0x0 #define GC_VOLT_VERSION_CHANGE_MASK 0xffffff #define GC_VOLT_VERSION_CHANGE_SIZE 0x18 -#define GC_VOLT_VERSION_CHANGE_DEFAULT 0x11f6d +#define GC_VOLT_VERSION_CHANGE_DEFAULT 0x121be #define GC_VOLT_VERSION_CHANGE_OFFSET 0x0 #define GC_VOLT_VERSION_REVISION_LSB 0x18 #define GC_VOLT_VERSION_REVISION_MASK 0xff000000 #define GC_VOLT_VERSION_REVISION_SIZE 0x8 -#define GC_VOLT_VERSION_REVISION_DEFAULT 0x4 +#define GC_VOLT_VERSION_REVISION_DEFAULT 0x5 #define GC_VOLT_VERSION_REVISION_OFFSET 0x0 -#define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_LSB 0x0 -#define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_MASK 0x1 -#define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_SIZE 0x1 -#define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_DEFAULT 0x0 -#define GC_VOLT_ANALOG_CONTROL_RSTB_VSEN_OFFSET 0x4 +#define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_LSB 0x0 +#define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_MASK 0x1 +#define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_SIZE 0x1 +#define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_DEFAULT 0x0 +#define GC_VOLT_ANALOG_CONTROL_VSEN_RSTB_OFFSET 0x8 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_LSB 0x1 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_MASK 0x3e #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_SIZE 0x5 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_DEFAULT 0xb -#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_OFFSET 0x4 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_NEG_OFFSET 0x8 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_LSB 0x6 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_MASK 0x1c0 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_SIZE 0x3 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_DEFAULT 0x4 -#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_OFFSET 0x4 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_INPUTDC_POS_OFFSET 0x8 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_LSB 0x9 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_MASK 0xe00 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_SIZE 0x3 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_DEFAULT 0x4 -#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_OFFSET 0x4 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_NEG_OFFSET 0x8 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_LSB 0xc #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_MASK 0x1f000 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_SIZE 0x5 #define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_DEFAULT 0xb -#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_OFFSET 0x4 +#define GC_VOLT_ANALOG_CONTROL_SEL_VSEN_TH_POS_OFFSET 0x8 #define GC_VOLT_CONFIG_SERIAL_TEST_EN_LSB 0x0 #define GC_VOLT_CONFIG_SERIAL_TEST_EN_MASK 0x1 #define GC_VOLT_CONFIG_SERIAL_TEST_EN_SIZE 0x1 #define GC_VOLT_CONFIG_SERIAL_TEST_EN_DEFAULT 0x0 -#define GC_VOLT_CONFIG_SERIAL_TEST_EN_OFFSET 0x8 +#define GC_VOLT_CONFIG_SERIAL_TEST_EN_OFFSET 0xc #define GC_WATCHDOG_WDOGCONTROL_INTEN_LSB 0x0 #define GC_WATCHDOG_WDOGCONTROL_INTEN_MASK 0x1 #define GC_WATCHDOG_WDOGCONTROL_INTEN_SIZE 0x1 @@ -25182,12 +25397,12 @@ #define GC_XO_VERSION_CHANGE_LSB 0x0 #define GC_XO_VERSION_CHANGE_MASK 0xffffff #define GC_XO_VERSION_CHANGE_SIZE 0x18 -#define GC_XO_VERSION_CHANGE_DEFAULT 0x11e43 +#define GC_XO_VERSION_CHANGE_DEFAULT 0x121be #define GC_XO_VERSION_CHANGE_OFFSET 0x0 #define GC_XO_VERSION_REVISION_LSB 0x18 #define GC_XO_VERSION_REVISION_MASK 0xff000000 #define GC_XO_VERSION_REVISION_SIZE 0x8 -#define GC_XO_VERSION_REVISION_DEFAULT 0x15 +#define GC_XO_VERSION_REVISION_DEFAULT 0x16 #define GC_XO_VERSION_REVISION_OFFSET 0x0 #define GC_XO_CLK_JTR_CTRL_HS_SEL_LSB 0x0 #define GC_XO_CLK_JTR_CTRL_HS_SEL_MASK 0x1 @@ -25984,161 +26199,146 @@ #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_SIZE 0x5 #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_DEFAULT 0xd #define GC_XO_OSC_XTL_FSM_CFG_SENSE_REG_MAX_OFFSET 0x1fc -#define GC_XO_OSC_SETHOLD_XTL_LSB 0x0 -#define GC_XO_OSC_SETHOLD_XTL_MASK 0x1 -#define GC_XO_OSC_SETHOLD_XTL_SIZE 0x1 -#define GC_XO_OSC_SETHOLD_XTL_DEFAULT 0x0 -#define GC_XO_OSC_SETHOLD_XTL_OFFSET 0x200 -#define GC_XO_OSC_SETHOLD_ANA_LSB 0x1 -#define GC_XO_OSC_SETHOLD_ANA_MASK 0x2 -#define GC_XO_OSC_SETHOLD_ANA_SIZE 0x1 -#define GC_XO_OSC_SETHOLD_ANA_DEFAULT 0x0 -#define GC_XO_OSC_SETHOLD_ANA_OFFSET 0x200 -#define GC_XO_OSC_CLRHOLD_XTL_LSB 0x0 -#define GC_XO_OSC_CLRHOLD_XTL_MASK 0x1 -#define GC_XO_OSC_CLRHOLD_XTL_SIZE 0x1 -#define GC_XO_OSC_CLRHOLD_XTL_DEFAULT 0x0 -#define GC_XO_OSC_CLRHOLD_XTL_OFFSET 0x204 -#define GC_XO_OSC_CLRHOLD_ANA_LSB 0x1 -#define GC_XO_OSC_CLRHOLD_ANA_MASK 0x2 -#define GC_XO_OSC_CLRHOLD_ANA_SIZE 0x1 -#define GC_XO_OSC_CLRHOLD_ANA_DEFAULT 0x0 -#define GC_XO_OSC_CLRHOLD_ANA_OFFSET 0x204 #define GC_XO_OSC_TEST_CLK2X_EN_LSB 0x0 #define GC_XO_OSC_TEST_CLK2X_EN_MASK 0x1 #define GC_XO_OSC_TEST_CLK2X_EN_SIZE 0x1 #define GC_XO_OSC_TEST_CLK2X_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_CLK2X_EN_OFFSET 0x208 +#define GC_XO_OSC_TEST_CLK2X_EN_OFFSET 0x200 #define GC_XO_OSC_TEST_CLK_JTR_EN_LSB 0x1 #define GC_XO_OSC_TEST_CLK_JTR_EN_MASK 0x2 #define GC_XO_OSC_TEST_CLK_JTR_EN_SIZE 0x1 #define GC_XO_OSC_TEST_CLK_JTR_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_CLK_JTR_EN_OFFSET 0x208 +#define GC_XO_OSC_TEST_CLK_JTR_EN_OFFSET 0x200 #define GC_XO_OSC_TEST_CLK_TIMER_EN_LSB 0x2 #define GC_XO_OSC_TEST_CLK_TIMER_EN_MASK 0x4 #define GC_XO_OSC_TEST_CLK_TIMER_EN_SIZE 0x1 #define GC_XO_OSC_TEST_CLK_TIMER_EN_DEFAULT 0x0 -#define GC_XO_OSC_TEST_CLK_TIMER_EN_OFFSET 0x208 +#define GC_XO_OSC_TEST_CLK_TIMER_EN_OFFSET 0x200 +#define GC_XO_ANTEST_CTRL_LDO_EN_LSB 0x0 +#define GC_XO_ANTEST_CTRL_LDO_EN_MASK 0x1 +#define GC_XO_ANTEST_CTRL_LDO_EN_SIZE 0x1 +#define GC_XO_ANTEST_CTRL_LDO_EN_DEFAULT 0x0 +#define GC_XO_ANTEST_CTRL_LDO_EN_OFFSET 0x204 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_LSB 0x0 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_MASK 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_OFFSET 0x20c +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_OVERFLOW_OFFSET 0x208 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_LSB 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_MASK 0x2 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_OFFSET 0x20c +#define GC_XO_DXO_INT_ENABLE_FAST_CALIB_UNDERRUN_OFFSET 0x208 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_LSB 0x2 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_MASK 0x4 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_OFFSET 0x20c +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_OVERFLOW_OFFSET 0x208 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_LSB 0x3 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_MASK 0x8 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_OFFSET 0x20c +#define GC_XO_DXO_INT_ENABLE_SLOW_CALIB_UNDERRUN_OFFSET 0x208 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_LSB 0x4 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_MASK 0x10 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_OFFSET 0x20c +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_NOP_SEEN_OFFSET 0x208 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_LSB 0x5 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_MASK 0x20 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_OFFSET 0x20c +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_NOP_SEEN_OFFSET 0x208 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_LSB 0x6 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_MASK 0x40 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x20c +#define GC_XO_DXO_INT_ENABLE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x208 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x20c +#define GC_XO_DXO_INT_ENABLE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x208 #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_LSB 0x0 #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_MASK 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_OFFSET 0x210 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_OVERFLOW_OFFSET 0x20c #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_LSB 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_MASK 0x2 #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_OFFSET 0x210 +#define GC_XO_DXO_INT_STATE_FAST_CALIB_UNDERRUN_OFFSET 0x20c #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_LSB 0x2 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_MASK 0x4 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_OFFSET 0x210 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_OVERFLOW_OFFSET 0x20c #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_LSB 0x3 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_MASK 0x8 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_OFFSET 0x210 +#define GC_XO_DXO_INT_STATE_SLOW_CALIB_UNDERRUN_OFFSET 0x20c #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_LSB 0x4 #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_MASK 0x10 #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_OFFSET 0x210 +#define GC_XO_DXO_INT_STATE_CLK_JTR_NOP_SEEN_OFFSET 0x20c #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_LSB 0x5 #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_MASK 0x20 #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_OFFSET 0x210 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_NOP_SEEN_OFFSET 0x20c #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_LSB 0x6 #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_MASK 0x40 #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x210 +#define GC_XO_DXO_INT_STATE_CLK_JTR_SW_TRIM_DONE_OFFSET 0x20c #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x210 +#define GC_XO_DXO_INT_STATE_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x20c #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_LSB 0x0 #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_MASK 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_OFFSET 0x214 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_OVERFLOW_OFFSET 0x210 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_LSB 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_MASK 0x2 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_OFFSET 0x214 +#define GC_XO_DXO_INT_TEST_FAST_CALIB_UNDERRUN_OFFSET 0x210 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_LSB 0x2 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_MASK 0x4 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_SIZE 0x1 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_OFFSET 0x214 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_OVERFLOW_OFFSET 0x210 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_LSB 0x3 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_MASK 0x8 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_OFFSET 0x214 +#define GC_XO_DXO_INT_TEST_SLOW_CALIB_UNDERRUN_OFFSET 0x210 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_LSB 0x4 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_MASK 0x10 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_OFFSET 0x214 +#define GC_XO_DXO_INT_TEST_CLK_JTR_NOP_SEEN_OFFSET 0x210 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_LSB 0x5 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_MASK 0x20 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_OFFSET 0x214 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_NOP_SEEN_OFFSET 0x210 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_LSB 0x6 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_MASK 0x40 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_OFFSET 0x214 +#define GC_XO_DXO_INT_TEST_CLK_JTR_SW_TRIM_DONE_OFFSET 0x210 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_LSB 0x7 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_MASK 0x80 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_SIZE 0x1 #define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_DEFAULT 0x0 -#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x214 +#define GC_XO_DXO_INT_TEST_CLK_TIMER_SW_TRIM_DONE_OFFSET 0x210 #define GC_M3_ITM_TCR_ITMENA_LSB 0x0 #define GC_M3_ITM_TCR_ITMENA_MASK 0x1 #define GC_M3_ITM_TCR_ITMENA_SIZE 0x1 @@ -26775,11 +26975,12 @@ -1 #endif /* GC__ENABLE_FLASH_DFT_DEFINITIONS__ */ +#define GC_CONST_FPGA_JITTER_FIXED_FREQ 0xf #define GC_CONST_FSH_PE_CONTROL_BULKERASE 0x1d1e2bad #define GC_CONST_FSH_PE_EN 0xb11924e1 #define GC_CONST_FSH_PE_CONTROL_PROGRAM 0x27182818 #define GC_CONST_FSH_PE_CONTROL_ERASE 0x31415927 #define GC_CONST_FSH_PE_CONTROL_READ 0x16021765 +#define GC_CONST_FPGA_TIMER_FIXED_FREQ 0x18 #define GC_CONST_FSH_OVRD_UNLOCK 0x13806488 - #endif /* __EC_CHIP_G_CR50_FPGA_REGDEFS_H */ diff --git a/util/signer/codesigner.cc b/util/signer/codesigner.cc index cf3513d773..590463b1ce 100644 --- a/util/signer/codesigner.cc +++ b/util/signer/codesigner.cc @@ -13,7 +13,9 @@ #include <common/image.h> #include <common/publickey.h> #include <common/signed_header.h> -//#include <rapidjson/document.h> +#ifdef HAVE_JSON +#include <rapidjson/document.h> +#endif #include <string> #include <map> @@ -195,7 +197,7 @@ bool readJSON(const string& filename, uint32_t* p4cl, map<string, uint32_t>* fusemap) { bool result = false; -#if 0 +#ifdef HAVE_JSON ifstream ifs(filename.c_str()); if (ifs) { @@ -235,7 +237,7 @@ bool readJSON(const string& filename, result = true; } } -#endif +#endif // HAVE_JSON return result; } @@ -253,7 +255,7 @@ void usage(int argc, char* argv[]) { "--key=$pem-filename\n" "[--xml=$xml-filename] typically 'havenTop.xml'\n" "[--json=$json-filename] the signing manifest\n" - "[--format=bin|hex] output file format, hex is default\n", + "[--format=bin|hex] output file format, hex is default\n", argv[0]); } @@ -272,7 +274,7 @@ int getOptions(int argc, char* argv[]) { int c, option_index = 0; outputFormat.assign("hex"); while ((c = getopt_long(argc, argv, "i:o:k:x:j:f:h", - long_options, &option_index)) != -1) { + long_options, &option_index)) != -1) { switch (c) { case 0: fprintf(stderr, "option %s", long_options[option_index].name); diff --git a/util/signer/common/publickey.h b/util/signer/common/publickey.h index 6a899be9ac..66a585ab0a 100644 --- a/util/signer/common/publickey.h +++ b/util/signer/common/publickey.h @@ -21,8 +21,8 @@ class PublicKey { bool ok(); // # of words for R. - // Currently set at 3104 bits (97*32). - size_t rwords() const { return 96 + 1; } + // Currently 96 (enough for upto 3071 moduli). + size_t rwords() const { return 96; } // # of significant words in modulus. size_t nwords(); @@ -33,7 +33,7 @@ class PublicKey { uint32_t n0inv(); // PKCS1.5 SHA256 - // Mongomery factor 2**(32*rwords()) multiplied in. + // Montgomery factor 2**(32*rwords()) multiplied in. int sign(const void* msg, size_t msglen, BIGNUM** output); // PKCS1_OAEP SHA-1, MGF1 diff --git a/util/signer/common/signed_header.h b/util/signer/common/signed_header.h index d04f1ac088..b6929522d9 100644 --- a/util/signer/common/signed_header.h +++ b/util/signer/common/signed_header.h @@ -29,7 +29,7 @@ typedef struct SignedHeader { #endif // __cplusplus uint32_t magic; // -1 - uint32_t signature[96 + 1]; + uint32_t signature[96]; uint32_t tag[7]; uint32_t keyid; uint32_t image_size; @@ -38,7 +38,7 @@ typedef struct SignedHeader { uint32_t rx_base; uint32_t rx_max; uint32_t fusemap[FUSE_MAX / (8 * sizeof(uint32_t))]; - uint32_t _pad[256 - 1 - 97 - 7 - 6*1 - 5]; + uint32_t _pad[256 - 1 - 96 - 7 - 6*1 - 5]; } SignedHeader; #ifdef __cplusplus diff --git a/util/signer/image.cc b/util/signer/image.cc index 4b9db30608..397143bb7c 100644 --- a/util/signer/image.cc +++ b/util/signer/image.cc @@ -6,6 +6,7 @@ #include <stddef.h> #include <stdlib.h> +#include <stdio.h> #include <string.h> #include <unistd.h> #include <sys/types.h> diff --git a/util/signer/rom-testkey-A.pem b/util/signer/rom-testkey-A.pem index 926b6b0497..77a69d8448 100644 --- a/util/signer/rom-testkey-A.pem +++ b/util/signer/rom-testkey-A.pem @@ -1,364 +1,39 @@ -# output of: openssl genrsa -f4 3072 -#-----BEGIN RSA PRIVATE KEY----- -MIIG4wIBAAKCAYEAslAOYh0KsW6B3a1slmQLiKvnLaLwO21yVM/l1MG0jzrdepPZ -o134FrFI/dHscPSRlN1M/MzpfDdn+q6FIupprYdHYahbvDb+YpVfrQNYFiYhq1zL -a3QKHRtlD0GEugPuBTIJZcl3zSgGpD3Nh4658f02KhDHnKNJYa9eY1GM5Ij3sW9y -DH8lCV80X8BZjN8mmkmlMjBHCbOgPgxvK8M1e/gsPYgfcmC0EYsiWnohXQBhGY31 -lEaKeub3fQylj5HrT0pck21lmVVYpL9oWaa2ib3p+jJCruddQI6TNvZtY4FQQbiE -hJ1XXSPECuv532pE5tYlB3FHuVUfKio1p/FG8RIerlqAsBI9QTayJePkm/H1GItX -qFsXdT7OhMDYJhUjtlX43pDcoufGzwXYxn9J3po5hbpHfGoGPJJedd/aiybaJywN -D+KmWBn8upMvEmdCsyE9IWb8WJbaH7Yq4yz5ZJm4hrHPqKBaW1BPbqGOEdPiU0PQ -K3XpToiqhU7fXHmDAgMBAAECggGAYTuobDX7878Xz+LWuLd7Vp6upEMajr1iv/7S -DA9Iv2XRCht/bUc7llw8OjRzozCqBiwa5Ct1EohACgGKlfyPfdGrygP9agfu9aEQ -mA6fxQwsBf7G6iRPs4mRtRz8HFcyPuEHINsYmeW+oWcWIVph6SQzmgKmZrLfvAXe -CXiZxLEvqDDmVwwqDQ8+RwxjiJ7StQV9sH2E7zRlKBCtuoZrLtuofDEzPLKg3oQp -Sn8YnFctm7q+dIl20AgMYsM3sK9XYLIVBpT6JqGXnjoXS6lSO5zDw24kbqlip9N9 -KrYO2+VXrppmR9hOKm23BvHIcs9AdhYK6+msGqq95mMkiTEphrh+myQr6kNN9Vx3 -qxRvwfpxejZCSivM+S43Ow25rUF7RYRTHQ/k7ihpHrFzNIyYGtDWK6L6ac9V/YLc -ld7nog+EdxjV0JRAjBvxbjohv2q87SmR1LgD2ORkTtbPFGVY3vBKhfWxTGJh57o0 -5p/UqeIRAMCvRhmKsba55+K7vLbRAoHBAOYMVkIskxk0hVz/hPmqXOoStnH0Nx/B -AI0oZ65Eiii7sTWubepn4l6vE8olCdRp1vNoBgP5B+ByT84Ur1LK3tdhA/LdjcGE -+vAbXL7mKz+SpqQReRN8UByD+UPvhFtZ1cctyCRFHYzWwG/oTkx2afC3JvmNLG2o -ZMopdnCBaSITsld27hUcRftSU+b5B0naqnhXzDE0enyyoFhrC7RHFf1IImTWdiCr -dQFJaHeV9rnJCQC6q7x70aIbHJ5jaDZLKwKBwQDGbaC00zdhAUEVNNW3Tb/CtIaB -RePeMU46pqt1EpU2fJ1Og/1MobX9Y6o1o6l8aIbXaQrOSLhGz2Sb8E+qfYQhuqL5 -/aAgYQ8blevhf+RlVRLktvv/q1vEIUZE2AbtpSiQAgMHgrYq1opg9aB/Q/JsHU3f -L2P2Jtgpkqz5gLPAWJKbU4UMbNbxiFECOZl6RyZWuIOVKH7xsCriUCiF2hwUJmM4 -SLZRkR8S6/wR2lGnHx9NqrPu44Hy1Zz73ke8/wkCgcEAzS93yHIlibe0s+wcWOtB -EG48WItwl1v39+9v+pmbeRVfy/eWhhq+Z6FUz1oV2GXGmTfRFb4K7oBG+hKtBfV4 -qTYY5YgDJfZMM9jT8lktffh5taD4Ew8wDR8RNyztKuWHra4B84fKAZKR9b6IB98e -Qtu5YaAvXmdx7nbo8xQaB5D14tlrJV0gdjdKKps3iwIERm5Y7BJYpdxU9EgWGmfF -DzJFqxc2KZGEPO+SxAb4F2FeLE5TWzw9EI+KCSO1EagdAoHANanYWI723ykzrMSJ -N/Wy8rlX1wZLxf+XpI0Guba42+9/q4hOrLbfPRQDKFaGs7qhHQivf3JzQ9M65mFr -ajRf069h/DH3aEpXh6JYFLg90JndbjV+mXqCatyE4IF7/jE4cxnYL+PN2HAFJIvJ -SCHcIhkawk1Sv3Np6nRci22fL1nE7HT9+opE5zVykyN4unUbjUCBdYlqK3r1XhdH -nkuKZHitRL+FbzHMMZXYqgtdIdFs6dhMqUKmFkJnHkbTJ+3hAoHAdURnZVl1gduI -ISCleulBmSuCXVv3CNQ1tfBsc6J5KZcve/sbkk9eJrea0P5gcVI4lHkK8neW4I3q -tmImgTPNzAzjOf38KdV3pNFuYVN4bFOoguV7I0yZGqE7Tzr+TEz/6GmCYA/QVWSr -tp9Cg9xcGpsHZ6AdhTeFJHWCRhTS2FAgM8Q/lFLF78ng3Mc3tTMv66Sy+N+809d3 -f/NiifJqEqXpTGGSfC9sLqBDG58+tLahkd/4bPzDsXYIORJ6eRIp ------END RSA PRIVATE KEY----- -# output of: openssl genrsa -f4 2048 -#-----BEGIN RSA PRIVATE KEY----- -MIIEowIBAAKCAQEAxkF2U+bC+B6BCfzfM9p3g6J4HbMvdhV3xS1HJSpCdsqhQMkO -6l08LV1R4U7hjF1Nk/7C546XKDJegf9hhHuSZkYtXZOOBdYP8DV8ckrB3Lz6WF+N -54WJTPUaFFRN6ynedl6oRa7vdDW5cjOYGwIqkZg24uPAJKzmKYPkX8BV7d1rNF7+ -LkuDGCt9SzJON7459JMC/mAy1pFS99SPmkmH31OG+WQGq8puqdUdnzT50AUznHOS -5QJiMY1kTXp2iOkII+pzuPhpwjxtqIH4riJ/Rs8lHBNSL/MrK8jsGj0njWPLi0D5 -lSIFmznYn29WayUCnEvjTOAJaUBYwlQrh8eDbwIDAQABAoIBAGdyON/GhO0aXZJs -k7pmv/27hJlaqeUfhoMoAPtvdYaubD11q4a2Z3P0QYkis6Wd+aDDScexK0YaIh4K -t0N9hwI+k+VD3NNGwsI/5lNsloMrSCVclpq7nsy9B4KcCpwuGJoDAiJ6CQ/GCKGC -MlfFZZjap6jz1YpNfTskSsF7hlq6RceOXas4bx8YhZl4V+EkDez3nT6hHT9PUal9 -IN+wGV0xYShSUhRSp9qdm/a8WiyETxjPkh8p+5jVpJTb61XbkIzzSnsl+Xmukapk -fJO6Rcbp/V/78zV5YuR0hbENexPEf/R8iEuNxtVAz7G09U+8t1fTIuCFYy2oLh43 -rAwjHaECgYEA+Ba+UkzoNP0oFnMj4hJgE31NmnPWBMnjyGgchoPYQZVf+tjyCOj9 -bc0D1LQzG8UrkAxMnm4VWUniJ6CzaLHNPKiUvPeS+z1ofvsMup8ly23yL4q3QKOy -nfHQREW5wHHldvwc2uZ53bUInOEPUpQMA9UPFgbighx6WQVXyszAP4MCgYEAzJPo -zL+Ix1s/fwZOjfkFCnWsKcJ1m8t7vEObke4ovWaHP6JpHAumys1ih2F3qg0jKCa5 -yItv/l+Hj9fssYlR09zOmzAR0g8GGFqVgDxFyX0NrXmxcqYexVwNmd0scQKFwj2J -iazYOs1AMuQZ1MqYaw4wS2eG28/Y/F3OooVu3KUCgYEAqyr9+0imudCk9QBSFKu6 -8Bd3EIa1di5ZY685ZzHWZkGKrEc8jxs5p6VY7Eu8K3/Zc5SY1IJ9ZlKMn+zHfAeY -5C4oGUzzczbGPz41ZRli+T2NaHHbx9Rp64GowUIeTAIJYRPHUNzN3kMGgz7g1Ifi -1k4ND5SGeWDupTcDgJ/OUMMCgYBCK71rLLDDOuKI5bNW/KsCvRkY0MtVvzWgqYWS -aCRJTvaEQLYa2jHy+wfZnk8kc+dhP1VsZp2s+51Pi5oFutL64jr5u0yoUy+3hOVC -ezxfddGMwQYCfXUKhUHo+L89NoGpWFo6a+vs6SLQ0zL/vyAZ0JcSbMQUKWCYEIeb -zekT+QKBgCrI1XeYP0+PtKVVsE+0CmKSNhi2jKtCgyFCzHQJb2NHz25fZhlo7aM0 -oLgdsQFqK1+oALk8fT0Bg1jddsggbG7iZlieBTC5tPkNTMjpTcBBgnI5BkbZYuNi -qqbFnV0S2cP86BWzHXrtXWvmdesvMBRGxO7wG/ELXI10rHZG7DvH ------END RSA PRIVATE KEY----- -# output of: openssl genrsa -3 2048 -#-----BEGIN RSA PRIVATE KEY----- -MIIEowIBAAKCAQEA0/22CLHy3W8TJcHX/yMQOFIyARFxmlsz9wxilz9oCjEpDpld -GIsS0vXmv3U3hqgD0+ocFwKeYKe86JBTp0KsD6rmLvRwMfF1/n8eLsvXSWU7Z3hF -d6KFUvZ1t4G9WxFq5V2k7pumRhN2g2J0oVPrJpBlJKbOG7f0L6+IZT+V00CQrqUJ -kVxHBCxXosxkJPmoU8NBG+Nlv0OncIj2HrfnzAxmbPs/6uM/yeiTM462M/zqXu44 -l16K17uSGJ5/s6CCVK0AuDcO7nZ+T8gZRXrZw6Ib2t3VgqA38fyJLOZJ2Vc3t7KO -05fM5hNP18JzMpmpd1avhzHgDEer45qsAt1jaQIBAwKCAQEAjVPOsHah6PS3boE6 -qhdgJYwhVguhEZIipLLsZNTwBstwtGY+EFy3N06Z1PjPrxqtN/FoD1cUQG/TRbWN -GixytRyZdKL1dqD5VFS+yd06MO4nmlAuT8GuN075JQEo52Dx7j5t9GfELrekV5b4 -a41HbwruGG80EnqiynUFmNUOjNR/ETxMy4pzd8XH9RPEh9UfRQcrDsU7KOsQVygB -KaU4OhuJMeaU7K+75thaAIFTM5Cp7SUu54Ri8wXcnuvW3qAI4BM/KMnbPWktNHAg -6WkASh3oaY/J03wlfW0J3RBEpefW4dJ8sMq4qAXZ3ycgfJE5lTI8oJH3nX94cOla -FJ0bqwKBgQDvOOwWTw2xtoOYohKYw/vvIMMf8vx4AaG68Hc4cBsGJiFxuWJTT4nV -c67RuVUArObDMe/KgGMy5wqglyDgojXMVhRtOTMBP5tSaUsNViWKJJ/u+QyTFvu4 -q+o2/OuQkYy1WZ/U9rJvb6LcvOuNaffV0JShXJ4HnRLuO5irD60kWQKBgQDi296A -EP7oGgATERwklT4KS3Vgkr8VAEFT/VW78CUNTsGm6L8NOFHQe/U6eXe4ub0oSUan -u7TDhCgmkxvcw3qornu0wdVE0r1oF9TakTfPL9VQQ3mTrmpHCe7DZGJSTu7AC1b+ -07VIemesTBw1Dcf9RvazObjlAvWI/qP51ESVkQKBgQCfe0gO3152ea0QbAxl1/1K -Fddqof2lVmvR9aTQSryuxBZL0Ow3ilvjonSL0ONVyJnXdp/cVZd3RLHAZMCVwXky -5A2eJiIA1RI28NyzjsOxbb/0pghiD1J7HUbPU0e1tl3OO7/jTyGfn8HoffJeRqU5 -NbhrkxQFE2H0J7sctR4YOwKBgQCXPT8AC1SavAAMthLDDilcMk5AYdS4qtY3/jkn -9W4I3yvEmyoI0DaK/U4m+6Ul0SjFhi8afSMtAsVvDL0916cbHv0jK+ODNyjwD+M8 -YM/fdTjgLPu3yZwvW/SCQuw230nVXOSp4nja/EUdiBLOCS/+L08iJntDV05bVG1R -OC25CwKBgESVOTLIZfSkAP8GtolQt5meiQNZAM1fkbTZmydzPU8RcxYSjH4S7xzZ -wqMvedczh7eJ+CjUbYN+n3jj6Dual/36WHsPntV2avejb6UaInYd61t0murRuUsQ -jZ6CAlsBSbhfOru6N3NQ6tQC5+9hPELCTIPgMU3vLFq1cP2G0fTT ------END RSA PRIVATE KEY----- -# output of: openssl genrsa -3 3072 -----BEGIN RSA PRIVATE KEY----- -MIIG5AIBAAKCAYEAx96yZwMRZLE+n+aYXqtacPjhpsDAz2IYqbTTKMsYz6Ojvdjw -UWLd6OF0QuEuDrF6J8OK5c/RWRkltlIZgYv8FF8PznKSmz9frPCIKxm4mAu6nnw4 -FFbNBH5RnkKdctVfr8++RzOHjdD6b0WD80cAKxMknXfBCxw36+BNfArdU5ZIgHhh -db3dfL8HPBsrndUOhUWI1OcAY4UTmY6W2nW+tgE0T3nf8kcnUr+qGsw9nAU95Ulm -3Gir8EqL+cepnKDIR0TqIeE9eUeVOZGpNX098FJNpYM4NPAVIiTlexQyYMst+z4x -/WLYxTHfqtRl/BtvGgLqw81jqrhEXZuKL/4ZXawy2VCE5VqckTGd1s7froXI1F4L -wT42eNwL3LO3sBl/BqTk5Ib0azRQADr5Q35AiMUPHMZ/iPdkfHAuFWCAxE3VvQAg -QxqohLKTFjTIDjotHcEDaNCEonhtsz662wJALHALfWxPwAt3Fy8j+b24snpw8Hh+ -T19P1s4mdHnk3GcxAgEDAoIBgQCFPyGaAguYdim/7xA/HOb1+0EZ1dXflrsbzeIb -MhCKbRfT5fWLlz6bQPgslh60dlFv17HuiouQu255jBEBB/1i6gqJobcSKj/IoFrH -ZnsQB9G+/Xq4Od4C/uEULGj3OOp1NSmEzQUJNfxKLlf3hKrHYhho+oCyEs/ylYj9 -XJONDtsAUED5KT5TKgTSvMe+jgmuLls4mgBCWLe7tGSRo9R5ViLfppVML2+Mf8a8 -iCkSrilDhkSS8HKgMbKmhRu9wIRW5YC5ipbuOAxRfyLi0jAgyAxmh9s6P1xj014d -yyQqRASH5M+SaoOXjW3lLm7g40GEkSPP7rpuscU4kKZPEv5c6CKKS5rdkRdYYpGC -hbu4vuQ+WAc/1WadzBouNapr51KpFubLD4HHXw/hrhoxoLVmABzG5f3bbI5oE8PL -cRgGAEM/XTcQ7kMXWBgkzkUNN9UzV+zTegVsGp/gfjdC+mCK3QepqEoMvJYKOSgg -aUgKO9e2lQja8ryW3ypukJZQQqMCgcEA7VhsMaDhAq1nlhX5RaZrddeCcrQv9jR5 -VJruGCp/rQZaezFpwV1tU0Eqir6ZzaUQSdS5t4BCCuoTMZUtQjl1mG8GWwTIF3Pp -hdx0W81ISE5UUYO+mNnvJ0GeEJc9j8+782nxbhH5/W9zd8ixav9AgYOch5v5SUvQ -lohHo+E0FVu8PtMdN+oblWfqSgIBvfLVxZPAKMWreFhE5YCe5a19EC1bKhA/YgU8 -JRlS5bT2ZvlWCng3DenY3GZqpY3dLcaLAoHBANeUPNnwehFGGyk8+5ubiklOuJkD -P2dckTfM6jY4/HRezLQ1kOBlpg6ckEhQJd0hfIlUe1RnCfnDiVctY3coJjng+K7a -VIGNEAbBTzc4/dEZHiVWQkikLWToRobL+n5uxxWYmUXdt8K2RLXtII4N7+5BR2rR -iXaIvknKQMBVqKXxtJ8hMHHLKExGhJT9Xrxzl4spYALT0Qf4OP0AyRDdMkv3JNTf -oUrrWeLAFONq1jwnV1QgufkJXBgY/CkTJjY8swKBwQCeOvLLwJYByO+5Y/uDxEej -5QGhzXVOzaY4Z0llcapzWZGndkaA6POM1hxcfxEzw2AxOHvPqtax8WIhDh4sJk5l -n1mSAzAPopuukvg9M4WFiY2LrSm7O/TE1mlgZNO1NSf3m/ZJYVFTn6JP2yDx/4BW -V72vvVDbh+BkWtptQM1jkn1/N2jP8We47/GGrAEpTI6Dt9Vwg8elkC3uVb9DyP4K -yOdxYCpBWNLDZjdDzfmZ+46xpXoJRpCS7vHDs+jJLwcCgcEAj7gokUr8C4QSG339 -EmexhjR7EKzU75MLeoicJCX9oundzXkLQEPECb21hYrD6MD9sOL84u9b+9ew5Mjs -+hrEJpX7Hzw4Vl4KryuKJNCpNhC+w47W2xgeQ0WEWd1RqZ8vY7sQ2T56gc7YeUjA -XrP1SYDaRzZbpFsphobV1Y5wbqEjFMDK9odwMtmtuKjp0ve6XMZAAeKLWqV7U1Xb -YJN23U9t4z/A3Jzmlyq4l5yO0sTk4sB7+1uSurtSxgzEJCh3AoHBAJxAc/3qetap -JdjBT6CbS2Jh08aCwT4ld1jVToPx3ulUKn/7tVozyjb6I2FipAUrTLnGtQ8+vCQe -F4TWdjYDAy0Dq8HSQ9GTDyk13OwoKou6qr/IyDUE9AFfjyQeo7iUYbpKnUmJAawO -KhlwR6B8x3lFrtwPkbNuWgvOeq++8tamxb1Q56m9DPYNzECrGybe2o/+qDiZCG5n -P/L5lDq30HHN2pyUQacVoXYzrYITzNIVZFg2h28Wti0JKjlX0j64YQ== ------END RSA PRIVATE KEY----- -# output of: openssl genrsa -f4 3071 -#-----BEGIN RSA PRIVATE KEY----- -MIIG4QIBAAKCAYBYpZXTcInNbU4yo/0A31NnKszEvM8lvMGMUzV4vjOIpDQsmyvP -4pCB9Na41Al0iz6VcToioXkUr8SVnUVyytSzTdFhcIVkHak7P5H/DGtYLjQMGwoS -2cgIVQvjqAk+9UV1IaLzDnfnE0+mVx75WYwBZwzk0J1u5aJrKUfW/iqZ/TWJDjCw -bhR5Durq8GXtdwF3AOwrpjS5nTW9rFGRwjUxOfGa0lezCRyPL5pxmyN5eSCFaHN1 -amY2MaJxGwT9AeLOLhDZYMC/juUeoZKT8/3nJLGfhsrOxBsfDXwl1R8HlcC6g8x3 -tm5h8b1EBeTthRzemCMyEhJ4uPIjaOvwfIe7MgC2RTIZICqrIctSN1oOhasDvPII -ZkwDzovWnuHE/vCEr3Gts+hwLHjIErWEXGPs7AGTY+TvIIBGwGbGxUXBp/+px+v7 -3GGMosLTABp68VrXMKvtVxFp7Si41rvxSaPbh8LNYHOdJ1OYvNF4e9/FJG5KKA17 -xyMDF7VjPxtAJScCAwEAAQKCAYAsz5+aX9Q5NR0HemBF1Z7KkxcqCKvKTs2kStfH -7pYMZ708I0CVeNlF6Ge2zPDuqgj78F3L7cZQT73XR8Y4jhHRhe/nCsNTZa8LlUoP -HM8Sp2CGEhEYkGCO3bcB4Qqzebcfy94ccd7ov5lO49FziPG+L8KT1GURDyH4e8im -BJuydg5e9v5j4XGV9JWKJ/XOgY8LAjtgoUcb4T2uYPJm9T6AYOMiOVw908hNFWpE -LYFUQYfQCIn8+8kpchPEiz0NTKsjyC1Z6TaTdd5H1OhiW5NFy8AZhZMzjj/VFbHl -tjhKxh3A8SN4hmmBz7TYpyNa3YDQiTTsIiwVHwJylSkvBNM+UfMTiyVCI8c/JQXa -xD2ZAFqImIJMbIAJpQs9KfTLZElEZ0+kfi1vHhNegeyYIk4ukB1c6m1fDZvXEjhi -TKUMuNfwKu3LXBBd3D6iIJDzSSfglh7W5/rIreKuLPlSrwxFTJXXPJbeCdVhcAe7 -4kLOu/geWNvHjNuekk23opZqMNkCgcEAzHz5c9CMnv6dtZ2LrHvvmriAYiae7Weu -VXRdnE22dqRxvt/VkHlYteHMo9U7Vq0APybaYScy/jF0AGlvOk49cjyPO9C0mLAt -whoZ38IHaonXbsUK/AHD7sQu0NUB8aRAhxIUm1xwq69kLWwOuWZpyZB0Hh1UxebB -MZBtG0nNF/nk97qvWGz5C9TZeZuUWmdwSuWWLGSou3rHYPHKEukasGhrHrlvZi3c -ui+Fjphjxbu4jHftX2xbjnkT9Q1elM+DAoHAbvo81cyI/9mm/gtX1q1+U7mNRUaK -t6E3/dTAZDxaPVw4ZzTPkNryYyE0nbeq0V9T6W6RjxReBQ6d6DYRPuioJfHO7+La -ozHjR3jMdLTK6E85Ti14LzLFf4nXuVEoXhFPngnDQofrRCf/lsEOH2v4uZs2Ea3g -Nn5dxEoDUzZc31MGP7IF9w3cKr9lTRDj2ITSlmKggZGEkH2HLwzUYjf1slhC37HX -eeVS1aOcomcbZdw2SIaa9RJLizsDzOITPZ6NAoHBAMUItqQtkxGwbO4OfAMa+Giw -1qO8au5+NLEKixiMmQAAu8kbjIDFLAE1LSW/1IlT8STonwt15eCgbhHnhdE8imCE -kc8k7p8hQzYASGYeY174qqiFHGxulwh96E44sMLRbYu4lDqO+9GyEmjh8d4bHFun -4PsTcBewnP7RFxBwMDqmA0XgkAw4FFCeK17N1ki12rGQPv9PjnX3fB2hXQCTs6+/ -LVhRfVGLZ1/PYnVfyONCWjSfag3ELwQ9DknVNAlXWQKBwE4QvzySHYkEfUDVj9uW -vXd93g9uOORFh1KKFzAreDsTpSWMc7ptGfZ7hDyx13piuW9KdSAV7rFV/+Q6LFV5 -adcPS0dZ5/zGeh9rrT8ncliKakBBIfrplx5JQ7O7kE7jlIMSUQV7ARc3n8ZXVWzr -EdLWiOlUy5TpvWH3wnEFm70I9StXOnT4jfiQHF1i1TQY8t4Q0OF0ELFna/G/76KL -xMzI43nh6zZ3B5b6+ZMQPqifiJvp/BUK4pM1V04HdgtxfQKBwHTuWXLDgURgV4Xl -PKtNQeeJpOXWTxjGo9dktYsYD02IzUwO53LA01XBbxakX1VxqzDU6ZAS0Xvk/gbk -5okecnydIBckw/9T+sOvS4KaC/mVHNlFucrvY8b+0Pjb+9I+gqxT6eq0D5D4zjMW -eiJCb2Cpw1dGtwOMGUhH0lqJdLgqX23TzTLhzoaYt/1hf4bdeRR1ogcSFXo2Vz59 -eA8fRe4RflCJ8t4pGxAv0go7MFP79LZy/NF8sNHDXGp/d/f9uA== ------END RSA PRIVATE KEY----- -# output of: openssl genrsa -3 2047 -#-----BEGIN RSA PRIVATE KEY----- -MIIEoAIBAAKCAQBd5Az6u/daXYeCv3aHYGJ01Aw8NUu8YLoT9ynBDvm7hT5yWLbY -ugLSIN44gLSsgVjJ7g6n0LddheDaOC0YRPgyYcipg8/Lo8Doe8x8qerRz+PwewuP -k9mDmTPvHANJJJ7d7crlwv/OhklPEmDaSUrAVh5AmlUYNxRwbOC/Di3SLzJc/X7m -7ItclQouinH+dOiQGUZwyLGzE+TBB7io3NyV74yxHnmpwyxussNqKcfiN8C1dcIb -uqs/IEoR/TZ5EAcJI8XbSTe8SOVwWIEUcBBohzQWUWJbzwcc2CCijITrnsrO+/Cc -FD34krjss2nDtA2mZsq5b/IqmofziTyf+B9DAgEDAoIBAD6YCKcn+jw+WlcqTwTq -7E3istLOMn2V0WKkxoC0pn0DfvblzzsmrIwV6XsAeHMA5dv0CcU1z5OulebQHhAt -+sxBMHECiofCgJr9Mv3GnIvf7Ur8sl+35le7d/S9V4YYaelJMe6B/98EMN9hlebb -hyrkFCsRjhAkuErzQH9eyTbJRB/7Fqi5pU5WWz7nuhIrrYVMeTEqbEdvCNiLjfrv -ooH7Eq2tQEVDcf49bCRhzOSpaykRsw9UkcLjWFn2OSnWrDlVSB9mbdGNJpBHLThf -WMuac2OxxbCl89bAFQ/oVjAqxLFzn46C7JZvLe/p8cHsYqbsRC21abbVDuAhBYX7 -nQsCgYEA4amkQZxDK1JCEZ7CcvFiV7SgkWqOesjDObpDd9te7M6cjDDVQQf560NR -6Mp4nLe8yBc00maPpLeL+FvovYtDRbDb2yIhyH9WgRWC30vtCMY/GpgS4jOcr3e0 -K9TkTbZTIINvem56rPOVJpJX5yXoG8lQdg/61TdZYISjSE123ykCgYBqg2CbTZLo -FNFvsWxn8dEMk4X/PHqUfyodwfLr1RZ8BFpke8VYOeQWLgS4aR5303zX4KZjHiwr -4z9NLyMjLwq/Akf+ig3Kgp6qgmrd8/QCcOBsaLPXnzlp4wPVNcu17QuDQV8G19Uu -I1bNcnyX+uld4rPuZOT+YQGRHrRsCYfUiwKBgQCWcRgrvYIc4YFhFIGh9kGPzcBg -8bRR2yzRJtelPOnzNGhddeOAr/vyLOFF3FBoen3auiM27wptz7KlkpspB4Iudefn -bBaFqjmrY6yU3UiwhCoRurdBd73KT81yje2JJDdrAkpRnvxzTQ4ZtuVEw/AShjWk -Cqc4z5DrAxeFiPnqGwKBgEcCQGeJDJq4i5/LnZqhNghiWVTS/GL/cWkr90fjZFKt -kZhSg5AmmA7JWHrwvvqM/eVAbuy+yB1CKjN0whd0sdSsL/8Gs9xXFHGsRz6ioqxL -QEhFzTpqJkaXV+N5MnlIsleA6gSP43QXjzOhqGVR8OlBzUmYmKmWAQtpzZ1br+MH -AoGBAJAgNpv0p3hZly5oecTzIan03/nJ7HlhS9XsR6zyI3n/HPxEd4MW7nAMlend -FtuJ8u033ZtWDW8E9qn6jrIMzgZgWMyh4Az+xYdq+ZMT6c3q/Ujh50FSeFc8y1we -onrGgK3d/IXnGIUpUUIexw6mEx4eux1GHusgMA/bWRG/DQeQ ------END RSA PRIVATE KEY----- -# output of: openssl genrsa -3 3056 -#-----BEGIN RSA PRIVATE KEY----- -MIIG2QIBAAKCAX8Ar8CGVa4OF/9HRjyN8FMy5s+iwtxMRl/s26hzwS+CipEFU0UO -vtm4A9YyfwfoZigneQjBKccwW4dJA5P9pjCWP5rwph0IIWErBm+EDWu+ANkGzVIG -YfP3RM3PVmVqciTvpVn5UDyXfABsrDlt542T0fHMz/RFZpZigmSg03tLqxjr36Ua -s8ObXh38PQSPiB8AoTXuADfVGHgGbMj2J2oXugXjPfpIsv58DnSYRtcwA2giR443 -ymjU3C4MlczUA5FhMNq5HC58tRRYqHExD2CrpKkyY0Zr0Is7VuAh9ttMHXgLAcfb -iKY2bumfZEq3p5ZTtBJxtYALOhwBGGX3Bigt5qRIQMWr9ThsScREMMbmuOvwyDtb -Aw1SyWf0SanqOvR/rh6kfy+b3Ta2jjtnULr+1Q6S7xhEgfko2YzSWHp7GMRZoryW -61P6hBvi/YcCkK6+elY5l/gxbtovSFaxV8ftfmIfw7VkcZ7woHD0YgJSK42m4W6b -eZmQDffPQeO3BwIBAwKCAX51KwQ5HrQP/4TZfbP1jMyZ38HXPYgu6p3nxaKAylcH -C1jiLgnUkSVX5CGqBUWZcBpQsIDGhMrnr4YCYqkZdbl/vKBuvgVrlhyu9QKznSlV -5gSI4VmWoqTYiTTkQ5xMGJ/DkVDgKGT9VZ3IJklFCQ02oTM1TYOZuZcBmGs3p4fH -ZfKVGLx317zpaVLTWF+wFKsWI/QAJTi6+q7zMKQaRrp8A+zT/DB3VFK0TbrZ5Mqs -8BbaXs/cReM9dAhj3eKtCnqe2xu3XvOx1grDXU92LHYQvQEquuwGKwzMX22srm6b -4MFXt0FMlcYvORNM/rsZccCVKPma66ORWVIQPDWTs1E/zsszf9PjWaCu4d9IjSeu -xEm+Vi2otqaLu2jAIxWa6vRgdKP3JZDJY4DY2Z53evjYECM17iHFFkoAxyhVX0YX -BR6kDBnfoP0gJ7Gi2C2PKgDT7hE7edaVc9gL03ElC9MthefgVjaj5L03sCO5EYw1 -0kOkVna9F0cHel1jaLw7AoHAAONtv0urcAltq467PkigEBSmIbTTWAUJhMkTjrPr -bxxZPEjYPek7sMg3PipB8kwE2RQuSZE26IgySh5xmRfweA+8IUO6o4JolzSiq88O -VE2rxWVh6wZp5P6IK0+Lv1JPgo/VK8s7wNa90DJ6u2nccRei4rK6o2ONg6NMcYcR -xUoucICLn3fw+DXvfdtSb5HLRmMCQoxeJZFzPb+acXzx+bXgGKJBYeCll6Letj0a -ZH5E7WjhYnw/I5UajCwPHE6DAoHAAMXU0sPdsAW8p7nIJvE+DeXla/vP1gS9xd8Q -wkmIZonaaqAl9xBaFMTw1dgu2lL8kp6mC2oWNg2ty+eOco64IyRKzNO44mu3msag -xaY1nt2HABzIzxAcFlpvo4edtfeDEYFIQ+NQtmvxUULOOY/BEXHuE6tjj65M1BaL -8I7GpkfHzCshCvgq6kjkYn020yxuqVo6LpNgm94bbqucKAquPHraAKGx0jHWMDHu -MoGyA4GV5NiJim0e0xBoNBcdqk4tAoHAAJeef4fHoAZJHQnSKYXACrhuwSM3kANb -rdtiXyKc9L2Q0ts60/DSddrPfsbWoYgDO2LJhmDPRbAhhr72Zg/1pV/SwNfRwlbw -ZM3Bx99e4t5yg5jr8gRGmKmwHN+yf4w1AbU4x9zSgI8pNXb8fPE9oLpslyHRwkJe -V8Iy9loL2Nwe9asHv6VLUCP0/pI29Qvc2ZdW1wg+w7ZM09URoP32pnlAEGwrlpXD -umyUeX4RmFQt85tA7FLUwmNnCB1faDRXAoHAAIPjNy0+dVkob9EwGfYpXplDnVKK -jq3T2T9ggYZa7waRnGrD+grmuINLOTrJ5uH9txRuska5eV5z3UUJobR6whgx3eJ7 -QZ0lEdnAg8Qjvz5aABMwigq9ZDxKbQUTzqUCC6uFgpeLJEf2NiyJe7UrYPaet8eX -tR7d4rmyoF8vGYUv3XIWB1AcnDCYQajPN3L0cObRdGJAZ+lnnx0SxVx0KFHmqxZ2 -jCE5dXaezFZ2rQEOmJBbsZ4UjLWazWS+cYlzAoG/T36zP8ftMSTz22u1WQtLbv28 -q8epi7lvQnDz/C7fbFxsq23r9qyEkPFhsdoogagZ3kSr+70rggkgibZeocGjrjLQ -ugMp/IKggQyoS1fDCufNi6MErZSGqTefzx1u9MMkOI5S3GDoRnRJD8TOfTUnDUIq -+cxLBV+9IMUXaB3Oecx42hLTi/nksalOL9TidrJh3OBU482UWBq0df0nnXYoRFEU -rkWWpQP1FbWGQ257ZEQTbNK/jM06JeliUh39hak= ------END RSA PRIVATE KEY----- -# openssl genrsa -3 3071 -#-----BEGIN RSA PRIVATE KEY----- -MIIG3wIBAAKCAYBrgb1tmM0ykgoLVVw7mCEHv5fVbe2gKOc/csx/a+AgJkwI/Ktc -R1WLfhyWPRVMqxri9UyhVwQV7VWp0gSLBMXigr7E9WrBvNAIshexkhjO9KLsut9q -w8Sv7PlLVXkDXCrFFkmKYhADeiInNADqcAfMZ8DFeGCehKH8FUb+K+FB2RbHdILQ -/Mxritqq87rAqkbGYvm0QIsyCWqnjEWEdw5R6u98+tPotcMeu0l0iStRFhqyqOWT -ISLijETRSk5w8rdSGoAzsYuyUj4DWbNIYPJlj3c5Z4a7M6CKkLyiqTi1eNHOUCqc -KqpNay8HTzJZbq+MpTvF3Ssp3l+t41YsFt730lE6p2qjKwcJRptwTk/BsLhd0RLn -K6cUVhNbxcwKP1QQdEam8THWb+foa/+O3VAyM+YBA6iu+ElIVxfhChv4sAN+vkke -uDTJ4uSDCTus6NSFvmsQfAUmV+hSMZlogOrx8JkshNWWvwXovz1eVAJQflNpGkLl -5Sz2xw4xFReIn+sCAQMCggGAR6vTnmXeIbaxXOOS0mVrWn+6jklJFXCaKkyIVPKV -asQysKhyPYTjslQTDtNjiHIR7KOIa49YDp45G+FYXK3ZQax/Lfjx1n3gBcwPy7a7 -NKMXSHyU8dfYdUimMjj7V5LHLg7bsZa1V6bBb3gAnEqv3ZqAg6WVvwMWqA4vVB1A -1pC52k2si1My8lyRx00nKxwvLuymeCsHdrDxxQguWE9e4UdKU1HimyPXadIw+Fty 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