diff options
| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2015-07-29 15:51:06 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-10-13 16:58:27 -0700 |
| commit | 5eb9e8f850b99de0f096b8f9626ea79f1845510c (patch) | |
| tree | f0edd14af58858b53f81da77a9c8118d92d98b39 | |
| parent | 828b55a7358ad5ec8bc27552bfb280eb173dd453 (diff) | |
| download | chrome-ec-5eb9e8f850b99de0f096b8f9626ea79f1845510c.tar.gz | |
Kunimitsu: PMIC: Configure the discharge configuration registers
BUG=none
TEST=On reboot, V3P3A_DSW voltage level drops by 2 Volts.
BRANCH=none
Change-Id: I86335187bab7ba122f47a5529d1affcc71aec687
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/301110
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | board/kunimitsu/board.c | 42 |
1 files changed, 42 insertions, 0 deletions
diff --git a/board/kunimitsu/board.c b/board/kunimitsu/board.c index a9ddb53a73..a557d906f3 100644 --- a/board/kunimitsu/board.c +++ b/board/kunimitsu/board.c @@ -394,6 +394,48 @@ static void board_pmic_init(void) if (ret) goto pmic_error; + /* + * Discharge control 4 register configuration + * [7:6] : 00b Reserved + * [5:4] : 01b V3.3S discharge resistance (V6S), 100 Ohm + * [3:2] : 01b V18S discharge resistance (V8S), 100 Ohm + * [1:0] : 01b V100S discharge resistance (V11S), 100 Ohm + */ + ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT4, 0x15); + if (ret) + goto pmic_error; + + /* + * Discharge control 3 register configuration + * [7:6] : 01b V1.8U_2.5U discharge resistance (V9), 100 Ohm + * [5:4] : 01b V1.2U discharge resistance (V10), 100 Ohm + * [3:2] : 01b V100A discharge resistance (V11), 100 Ohm + * [1:0] : 01b V085A discharge resistance (V12), 100 Ohm + */ + ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT3, 0x55); + if (ret) + goto pmic_error; + + /* + * Discharge control 2 register configuration + * [7:6] : 01b V5ADS3 discharge resistance (V5), 100 Ohm + * [5:4] : 01b V33A_DSW discharge resistance (V6), 100 Ohm + * [3:2] : 01b V33PCH discharge resistance (V7), 100 Ohm + * [1:0] : 01b V18A discharge resistance (V8), 100 Ohm + */ + ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT2, 0x55); + if (ret) + goto pmic_error; + + /* + * Discharge control 1 register configuration + * [7:2] : 00b Reserved + * [1:0] : 01b VCCIO discharge resistance (V4), 100 Ohm + */ + ret = I2C_PMIC_WRITE(TPS650830_REG_DISCHCNT1, 0x01); + if (ret) + goto pmic_error; + CPRINTS("PMIC initialization done"); return; |