mec1322: Change the Port 80 task to a timer IRQ.

The port 80 task just polls every 1ms until disabled when the system
goes into suspend.  Therefore, this commit configures a 1ms timer
interrupt that will be used for the port 80 writes instead of using an
entire task.  This saves task stack space as well as context switches.

BUG=chrome-os-partner:46062
BUG=chrome-os-partner:46063
BRANCH=None
TEST=Flash GLaDOS and verify using the `port80' console comamnd that
there are bytes in the port80 history.
TEST=make -j buildall tests

Change-Id: I65b48217a638c1f6ae1ac86471f9a98e0ec4533a
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://chromium-review.googlesource.com/305591
Commit-Ready: Aseda Aboagye <aaboagye@chromium.org>
Tested-by: Aseda Aboagye <aaboagye@chromium.org>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>

10 files changed, 91 insertions, 14 deletions

diff --git a/board/chell/ec.tasklist b/board/chell/ec.tasklist
index ec413f8047..8ad79e0f3c 100644
--- a/board/chell/ec.tasklist
+++ b/board/chell/ec.tasklist
@@ -29,5 +29,4 @@
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(PORT80, port80_task, NULL, TASK_STACK_SIZE)
+	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/cyan/ec.tasklist b/board/cyan/ec.tasklist
index 6ef89e4074..2e7070a299 100644
--- a/board/cyan/ec.tasklist
+++ b/board/cyan/ec.tasklist
@@ -24,7 +24,6 @@
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, HOST_CMD_TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE) \
-	TASK_NOTEST(PORT80, port80_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
 
diff --git a/board/glados/ec.tasklist b/board/glados/ec.tasklist
index b8e334b52d..9d0445d2ad 100644
--- a/board/glados/ec.tasklist
+++ b/board/glados/ec.tasklist
@@ -30,5 +30,5 @@
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(PORT80, port80_task, NULL, TASK_STACK_SIZE)
+	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
+
diff --git a/board/glower/ec.tasklist b/board/glower/ec.tasklist
index 4067403bee..b199809ac9 100644
--- a/board/glower/ec.tasklist
+++ b/board/glower/ec.tasklist
@@ -23,6 +23,5 @@
 	TASK_NOTEST(KEYPROTO, keyboard_protocol_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(PORT80, port80_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE)
diff --git a/board/kunimitsu/ec.tasklist b/board/kunimitsu/ec.tasklist
index b8e334b52d..eadfe99022 100644
--- a/board/kunimitsu/ec.tasklist
+++ b/board/kunimitsu/ec.tasklist
@@ -30,5 +30,4 @@
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, LARGER_TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(PD_C0, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE) \
-	TASK_NOTEST(PORT80, port80_task, NULL, TASK_STACK_SIZE)
+	TASK_ALWAYS(PD_C1, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/board/strago/ec.tasklist b/board/strago/ec.tasklist
index 2e75973b9b..4f0691a26f 100644
--- a/board/strago/ec.tasklist
+++ b/board/strago/ec.tasklist
@@ -27,7 +27,6 @@
 	TASK_NOTEST(PDCMD, pd_command_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(CONSOLE, console_task, NULL, TASK_STACK_SIZE) \
-	TASK_NOTEST(PORT80, port80_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(POWERBTN, power_button_task, NULL, TASK_STACK_SIZE) \
 	TASK_NOTEST(KEYSCAN, keyboard_scan_task, NULL, TASK_STACK_SIZE) \
 	TASK_ALWAYS(PD, pd_task, NULL, LARGER_TASK_STACK_SIZE)
diff --git a/chip/mec1322/build.mk b/chip/mec1322/build.mk
index 064fb4879c..0f18cee24c 100644
--- a/chip/mec1322/build.mk
+++ b/chip/mec1322/build.mk
@@ -12,7 +12,7 @@ CORE:=cortex-m
 CFLAGS_CPU+=-march=armv7e-m -mcpu=cortex-m4
 
 # Required chip modules
-chip-y=clock.o gpio.o hwtimer.o system.o uart.o jtag.o
+chip-y=clock.o gpio.o hwtimer.o system.o uart.o jtag.o port80.o
 chip-$(CONFIG_ADC)+=adc.o
 chip-$(CONFIG_FANS)+=fan.o
 chip-$(CONFIG_FLASH)+=flash.o
diff --git a/chip/mec1322/lpc.c b/chip/mec1322/lpc.c
index c486f75e77..e5e86b4454 100644
--- a/chip/mec1322/lpc.c
+++ b/chip/mec1322/lpc.c
@@ -351,7 +351,6 @@ void emi_interrupt(void)
 }
 DECLARE_IRQ(MEC1322_IRQ_EMI, emi_interrupt, 1);
 
-#ifdef HAS_TASK_PORT80
 /*
  * Port80 POST code polling limitation:
  * - POST code 0xFF is ignored.
@@ -372,7 +371,6 @@ int port_80_read(void)
 
 	return data;
 }
-#endif
 
 void acpi_0_interrupt(void)
 {
diff --git a/chip/mec1322/port80.c b/chip/mec1322/port80.c
new file mode 100644
index 0000000000..674d52d6d0
--- /dev/null
+++ b/chip/mec1322/port80.c
@@ -0,0 +1,86 @@
+/* Copyright 2015 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Port 80 Timer Interrupt for MEC1322 */
+
+#include "common.h"
+#include "console.h"
+#include "hooks.h"
+#include "lpc.h"
+#include "port80.h"
+#include "registers.h"
+#include "task.h"
+
+void port_80_interrupt(void)
+{
+	int data;
+
+	if ((1 << 1) & MEC1322_INT_RESULT(23)) {
+		data = port_80_read();
+
+		if (data != PORT_80_IGNORE)
+			port_80_write(data);
+	}
+}
+DECLARE_IRQ(MEC1322_IRQ_TIMER16_1, port_80_interrupt, 2);
+
+/*
+ * The port 80 interrupt will use TIMER16 instance 1 for a 1ms countdown
+ * timer.  This timer is on GIRQ23, bit 1.
+ */
+static void port_80_interrupt_init(void)
+{
+	uint32_t val = 0;
+
+	/*
+	 * The timers are driven by a 48MHz oscillator.  Prescale down to
+	 * 1MHz. 48MHz/48 -> 1MHz
+	 */
+	val = MEC1322_TMR16_CTL(1);
+	val = (val & 0xFFFF) | (47 << 16);
+	/* Automatically restart the timer. */
+	val |= (1 << 3);
+	/* The counter should decrement. */
+	val &= ~(1 << 2);
+	MEC1322_TMR16_CTL(1) = val;
+
+	/* Set the reload value to 1000us. (1ms). */
+	MEC1322_TMR16_PRE(1) = 1000;
+
+	/* Clear the status if any. */
+	MEC1322_TMR16_STS(1) |= 1;
+
+	/* Clear any pending interrupt. */
+	MEC1322_INT_SOURCE(23) = (1 << 1);
+	/* Enable IRQ vector 23. */
+	MEC1322_INT_BLK_EN |= (1 << 23);
+	/* Enable the interrupt. */
+	MEC1322_TMR16_IEN(1) |= 1;
+	MEC1322_INT_ENABLE(23) = (1 << 1);
+	task_enable_irq(MEC1322_IRQ_TIMER16_1);
+
+	/* Enable and start the timer. */
+	MEC1322_TMR16_CTL(1) |= 1 | (1 << 5);
+}
+DECLARE_HOOK(HOOK_INIT, port_80_interrupt_init, HOOK_PRIO_DEFAULT);
+
+static void port_80_interrupt_enable(void)
+{
+	/* Enable the interrupt. */
+	task_enable_irq(MEC1322_IRQ_TIMER16_1);
+	/* Enable the timer block. */
+	MEC1322_TMR16_CTL(1) |= 1;
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, port_80_interrupt_enable, HOOK_PRIO_DEFAULT);
+
+static void port_80_interrupt_disable(void)
+{
+	/* Disable the timer block. */
+	MEC1322_TMR16_CTL(1) &= ~1;
+	/* Disable the interrupt. */
+	task_disable_irq(MEC1322_IRQ_TIMER16_1);
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, port_80_interrupt_disable,
+	     HOOK_PRIO_DEFAULT);
diff --git a/include/port80.h b/include/port80.h
index 470b01cc4b..c134dd92cf 100644
--- a/include/port80.h
+++ b/include/port80.h
@@ -23,7 +23,6 @@ enum port_80_event {
  */
 void port_80_write(int data);
 
-#ifdef HAS_TASK_PORT80
 /**
  * Chip specific function to read from port 80.
  *
@@ -31,6 +30,5 @@ void port_80_write(int data);
  *	or PORT_80_IGNORE if no data is available.
  */
 int port_80_read(void);
-#endif
 
 #endif  /* __CROS_EC_PORT80_H */