diff options
| author | Vijay Hiremath <vijay.p.hiremath@intel.com> | 2015-10-16 11:18:42 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2015-10-17 04:56:09 -0700 |
| commit | 784e0b1b472772080aaa975e0b7b415d78ab8ef1 (patch) | |
| tree | 28069d06776f6baf760cfbd05df8774f945ca142 | |
| parent | 9e070fd92b64508f76db1e9e5da19d6bd4e7a7b9 (diff) | |
| download | chrome-ec-784e0b1b472772080aaa975e0b7b415d78ab8ef1.tar.gz | |
Kunimitsu: PMIC: Keep the emergency reset time to default
Keeping the emergency reset time to default (31s) as the
EC/PCH can handle the 8sec emergency shutdown.
Reverting the below patch.
https://chromium-review.googlesource.com/#/c/298148/.
BUG=none
BRANCH=none
TEST=Manually tested the following.
1. Hold the powerbutton for >4s && <31s device enters to S3, S5 & SOC G3.
2. Hold the power button for >31s deive enetrs to S3, S5, SOC G3 & PG3.
3. From the Kernel console entered "stop powerd", hold the power
button for >10s && <31s device enters to S3, S5 & SOC G3.
Change-Id: I6db44bb4b9f6d64ff3b1d7677c54401971b534c3
Signed-off-by: Vijay Hiremath <vijay.p.hiremath@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/306733
Commit-Ready: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Tested-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Kevin K Wong <kevin.k.wong@intel.com>
Reviewed-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Kyoung Il Kim <kyoung.il.kim@intel.com>
| -rw-r--r-- | board/kunimitsu/board.c | 11 |
1 files changed, 0 insertions, 11 deletions
diff --git a/board/kunimitsu/board.c b/board/kunimitsu/board.c index e3e9b071c6..03007fefbe 100644 --- a/board/kunimitsu/board.c +++ b/board/kunimitsu/board.c @@ -384,17 +384,6 @@ static void board_pmic_init(void) goto pmic_error; /* - * Power button configuration - * [7] : 0b Power button debounce time, 30ms - * [6] : 0b Reset of power button timer logic, no action - * [5:0]: 1000b Time that the button must be held to force an - * emergency reset, 8s - */ - ret = I2C_PMIC_WRITE(TPS650830_REG_PBCONFIG, 0x08); - if (ret) - goto pmic_error; - - /* * Discharge control 4 register configuration * [7:6] : 00b Reserved * [5:4] : 01b V3.3S discharge resistance (V6S), 100 Ohm |