diff options
| author | Duncan Laurie <dlaurie@chromium.org> | 2016-01-22 07:14:27 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2016-01-22 11:55:56 -0800 |
| commit | 466675fb1778c910b3d67a5c1c7d37365e30ec57 (patch) | |
| tree | 59821dbeb90afe88524c1e3302061835d242310b | |
| parent | 0e8928920c0ec8b00da6da477ee719671046bb31 (diff) | |
| download | chrome-ec-466675fb1778c910b3d67a5c1c7d37365e30ec57.tar.gz | |
skylake: Better handling of S0->S5->S0 path
If we are doing a cold reset or if Deep S5 is disabled we will go into S5
and need to be able to power up again, but we do not have enough information
to know what direction the sequencing may go from S5 (to G3 or up to S0).
So limit the RTCRST check to just the explicit G3->S5 path and let the normal
checking of SLP_S4 signal happen otherwise.
BUG=chrome-os-partner:49564
BRANCH=glados
TEST=pass FAFT testing finally
Change-Id: I202234e58281e6b007ad2b98396994222d0831b2
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/323087
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
| -rw-r--r-- | power/skylake.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/power/skylake.c b/power/skylake.c index 1272575a5b..d19a639f77 100644 --- a/power/skylake.c +++ b/power/skylake.c @@ -212,10 +212,9 @@ static enum power_state _power_handle_state(enum power_state state) /* Wait for S5 exit and attempt RTC reset it supported */ if (power_s5_up) return power_wait_s5_rtc_reset(); -#else +#endif if (gpio_get_level(GPIO_PCH_SLP_S4_L) == 1) return POWER_S5S3; /* Power up to next state */ -#endif break; case POWER_S3: |