Active-low Link GPIOs end with _L, not n.

This is now consistent with other boards.

No functional changes, just renaming,

BUG=chrome-os-partner:18343
BRANCH=none
TEST=build link, bds

Change-Id: Ifd7c1ec608ab61f5f66800e91803ffafe1d944b6
Signed-off-by: Randall Spangler <rspangler@chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/48804
Reviewed-by: Bill Richardson <wfrichar@chromium.org>

6 files changed, 174 insertions, 174 deletions

diff --git a/board/link/board.c b/board/link/board.c
index b40fdd9a6a..b4e631d2f3 100644
--- a/board/link/board.c
+++ b/board/link/board.c
@@ -23,97 +23,97 @@
 /* GPIO signal list.  Must match order from enum gpio_signal. */
 const struct gpio_info gpio_list[GPIO_COUNT] = {
 	/* Inputs with interrupt handlers are first for efficiency */
-	{"POWER_BUTTONn",       LM4_GPIO_K, (1<<7), GPIO_INT_BOTH,
+	{"POWER_BUTTON_L",       LM4_GPIO_K, (1<<7), GPIO_INT_BOTH,
 	 switch_interrupt},
-	{"LID_SWITCHn",         LM4_GPIO_K, (1<<5), GPIO_INT_BOTH,
+	{"LID_SWITCH_L",         LM4_GPIO_K, (1<<5), GPIO_INT_BOTH,
 	 lid_interrupt},
 	/* Other inputs */
-	{"THERMAL_DATA_READYn", LM4_GPIO_B, (1<<4), 0, NULL},
-	{"AC_PRESENT",          LM4_GPIO_H, (1<<3), GPIO_INT_BOTH,
+	{"THERMAL_DATA_READY_L", LM4_GPIO_B, (1<<4), 0, NULL},
+	{"AC_PRESENT",           LM4_GPIO_H, (1<<3), GPIO_INT_BOTH,
 	 extpower_interrupt},
-	{"BOARD_VERSION1",      LM4_GPIO_H, (1<<6), 0, NULL},
-	{"BOARD_VERSION2",      LM4_GPIO_L, (1<<6), 0, NULL},
-	{"BOARD_VERSION3",      LM4_GPIO_L, (1<<7), 0, NULL},
-	{"PCH_BKLTEN",          LM4_GPIO_J, (1<<3), GPIO_INT_BOTH,
+	{"BOARD_VERSION1",       LM4_GPIO_H, (1<<6), 0, NULL},
+	{"BOARD_VERSION2",       LM4_GPIO_L, (1<<6), 0, NULL},
+	{"BOARD_VERSION3",       LM4_GPIO_L, (1<<7), 0, NULL},
+	{"PCH_BKLTEN",           LM4_GPIO_J, (1<<3), GPIO_INT_BOTH,
 	 switch_interrupt},
-	{"PCH_SLP_An",          LM4_GPIO_G, (1<<5), GPIO_INT_BOTH,
+	{"PCH_SLP_A_L",          LM4_GPIO_G, (1<<5), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PCH_SLP_ME_CSW_DEVn", LM4_GPIO_G, (1<<4), GPIO_INT_BOTH,
+	{"PCH_SLP_ME_CSW_DEV_L", LM4_GPIO_G, (1<<4), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PCH_SLP_S3n",         LM4_GPIO_J, (1<<0), GPIO_INT_BOTH,
+	{"PCH_SLP_S3_L",         LM4_GPIO_J, (1<<0), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PCH_SLP_S4n",         LM4_GPIO_J, (1<<1), GPIO_INT_BOTH,
+	{"PCH_SLP_S4_L",         LM4_GPIO_J, (1<<1), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PCH_SLP_S5n",         LM4_GPIO_J, (1<<2), GPIO_INT_BOTH,
+	{"PCH_SLP_S5_L",         LM4_GPIO_J, (1<<2), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PCH_SLP_SUSn",        LM4_GPIO_G, (1<<3), GPIO_INT_BOTH,
+	{"PCH_SLP_SUS_L",        LM4_GPIO_G, (1<<3), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PCH_SUSWARNn",        LM4_GPIO_G, (1<<2), GPIO_INT_BOTH,
+	{"PCH_SUSWARN_L",        LM4_GPIO_G, (1<<2), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PGOOD_1_5V_DDR",      LM4_GPIO_K, (1<<0), GPIO_INT_BOTH,
+	{"PGOOD_1_5V_DDR",       LM4_GPIO_K, (1<<0), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PGOOD_1_5V_PCH",      LM4_GPIO_K, (1<<1), GPIO_INT_BOTH,
+	{"PGOOD_1_5V_PCH",       LM4_GPIO_K, (1<<1), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PGOOD_1_8VS",         LM4_GPIO_K, (1<<3), GPIO_INT_BOTH,
+	{"PGOOD_1_8VS",          LM4_GPIO_K, (1<<3), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PGOOD_5VALW",         LM4_GPIO_H, (1<<0), GPIO_INT_BOTH,
+	{"PGOOD_5VALW",          LM4_GPIO_H, (1<<0), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PGOOD_CPU_CORE",      LM4_GPIO_M, (1<<3), GPIO_INT_BOTH,
+	{"PGOOD_CPU_CORE",       LM4_GPIO_M, (1<<3), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PGOOD_VCCP",          LM4_GPIO_K, (1<<2), GPIO_INT_BOTH,
+	{"PGOOD_VCCP",           LM4_GPIO_K, (1<<2), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PGOOD_VCCSA",         LM4_GPIO_H, (1<<1), GPIO_INT_BOTH,
+	{"PGOOD_VCCSA",          LM4_GPIO_H, (1<<1), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"PGOOD_VGFX_CORE",     LM4_GPIO_D, (1<<2), GPIO_INT_BOTH,
+	{"PGOOD_VGFX_CORE",      LM4_GPIO_D, (1<<2), GPIO_INT_BOTH,
 	 x86_power_interrupt},
-	{"RECOVERYn",           LM4_GPIO_H, (1<<7), GPIO_INT_BOTH,
+	{"RECOVERY_L",           LM4_GPIO_H, (1<<7), GPIO_INT_BOTH,
 	 switch_interrupt},
-	{"USB1_STATUSn",        LM4_GPIO_E, (1<<7), 0, NULL},
-	{"USB2_STATUSn",        LM4_GPIO_E, (1<<1), 0, NULL},
-	{"WRITE_PROTECT",       LM4_GPIO_J, (1<<4), GPIO_INT_BOTH,
+	{"USB1_STATUS_L",        LM4_GPIO_E, (1<<7), 0, NULL},
+	{"USB2_STATUS_L",        LM4_GPIO_E, (1<<1), 0, NULL},
+	{"WRITE_PROTECT",        LM4_GPIO_J, (1<<4), GPIO_INT_BOTH,
 	 switch_interrupt},
 	/* Outputs; all unasserted by default except for reset signals */
-	{"CPU_PROCHOT",         LM4_GPIO_F, (1<<2), GPIO_OUT_LOW, NULL},
-	{"ENABLE_1_5V_DDR",     LM4_GPIO_H, (1<<5), GPIO_OUT_LOW, NULL},
-	{"ENABLE_5VALW",        LM4_GPIO_K, (1<<4), GPIO_OUT_HIGH, NULL},
-	{"ENABLE_BACKLIGHT",    LM4_GPIO_H, (1<<4), GPIO_OUT_LOW, NULL},
-	{"ENABLE_TOUCHPAD",     LM4_GPIO_C, (1<<6), GPIO_OUT_LOW, NULL},
-	{"ENABLE_VCORE",        LM4_GPIO_F, (1<<7), GPIO_OUT_LOW, NULL},
-	{"ENABLE_VS",           LM4_GPIO_G, (1<<6), GPIO_OUT_LOW, NULL},
-	{"ENABLE_WLAN",         LM4_GPIO_Q, (1<<5), GPIO_OUT_LOW, NULL},
-	{"ENTERING_RW",         LM4_GPIO_J, (1<<5), GPIO_OUT_LOW, NULL},
-	{"LIGHTBAR_RESETn",     LM4_GPIO_B, (1<<1), GPIO_OUT_LOW, NULL},
-	{"PCH_A20GATE",         LM4_GPIO_Q, (1<<6), GPIO_OUT_LOW, NULL},
-	{"PCH_DPWROK",          LM4_GPIO_G, (1<<0), GPIO_OUT_LOW, NULL},
+	{"CPU_PROCHOT",          LM4_GPIO_F, (1<<2), GPIO_OUT_LOW, NULL},
+	{"ENABLE_1_5V_DDR",      LM4_GPIO_H, (1<<5), GPIO_OUT_LOW, NULL},
+	{"ENABLE_5VALW",         LM4_GPIO_K, (1<<4), GPIO_OUT_HIGH, NULL},
+	{"ENABLE_BACKLIGHT",     LM4_GPIO_H, (1<<4), GPIO_OUT_LOW, NULL},
+	{"ENABLE_TOUCHPAD",      LM4_GPIO_C, (1<<6), GPIO_OUT_LOW, NULL},
+	{"ENABLE_VCORE",         LM4_GPIO_F, (1<<7), GPIO_OUT_LOW, NULL},
+	{"ENABLE_VS",            LM4_GPIO_G, (1<<6), GPIO_OUT_LOW, NULL},
+	{"ENABLE_WLAN",          LM4_GPIO_Q, (1<<5), GPIO_OUT_LOW, NULL},
+	{"ENTERING_RW",          LM4_GPIO_J, (1<<5), GPIO_OUT_LOW, NULL},
+	{"LIGHTBAR_RESET_L",     LM4_GPIO_B, (1<<1), GPIO_OUT_LOW, NULL},
+	{"PCH_A20GATE",          LM4_GPIO_Q, (1<<6), GPIO_OUT_LOW, NULL},
+	{"PCH_DPWROK",           LM4_GPIO_G, (1<<0), GPIO_OUT_LOW, NULL},
 	/*
 	 * HDA_SDO is technically an output, but we need to leave it as an
 	 * input until we drive it high.  So can't use open-drain (HI_Z).
 	 */
-	{"PCH_HDA_SDO",         LM4_GPIO_G, (1<<1), GPIO_INPUT, NULL},
-	{"PCH_WAKEn",           LM4_GPIO_F, (1<<0), GPIO_OUT_HIGH, NULL},
-	{"PCH_NMIn",            LM4_GPIO_M, (1<<2), GPIO_OUT_HIGH, NULL},
-	{"PCH_PWRBTNn",         LM4_GPIO_G, (1<<7), GPIO_OUT_HIGH, NULL},
-	{"PCH_PWROK",           LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL},
-	{"PCH_RCINn",           LM4_GPIO_Q, (1<<7), GPIO_HI_Z, NULL},
-	{"PCH_RSMRSTn",         LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL},
-	{"PCH_RTCRSTn",         LM4_GPIO_F, (1<<6), GPIO_HI_Z, NULL},
-	{"PCH_SMIn",            LM4_GPIO_F, (1<<4), GPIO_OUT_HIGH, NULL},
-	{"PCH_SRTCRSTn",        LM4_GPIO_C, (1<<7), GPIO_HI_Z, NULL},
-	{"PCH_SUSACKn",         LM4_GPIO_F, (1<<3), GPIO_OUT_HIGH, NULL},
-	{"RADIO_ENABLE_WLAN",   LM4_GPIO_D, (1<<0), GPIO_OUT_LOW, NULL},
-	{"RADIO_ENABLE_BT",     LM4_GPIO_D, (1<<1), GPIO_OUT_LOW, NULL},
-	{"SPI_CSn",             LM4_GPIO_A, (1<<3), GPIO_HI_Z, NULL},
-	{"TOUCHSCREEN_RESETn",  LM4_GPIO_B, (1<<0), GPIO_OUT_LOW, NULL},
-	{"USB1_CTL1",           LM4_GPIO_E, (1<<2), GPIO_OUT_LOW, NULL},
-	{"USB1_CTL2",           LM4_GPIO_E, (1<<3), GPIO_OUT_LOW, NULL},
-	{"USB1_CTL3",           LM4_GPIO_E, (1<<4), GPIO_OUT_LOW, NULL},
-	{"USB1_ENABLE",         LM4_GPIO_E, (1<<5), GPIO_OUT_LOW, NULL},
-	{"USB1_ILIM_SEL",       LM4_GPIO_E, (1<<6), GPIO_OUT_LOW, NULL},
-	{"USB2_CTL1",           LM4_GPIO_D, (1<<4), GPIO_OUT_LOW, NULL},
-	{"USB2_CTL2",           LM4_GPIO_D, (1<<5), GPIO_OUT_LOW, NULL},
-	{"USB2_CTL3",           LM4_GPIO_D, (1<<6), GPIO_OUT_LOW, NULL},
-	{"USB2_ENABLE",         LM4_GPIO_D, (1<<7), GPIO_OUT_LOW, NULL},
-	{"USB2_ILIM_SEL",       LM4_GPIO_E, (1<<0), GPIO_OUT_LOW, NULL},
+	{"PCH_HDA_SDO",          LM4_GPIO_G, (1<<1), GPIO_INPUT, NULL},
+	{"PCH_WAKE_L",           LM4_GPIO_F, (1<<0), GPIO_OUT_HIGH, NULL},
+	{"PCH_NMI_L",            LM4_GPIO_M, (1<<2), GPIO_OUT_HIGH, NULL},
+	{"PCH_PWRBTN_L",         LM4_GPIO_G, (1<<7), GPIO_OUT_HIGH, NULL},
+	{"PCH_PWROK",            LM4_GPIO_F, (1<<5), GPIO_OUT_LOW, NULL},
+	{"PCH_RCIN_L",           LM4_GPIO_Q, (1<<7), GPIO_HI_Z, NULL},
+	{"PCH_RSMRST_L",         LM4_GPIO_F, (1<<1), GPIO_OUT_LOW, NULL},
+	{"PCH_RTCRST_L",         LM4_GPIO_F, (1<<6), GPIO_HI_Z, NULL},
+	{"PCH_SMI_L",            LM4_GPIO_F, (1<<4), GPIO_OUT_HIGH, NULL},
+	{"PCH_SRTCRST_L",        LM4_GPIO_C, (1<<7), GPIO_HI_Z, NULL},
+	{"PCH_SUSACK_L",         LM4_GPIO_F, (1<<3), GPIO_OUT_HIGH, NULL},
+	{"RADIO_ENABLE_WLAN",    LM4_GPIO_D, (1<<0), GPIO_OUT_LOW, NULL},
+	{"RADIO_ENABLE_BT",      LM4_GPIO_D, (1<<1), GPIO_OUT_LOW, NULL},
+	{"SPI_CS_L",             LM4_GPIO_A, (1<<3), GPIO_HI_Z, NULL},
+	{"TOUCHSCREEN_RESET_L",  LM4_GPIO_B, (1<<0), GPIO_OUT_LOW, NULL},
+	{"USB1_CTL1",            LM4_GPIO_E, (1<<2), GPIO_OUT_LOW, NULL},
+	{"USB1_CTL2",            LM4_GPIO_E, (1<<3), GPIO_OUT_LOW, NULL},
+	{"USB1_CTL3",            LM4_GPIO_E, (1<<4), GPIO_OUT_LOW, NULL},
+	{"USB1_ENABLE",          LM4_GPIO_E, (1<<5), GPIO_OUT_LOW, NULL},
+	{"USB1_ILIM_SEL",        LM4_GPIO_E, (1<<6), GPIO_OUT_LOW, NULL},
+	{"USB2_CTL1",            LM4_GPIO_D, (1<<4), GPIO_OUT_LOW, NULL},
+	{"USB2_CTL2",            LM4_GPIO_D, (1<<5), GPIO_OUT_LOW, NULL},
+	{"USB2_CTL3",            LM4_GPIO_D, (1<<6), GPIO_OUT_LOW, NULL},
+	{"USB2_ENABLE",          LM4_GPIO_D, (1<<7), GPIO_OUT_LOW, NULL},
+	{"USB2_ILIM_SEL",        LM4_GPIO_E, (1<<0), GPIO_OUT_LOW, NULL},
 };
 
 /* ADC channels. Must be in the exactly same order as in enum adc_channel. */
diff --git a/board/link/board.h b/board/link/board.h
index 7d3c7c1ceb..b8cc44df97 100644
--- a/board/link/board.h
+++ b/board/link/board.h
@@ -121,73 +121,73 @@ enum adc_channel
 /* GPIO signal definitions. */
 enum gpio_signal {
 	/* Inputs with interrupt handlers are first for efficiency */
-	GPIO_POWER_BUTTONn = 0,   /* Power button */
-	GPIO_LID_SWITCHn,         /* Lid switch */
-	GPIO_THERMAL_DATA_READYn, /* Data ready from I2C thermal sensor */
+	GPIO_POWER_BUTTON_L = 0,   /* Power button */
+	GPIO_LID_SWITCH_L,         /* Lid switch */
+	GPIO_THERMAL_DATA_READY_L, /* Data ready from I2C thermal sensor */
 	/* Other inputs */
-	GPIO_AC_PRESENT,          /* AC power present */
-	GPIO_BOARD_VERSION1,      /* Board version stuffing resistor 1 */
-	GPIO_BOARD_VERSION2,      /* Board version stuffing resistor 2 */
-	GPIO_BOARD_VERSION3,      /* Board version stuffing resistor 3 */
-	GPIO_PCH_BKLTEN,          /* Backlight enable signal from PCH */
-	GPIO_PCH_SLP_An,          /* SLP_A# signal from PCH */
-	GPIO_PCH_SLP_ME_CSW_DEVn, /* SLP_ME_CSW_DEV# signal from PCH */
-	GPIO_PCH_SLP_S3n,         /* SLP_S3# signal from PCH */
-	GPIO_PCH_SLP_S4n,         /* SLP_S4# signal from PCH */
-	GPIO_PCH_SLP_S5n,         /* SLP_S5# signal from PCH */
-	GPIO_PCH_SLP_SUSn,        /* SLP_SUS# signal from PCH */
-	GPIO_PCH_SUSWARNn,        /* SUSWARN# signal from PCH */
-	GPIO_PGOOD_1_5V_DDR,      /* Power good on +1.5V_DDR */
-	GPIO_PGOOD_1_5V_PCH,      /* Power good on +1.5V_PCH */
-	GPIO_PGOOD_1_8VS,         /* Power good on +1.8VS */
-	GPIO_PGOOD_5VALW,         /* Power good on +5VALW */
-	GPIO_PGOOD_CPU_CORE,      /* Power good on +CPU_CORE */
-	GPIO_PGOOD_VCCP,          /* Power good on +VCCP */
-	GPIO_PGOOD_VCCSA,         /* Power good on +VCCSA */
-	GPIO_PGOOD_VGFX_CORE,     /* Power good on +VGFX_CORE */
-	GPIO_RECOVERYn,           /* Recovery signal from servo */
-	GPIO_USB1_STATUSn,        /* USB charger port 1 status output */
-	GPIO_USB2_STATUSn,        /* USB charger port 2 status output */
-	GPIO_WRITE_PROTECT,       /* Write protect input */
+	GPIO_AC_PRESENT,           /* AC power present */
+	GPIO_BOARD_VERSION1,       /* Board version stuffing resistor 1 */
+	GPIO_BOARD_VERSION2,       /* Board version stuffing resistor 2 */
+	GPIO_BOARD_VERSION3,       /* Board version stuffing resistor 3 */
+	GPIO_PCH_BKLTEN,           /* Backlight enable signal from PCH */
+	GPIO_PCH_SLP_A_L,          /* SLP_A# signal from PCH */
+	GPIO_PCH_SLP_ME_CSW_DEV_L, /* SLP_ME_CSW_DEV# signal from PCH */
+	GPIO_PCH_SLP_S3_L,         /* SLP_S3# signal from PCH */
+	GPIO_PCH_SLP_S4_L,         /* SLP_S4# signal from PCH */
+	GPIO_PCH_SLP_S5_L,         /* SLP_S5# signal from PCH */
+	GPIO_PCH_SLP_SUS_L,        /* SLP_SUS# signal from PCH */
+	GPIO_PCH_SUSWARN_L,        /* SUSWARN# signal from PCH */
+	GPIO_PGOOD_1_5V_DDR,       /* Power good on +1.5V_DDR */
+	GPIO_PGOOD_1_5V_PCH,       /* Power good on +1.5V_PCH */
+	GPIO_PGOOD_1_8VS,          /* Power good on +1.8VS */
+	GPIO_PGOOD_5VALW,          /* Power good on +5VALW */
+	GPIO_PGOOD_CPU_CORE,       /* Power good on +CPU_CORE */
+	GPIO_PGOOD_VCCP,           /* Power good on +VCCP */
+	GPIO_PGOOD_VCCSA,          /* Power good on +VCCSA */
+	GPIO_PGOOD_VGFX_CORE,      /* Power good on +VGFX_CORE */
+	GPIO_RECOVERY_L,           /* Recovery signal from servo */
+	GPIO_USB1_STATUS_L,        /* USB charger port 1 status output */
+	GPIO_USB2_STATUS_L,        /* USB charger port 2 status output */
+	GPIO_WRITE_PROTECT,        /* Write protect input */
 	/* Outputs */
-	GPIO_CPU_PROCHOT,         /* Force CPU to think it's overheated */
-	GPIO_ENABLE_1_5V_DDR,     /* Enable +1.5V_DDR supply */
-	GPIO_ENABLE_5VALW,        /* Enable +5V always on rail */
-	GPIO_ENABLE_BACKLIGHT,    /* Enable backlight power */
-	GPIO_ENABLE_TOUCHPAD,     /* Enable touchpad power */
-	GPIO_ENABLE_VCORE,        /* Enable +CPU_CORE and +VGFX_CORE */
-	GPIO_ENABLE_VS,           /* Enable VS power supplies */
-	GPIO_ENABLE_WLAN,         /* Enable WLAN module power (+3VS_WLAN) */
-	GPIO_ENTERING_RW,         /* Indicate when EC is entering RW code */
-	GPIO_LIGHTBAR_RESETn,     /* Reset lightbar controllers */
-	GPIO_PCH_A20GATE,         /* A20GATE signal to PCH */
-	GPIO_PCH_DPWROK,          /* DPWROK signal to PCH */
-	GPIO_PCH_HDA_SDO,         /* HDA_SDO signal to PCH; when high, ME
-				   * ignores security descriptor */
-	GPIO_PCH_WAKEn,           /* Wake signal output to PCH */
-	GPIO_PCH_NMIn,            /* Non-maskable interrupt pin to PCH */
-	GPIO_PCH_PWRBTNn,         /* Power button output to PCH */
-	GPIO_PCH_PWROK,           /* PWROK / APWROK signals to PCH */
-	GPIO_PCH_RCINn,           /* RCIN# signal to PCH */
-	GPIO_PCH_RSMRSTn,         /* Reset PCH resume power plane logic */
-	GPIO_PCH_RTCRSTn,         /* Reset PCH RTC well */
-	GPIO_PCH_SMIn,            /* System management interrupt to PCH */
-	GPIO_PCH_SRTCRSTn,        /* Reset PCH ME RTC well */
-	GPIO_PCH_SUSACKn,         /* Acknowledge PCH SUSWARN# signal */
-	GPIO_RADIO_ENABLE_WLAN,   /* Enable WLAN radio */
-	GPIO_RADIO_ENABLE_BT,     /* Enable bluetooth radio */
-	GPIO_SPI_CSn,             /* SPI chip select */
-	GPIO_TOUCHSCREEN_RESETn,  /* Reset touch screen */
-	GPIO_USB1_CTL1,           /* USB charger port 1 CTL1 output */
-	GPIO_USB1_CTL2,           /* USB charger port 1 CTL2 output */
-	GPIO_USB1_CTL3,           /* USB charger port 1 CTL3 output */
-	GPIO_USB1_ENABLE,         /* USB charger port 1 enable */
-	GPIO_USB1_ILIM_SEL,       /* USB charger port 1 ILIM_SEL output */
-	GPIO_USB2_CTL1,           /* USB charger port 2 CTL1 output */
-	GPIO_USB2_CTL2,           /* USB charger port 2 CTL2 output */
-	GPIO_USB2_CTL3,           /* USB charger port 2 CTL3 output */
-	GPIO_USB2_ENABLE,         /* USB charger port 2 enable */
-	GPIO_USB2_ILIM_SEL,       /* USB charger port 2 ILIM_SEL output */
+	GPIO_CPU_PROCHOT,          /* Force CPU to think it's overheated */
+	GPIO_ENABLE_1_5V_DDR,      /* Enable +1.5V_DDR supply */
+	GPIO_ENABLE_5VALW,         /* Enable +5V always on rail */
+	GPIO_ENABLE_BACKLIGHT,     /* Enable backlight power */
+	GPIO_ENABLE_TOUCHPAD,      /* Enable touchpad power */
+	GPIO_ENABLE_VCORE,         /* Enable +CPU_CORE and +VGFX_CORE */
+	GPIO_ENABLE_VS,            /* Enable VS power supplies */
+	GPIO_ENABLE_WLAN,          /* Enable WLAN module power (+3VS_WLAN) */
+	GPIO_ENTERING_RW,          /* Indicate when EC is entering RW code */
+	GPIO_LIGHTBAR_RESET_L,     /* Reset lightbar controllers */
+	GPIO_PCH_A20GATE,          /* A20GATE signal to PCH */
+	GPIO_PCH_DPWROK,           /* DPWROK signal to PCH */
+	GPIO_PCH_HDA_SDO,          /* HDA_SDO signal to PCH; when high, ME
+				    * ignores security descriptor */
+	GPIO_PCH_WAKE_L,           /* Wake signal output to PCH */
+	GPIO_PCH_NMI_L,            /* Non-maskable interrupt pin to PCH */
+	GPIO_PCH_PWRBTN_L,         /* Power button output to PCH */
+	GPIO_PCH_PWROK,            /* PWROK / APWROK signals to PCH */
+	GPIO_PCH_RCIN_L,           /* RCIN# signal to PCH */
+	GPIO_PCH_RSMRST_L,         /* Reset PCH resume power plane logic */
+	GPIO_PCH_RTCRST_L,         /* Reset PCH RTC well */
+	GPIO_PCH_SMI_L,            /* System management interrupt to PCH */
+	GPIO_PCH_SRTCRST_L,        /* Reset PCH ME RTC well */
+	GPIO_PCH_SUSACK_L,         /* Acknowledge PCH SUSWARN# signal */
+	GPIO_RADIO_ENABLE_WLAN,    /* Enable WLAN radio */
+	GPIO_RADIO_ENABLE_BT,      /* Enable bluetooth radio */
+	GPIO_SPI_CS_L,             /* SPI chip select */
+	GPIO_TOUCHSCREEN_RESET_L,  /* Reset touch screen */
+	GPIO_USB1_CTL1,            /* USB charger port 1 CTL1 output */
+	GPIO_USB1_CTL2,            /* USB charger port 1 CTL2 output */
+	GPIO_USB1_CTL3,            /* USB charger port 1 CTL3 output */
+	GPIO_USB1_ENABLE,          /* USB charger port 1 enable */
+	GPIO_USB1_ILIM_SEL,        /* USB charger port 1 ILIM_SEL output */
+	GPIO_USB2_CTL1,            /* USB charger port 2 CTL1 output */
+	GPIO_USB2_CTL2,            /* USB charger port 2 CTL2 output */
+	GPIO_USB2_CTL3,            /* USB charger port 2 CTL3 output */
+	GPIO_USB2_ENABLE,          /* USB charger port 2 enable */
+	GPIO_USB2_ILIM_SEL,        /* USB charger port 2 ILIM_SEL output */
 
 	/* Number of GPIOs; not an actual GPIO */
 	GPIO_COUNT
diff --git a/chip/lm4/lpc.c b/chip/lm4/lpc.c
index fa221fd71e..00f9e7273e 100644
--- a/chip/lm4/lpc.c
+++ b/chip/lm4/lpc.c
@@ -113,9 +113,9 @@ static void lpc_manual_irq(int irq_num)
  */
 static void lpc_generate_smi(void)
 {
-	gpio_set_level(GPIO_PCH_SMIn, 0);
+	gpio_set_level(GPIO_PCH_SMI_L, 0);
 	udelay(65);
-	gpio_set_level(GPIO_PCH_SMIn, 1);
+	gpio_set_level(GPIO_PCH_SMI_L, 1);
 
 	if (host_events & event_mask[LPC_HOST_EVENT_SMI])
 		CPRINTF("[%T smi 0x%08x]\n",
@@ -251,7 +251,7 @@ void lpc_comx_put_char(int c)
  * Update the host event status.
  *
  * Sends a pulse if masked event status becomes non-zero:
- *   - SMI pulse via EC_SMIn GPIO
+ *   - SMI pulse via EC_SMI_L GPIO
  *   - SCI pulse via LPC0SCI
  */
 static void update_host_event_status(void) {
@@ -286,9 +286,9 @@ static void update_host_event_status(void) {
 
 	/* Update level-sensitive wake signal */
 	if (host_events & event_mask[LPC_HOST_EVENT_WAKE])
-		gpio_set_level(GPIO_PCH_WAKEn, 0);
+		gpio_set_level(GPIO_PCH_WAKE_L, 0);
 	else
-		gpio_set_level(GPIO_PCH_WAKEn, 1);
+		gpio_set_level(GPIO_PCH_WAKE_L, 1);
 
 	/* Send pulse on SMI signal if needed */
 	if (need_smi)
diff --git a/chip/lm4/switch.c b/chip/lm4/switch.c
index 76e28c95fd..237f130712 100644
--- a/chip/lm4/switch.c
+++ b/chip/lm4/switch.c
@@ -126,7 +126,7 @@ static void update_other_switches(void)
 	else
 		*memmap_switches &= ~EC_SWITCH_WRITE_PROTECT_DISABLED;
 
-	if (gpio_get_level(GPIO_RECOVERYn) == 0)
+	if (gpio_get_level(GPIO_RECOVERY_L) == 0)
 		*memmap_switches |= EC_SWITCH_DEDICATED_RECOVERY;
 	else
 		*memmap_switches &= ~EC_SWITCH_DEDICATED_RECOVERY;
@@ -144,7 +144,7 @@ static void set_pwrbtn_to_pch(int high)
 	}
 
 	CPRINTF("[%T PB PCH pwrbtn=%s]\n", high ? "HIGH" : "LOW");
-	gpio_set_level(GPIO_PCH_PWRBTNn, high);
+	gpio_set_level(GPIO_PCH_PWRBTN_L, high);
 }
 
 /**
@@ -161,7 +161,7 @@ static int raw_power_button_pressed(void)
 	if (!lid_is_open())
 		return 0;
 
-	return gpio_get_level(GPIO_POWER_BUTTONn) ? 0 : 1;
+	return gpio_get_level(GPIO_POWER_BUTTON_L) ? 0 : 1;
 }
 
 static void update_backlight(void)
@@ -504,8 +504,8 @@ static void switch_init(void)
 	*host_get_memmap(EC_MEMMAP_SWITCHES_VERSION) = 1;
 
 	/* Enable interrupts, now that we've initialized */
-	gpio_enable_interrupt(GPIO_POWER_BUTTONn);
-	gpio_enable_interrupt(GPIO_RECOVERYn);
+	gpio_enable_interrupt(GPIO_POWER_BUTTON_L);
+	gpio_enable_interrupt(GPIO_RECOVERY_L);
 	gpio_enable_interrupt(GPIO_WRITE_PROTECT);
 }
 DECLARE_HOOK(HOOK_INIT, switch_init, HOOK_PRIO_DEFAULT);
@@ -539,7 +539,7 @@ void switch_interrupt(enum gpio_signal signal)
 {
 	/* Reset debounce time for the changed signal */
 	switch (signal) {
-	case GPIO_POWER_BUTTONn:
+	case GPIO_POWER_BUTTON_L:
 		/* Reset power button debounce time */
 		tdebounce_pwr = get_time().val + PWRBTN_DEBOUNCE_US;
 		if (raw_power_button_pressed()) {
diff --git a/common/lid_switch.c b/common/lid_switch.c
index 68c049e52c..b866bad0f7 100644
--- a/common/lid_switch.c
+++ b/common/lid_switch.c
@@ -28,7 +28,7 @@ static int debounced_lid_open;		/* Debounced lid state */
  */
 static int raw_lid_open(void)
 {
-	return gpio_get_level(GPIO_LID_SWITCHn) ? 1 : 0;
+	return gpio_get_level(GPIO_LID_SWITCH_L) ? 1 : 0;
 }
 
 /**
@@ -77,7 +77,7 @@ static void lid_init(void)
 		debounced_lid_open = 1;
 
 	/* Enable interrupts, now that we've initialized */
-	gpio_enable_interrupt(GPIO_LID_SWITCHn);
+	gpio_enable_interrupt(GPIO_LID_SWITCH_L);
 }
 DECLARE_HOOK(HOOK_INIT, lid_init, HOOK_PRIO_INIT_LID);
 
diff --git a/common/x86_power.c b/common/x86_power.c
index 689229e5e5..7761b883c9 100644
--- a/common/x86_power.c
+++ b/common/x86_power.c
@@ -141,25 +141,25 @@ static void update_in_signals(void)
 	if (gpio_get_level(GPIO_PGOOD_VGFX_CORE))
 		inew |= IN_PGOOD_VGFX_CORE;
 
-	if (gpio_get_level(GPIO_PCH_SLP_An))
+	if (gpio_get_level(GPIO_PCH_SLP_A_L))
 		inew |= IN_PCH_SLP_An_DEASSERTED;
-	if (gpio_get_level(GPIO_PCH_SLP_S3n))
+	if (gpio_get_level(GPIO_PCH_SLP_S3_L))
 		inew |= IN_PCH_SLP_S3n_DEASSERTED;
-	if (gpio_get_level(GPIO_PCH_SLP_S4n))
+	if (gpio_get_level(GPIO_PCH_SLP_S4_L))
 		inew |= IN_PCH_SLP_S4n_DEASSERTED;
-	if (gpio_get_level(GPIO_PCH_SLP_S5n))
+	if (gpio_get_level(GPIO_PCH_SLP_S5_L))
 		inew |= IN_PCH_SLP_S5n_DEASSERTED;
 
-	if (gpio_get_level(GPIO_PCH_SLP_SUSn))
+	if (gpio_get_level(GPIO_PCH_SLP_SUS_L))
 		inew |= IN_PCH_SLP_SUSn_DEASSERTED;
-	if (gpio_get_level(GPIO_PCH_SLP_ME_CSW_DEVn))
+	if (gpio_get_level(GPIO_PCH_SLP_ME_CSW_DEV_L))
 		inew |= IN_PCH_SLP_MEn_DEASSERTED;
 
-	v = gpio_get_level(GPIO_PCH_SUSWARNn);
+	v = gpio_get_level(GPIO_PCH_SUSWARN_L);
 	if (v)
 		inew |= IN_PCH_SUSWARNn_DEASSERTED;
 	/* Copy SUSWARN# signal from PCH to SUSACK# */
-	gpio_set_level(GPIO_PCH_SUSACKn, v);
+	gpio_set_level(GPIO_PCH_SUSACK_L, v);
 
 	if ((in_signals & in_debug) != (inew & in_debug))
 		CPRINTF("[%T x86 in 0x%04x]\n", inew);
@@ -227,7 +227,7 @@ void chipset_force_shutdown(void)
 	 * transitions to G3.
 	 */
 	gpio_set_level(GPIO_PCH_DPWROK, 0);
-	gpio_set_level(GPIO_PCH_RSMRSTn, 0);
+	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
 }
 
 void chipset_reset(int cold_reset)
@@ -258,9 +258,9 @@ void chipset_reset(int cold_reset)
 		 */
 
 		/* Pulse must be at least 16 PCI clocks long = 500 ns */
-		gpio_set_level(GPIO_PCH_RCINn, 0);
+		gpio_set_level(GPIO_PCH_RCIN_L, 0);
 		udelay(10);
-		gpio_set_level(GPIO_PCH_RCINn, 1);
+		gpio_set_level(GPIO_PCH_RCIN_L, 1);
 	}
 }
 
@@ -380,22 +380,22 @@ static void x86_power_init(void)
 			gpio_set_level(GPIO_ENABLE_VCORE, 0);
 			gpio_set_level(GPIO_ENABLE_VS, 0);
 			gpio_set_level(GPIO_ENABLE_TOUCHPAD, 0);
-			gpio_set_level(GPIO_TOUCHSCREEN_RESETn, 0);
+			gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
 			gpio_set_level(GPIO_ENABLE_1_5V_DDR, 0);
-			gpio_set_level(GPIO_PCH_RSMRSTn, 0);
+			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
 			gpio_set_level(GPIO_PCH_DPWROK, 0);
 		}
 	}
 
 	/* Enable interrupts for our GPIOs */
 	gpio_enable_interrupt(GPIO_PCH_BKLTEN);
-	gpio_enable_interrupt(GPIO_PCH_SLP_An);
-	gpio_enable_interrupt(GPIO_PCH_SLP_ME_CSW_DEVn);
-	gpio_enable_interrupt(GPIO_PCH_SLP_S3n);
-	gpio_enable_interrupt(GPIO_PCH_SLP_S4n);
-	gpio_enable_interrupt(GPIO_PCH_SLP_S5n);
-	gpio_enable_interrupt(GPIO_PCH_SLP_SUSn);
-	gpio_enable_interrupt(GPIO_PCH_SUSWARNn);
+	gpio_enable_interrupt(GPIO_PCH_SLP_A_L);
+	gpio_enable_interrupt(GPIO_PCH_SLP_ME_CSW_DEV_L);
+	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
+	gpio_enable_interrupt(GPIO_PCH_SLP_S4_L);
+	gpio_enable_interrupt(GPIO_PCH_SLP_S5_L);
+	gpio_enable_interrupt(GPIO_PCH_SLP_SUS_L);
+	gpio_enable_interrupt(GPIO_PCH_SUSWARN_L);
 	gpio_enable_interrupt(GPIO_PGOOD_1_5V_DDR);
 	gpio_enable_interrupt(GPIO_PGOOD_1_5V_PCH);
 	gpio_enable_interrupt(GPIO_PGOOD_1_8VS);
@@ -466,7 +466,7 @@ void chipset_task(void)
 			break;
 
 		case X86_S5:
-			if (gpio_get_level(GPIO_PCH_SLP_S5n) == 1) {
+			if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 1) {
 				/* Power up to next state */
 				state = X86_S5S3;
 				break;
@@ -488,7 +488,7 @@ void chipset_task(void)
 			 * power usage.  If lid is open, take touchscreen out
 			 * of reset so it can wake the processor.
 			 */
-			gpio_set_level(GPIO_TOUCHSCREEN_RESETn, lid_is_open());
+			gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, lid_is_open());
 
 			/* Check for state transitions */
 			if (!have_all_in_signals(IN_PGOOD_S3)) {
@@ -496,11 +496,11 @@ void chipset_task(void)
 				chipset_force_shutdown();
 				state = X86_S3S5;
 				break;
-			} else if (gpio_get_level(GPIO_PCH_SLP_S3n) == 1) {
+			} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 1) {
 				/* Power up to next state */
 				state = X86_S3S0;
 				break;
-			} else if (gpio_get_level(GPIO_PCH_SLP_S5n) == 0) {
+			} else if (gpio_get_level(GPIO_PCH_SLP_S5_L) == 0) {
 				/* Power down to next state */
 				state = X86_S3S5;
 				break;
@@ -517,7 +517,7 @@ void chipset_task(void)
 				chipset_force_shutdown();
 				state = X86_S0S3;
 				break;
-			} else if (gpio_get_level(GPIO_PCH_SLP_S3n) == 0) {
+			} else if (gpio_get_level(GPIO_PCH_SLP_S3_L) == 0) {
 				/* Power down to next state */
 				state = X86_S0S3;
 				break;
@@ -537,7 +537,7 @@ void chipset_task(void)
 
 			/* Assert DPWROK, deassert RSMRST# */
 			gpio_set_level(GPIO_PCH_DPWROK, 1);
-			gpio_set_level(GPIO_PCH_RSMRSTn, 1);
+			gpio_set_level(GPIO_PCH_RSMRST_L, 1);
 
 			/* Wait 5ms for SUSCLK to stabilize */
 			msleep(5);
@@ -557,7 +557,7 @@ void chipset_task(void)
 			 * available and we won't leak +3VALW through the reset
 			 * line.
 			 */
-			gpio_set_level(GPIO_LIGHTBAR_RESETn, 1);
+			gpio_set_level(GPIO_LIGHTBAR_RESET_L, 1);
 
 			/* Turn on power to RAM */
 			gpio_set_level(GPIO_ENABLE_1_5V_DDR, 1);
@@ -592,12 +592,12 @@ void chipset_task(void)
 			 * lid is still closed); it may have been turned off if
 			 * the lid was closed in S3.
 			 */
-			gpio_set_level(GPIO_TOUCHSCREEN_RESETn, 1);
+			gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 1);
 
 			/* Wait for non-core power rails good */
 			if (wait_in_signals(IN_PGOOD_S0)) {
 				chipset_force_shutdown();
-				gpio_set_level(GPIO_TOUCHSCREEN_RESETn, 0);
+				gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
 				gpio_set_level(GPIO_ENABLE_WLAN, 0);
 				gpio_set_level(GPIO_RADIO_ENABLE_WLAN, 0);
 				gpio_set_level(GPIO_RADIO_ENABLE_BT, 0);
@@ -679,8 +679,8 @@ void chipset_task(void)
 			 * of that change we'll still reset these components in
 			 * S5.)
 			 */
-			gpio_set_level(GPIO_TOUCHSCREEN_RESETn, 0);
-			gpio_set_level(GPIO_LIGHTBAR_RESETn, 0);
+			gpio_set_level(GPIO_TOUCHSCREEN_RESET_L, 0);
+			gpio_set_level(GPIO_LIGHTBAR_RESET_L, 0);
 
 			state = X86_S5;
 			break;
@@ -688,7 +688,7 @@ void chipset_task(void)
 		case X86_S5G3:
 			/* Deassert DPWROK, assert RSMRST# */
 			gpio_set_level(GPIO_PCH_DPWROK, 0);
-			gpio_set_level(GPIO_PCH_RSMRSTn, 0);
+			gpio_set_level(GPIO_PCH_RSMRST_L, 0);
 
 			/* Record the time we go into G3 */
 			last_shutdown_time = get_time().val;