nucleo-f412zg: Initial board offering

This brings initial support for the Nucleo-F412ZG
development board.

This configuration is similar to bloonchipper, but without
fingerprint sensor support, without rollback secret
support, and with an adjusted console USART selection.

The included README.md shows some quick steps to
get a Nucleo-F412ZG up and running EC.

Note that the RSA key included is only for test builds.
It should not be used for any production builds.

BRANCH=none
BUG=none
TEST=make BOARD=nucleo-f412zg
     make BOARD=nucleo-f412zg flash
     minicom -D/dev/ttyACM0

Change-Id: Ic1150152adbef9ed3f81aafb007be747b2c436af
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1970642
Reviewed-by: Jett Rink <jettrink@chromium.org>
Commit-Queue: Craig Hesling <hesling@chromium.org>
Tested-by: Craig Hesling <hesling@chromium.org>

15 files changed, 526 insertions, 0 deletions

diff --git a/baseboard/nucleo-f412zg/base-board.c b/baseboard/nucleo-f412zg/base-board.c
new file mode 100644
index 0000000000..15e46f006e
--- /dev/null
+++ b/baseboard/nucleo-f412zg/base-board.c
@@ -0,0 +1,11 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "gpio.h"
+
+__overridable void button_event(enum gpio_signal signal)
+{
+}
diff --git a/baseboard/nucleo-f412zg/base-board.h b/baseboard/nucleo-f412zg/base-board.h
new file mode 100644
index 0000000000..7b69fde7c5
--- /dev/null
+++ b/baseboard/nucleo-f412zg/base-board.h
@@ -0,0 +1,200 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* Nucleo-F412ZG baseboard configuration */
+
+#ifndef __CROS_EC_BASE_BOARD_H
+#define __CROS_EC_BASE_BOARD_H
+
+/*-------------------------------------------------------------------------*
+ * Flash layout:
+ *
+ * +++++++++++++
+ * |    RO     |
+ * | ......... |
+ * |  Rollback | (two sectors)
+ * +-----------+
+ * |    RW     |
+ * |           |
+ * |           |
+ * |           |
+ * |           |
+ * +++++++++++++
+ *
+ * We adjust the following macros to accommodate a for a rollback, RO,
+ * and RW region of different sizes.
+ *
+ *-------------------------------------------------------------------------*/
+
+#undef _IMAGE_SIZE
+#undef CONFIG_ROLLBACK_OFF
+#undef CONFIG_ROLLBACK_SIZE
+#undef CONFIG_FLASH_PSTATE
+#undef CONFIG_FW_PSTATE_SIZE
+#undef CONFIG_FW_PSTATE_OFF
+#undef CONFIG_SHAREDLIB_SIZE
+#undef CONFIG_RO_MEM_OFF
+#undef CONFIG_RO_STORAGE_OFF
+#undef CONFIG_RO_SIZE
+#undef CONFIG_RW_MEM_OFF
+#undef CONFIG_RW_STORAGE_OFF
+#undef CONFIG_RW_SIZE
+#undef CONFIG_EC_PROTECTED_STORAGE_OFF
+#undef CONFIG_EC_PROTECTED_STORAGE_SIZE
+#undef CONFIG_EC_WRITABLE_STORAGE_OFF
+#undef CONFIG_EC_WRITABLE_STORAGE_SIZE
+#undef CONFIG_WP_STORAGE_OFF
+#undef CONFIG_WP_STORAGE_SIZE
+
+#define CONFIG_FLASH_WRITE_SIZE STM32_FLASH_WRITE_SIZE_3300
+
+#define CONFIG_SHAREDLIB_SIZE   0
+
+#define CONFIG_RO_MEM_OFF       0
+#define CONFIG_RO_STORAGE_OFF   0
+#define CONFIG_RO_SIZE          (128 * 1024)
+
+/* EC rollback protection block */
+#define CONFIG_ROLLBACK_OFF (CONFIG_RO_MEM_OFF + CONFIG_RO_SIZE)
+#define CONFIG_ROLLBACK_SIZE (128 * 1024 * 2) /* 2 blocks of 128KB each */
+
+#define CONFIG_RW_MEM_OFF	(CONFIG_ROLLBACK_OFF + CONFIG_ROLLBACK_SIZE)
+#define CONFIG_RW_STORAGE_OFF	0
+#define CONFIG_RW_SIZE		(CONFIG_FLASH_SIZE -			\
+				(CONFIG_RW_MEM_OFF - CONFIG_RO_MEM_OFF))
+
+#define CONFIG_EC_PROTECTED_STORAGE_OFF         CONFIG_RO_MEM_OFF
+#define CONFIG_EC_PROTECTED_STORAGE_SIZE        CONFIG_RO_SIZE
+#define CONFIG_EC_WRITABLE_STORAGE_OFF          CONFIG_RW_MEM_OFF
+#define CONFIG_EC_WRITABLE_STORAGE_SIZE         CONFIG_RW_SIZE
+
+#define CONFIG_WP_STORAGE_OFF           CONFIG_EC_PROTECTED_STORAGE_OFF
+#define CONFIG_WP_STORAGE_SIZE          CONFIG_EC_PROTECTED_STORAGE_SIZE
+
+/*
+ * We want to prevent flash readout, and use it as indicator of protection
+ * status.
+ */
+#define CONFIG_FLASH_READOUT_PROTECTION_AS_PSTATE
+
+/*-------------------------------------------------------------------------*
+ * UART Console Setup
+ *-------------------------------------------------------------------------*/
+
+/* The UART console is on USART3 */
+#undef CONFIG_UART_CONSOLE
+#define CONFIG_UART_CONSOLE 3
+#undef CONFIG_UART_TX_BUF_SIZE
+#define CONFIG_UART_TX_BUF_SIZE 2048
+#define CONFIG_UART_TX_REQ_CH 4
+#define CONFIG_UART_RX_REQ_CH 4
+/* We don't currently use DMA. */
+#define CONFIG_UART_TX_DMA_PH DMAMUX1_REQ_USART3_TX
+#undef CONFIG_UART_TX_DMA
+#undef CONFIG_UART_RX_DMA
+
+/*-------------------------------------------------------------------------*
+ * Console Commands
+ *-------------------------------------------------------------------------*/
+
+#define CONFIG_CMD_FLASH
+#define CONFIG_CMD_IDLE_STATS
+
+/*-------------------------------------------------------------------------*
+ * Rollback Block
+ *-------------------------------------------------------------------------*/
+
+#define CONFIG_ROLLBACK
+#define CONFIG_MPU
+#define CONFIG_ROLLBACK_MPU_PROTECT
+
+/*
+ * We do not use any "locally" generated entropy: this is normally used
+ * to add local entropy when the main source of entropy is remote.
+ */
+#undef CONFIG_ROLLBACK_SECRET_LOCAL_ENTROPY_SIZE
+#ifdef SECTION_IS_RW
+	#undef CONFIG_ROLLBACK_UPDATE
+#endif
+
+/*-------------------------------------------------------------------------*
+ * RW Signature Verification
+ *-------------------------------------------------------------------------*/
+
+#ifdef SECTION_IS_RO
+	/* RO verifies the RW partition signature */
+	#define CONFIG_RSA
+	#define CONFIG_RWSIG
+#endif /* SECTION_IS_RO */
+#define CONFIG_RSA_KEY_SIZE 3072
+#define CONFIG_RSA_EXPONENT_3
+#define CONFIG_RWSIG_TYPE_RWSIG
+
+/*-------------------------------------------------------------------------*
+ * Watchdog
+ *-------------------------------------------------------------------------*/
+
+/*
+ * RW does slow compute, RO does slow flash erase.
+ */
+#undef CONFIG_WATCHDOG_PERIOD_MS
+#define CONFIG_WATCHDOG_PERIOD_MS 10000
+#define CONFIG_WATCHDOG_HELP
+
+/*-------------------------------------------------------------------------*
+ * Disable Features
+ *-------------------------------------------------------------------------*/
+
+#undef CONFIG_ADC
+#undef CONFIG_HIBERNATE
+#undef CONFIG_I2C
+#undef CONFIG_LID_SWITCH
+#undef CONFIG_TASK_PROFILING
+
+/*-------------------------------------------------------------------------*
+ * Other
+ *-------------------------------------------------------------------------*/
+
+#define CONFIG_AES
+#define CONFIG_AES_GCM
+#define CONFIG_DMA
+#define CONFIG_FPU
+#define CONFIG_HOST_COMMAND_STATUS
+#define CONFIG_MKBP_EVENT
+#define CONFIG_MKBP_USE_GPIO
+#define CONFIG_PRINTF_LEGACY_LI_FORMAT
+#define CONFIG_RNG
+#define CONFIG_SHA256
+#define CONFIG_SHA256_UNROLLED
+#define CONFIG_STM_HWTIMER32
+#define CONFIG_SUPPRESSED_HOST_COMMANDS \
+	EC_CMD_CONSOLE_SNAPSHOT, EC_CMD_CONSOLE_READ, EC_CMD_PD_GET_LOG_ENTRY
+#define CONFIG_WP_ACTIVE_HIGH
+
+#ifndef TEST_BUILD
+	/* TODO(hesling): Fix the illogical dependency between spi.c
+	 *                and host_command.c
+	 *
+	 * Currently, the chip/stm32/spi.c depends on functions defined in
+	 * common/host_command.c. When unit test builds use their own tasklist
+	 * without the HOSTCMD task, host_command.c is excluded from the build,
+	 * but chip/stm32/spi.c remains (because of CONFIG_SPI).
+	 * This triggers an undefined reference linker error.
+	 * The reproduce case:
+	 * - Allow CONFIG_SPI in TEST_BUILDs
+	 * - make BOARD=nucleo-h743zi tests
+	 */
+	#define CONFIG_SPI
+#endif
+
+#ifndef __ASSEMBLER__
+	/* Timer selection */
+	#define TIM_CLOCK32 2
+	#define TIM_WATCHDOG 16
+	#include "gpio_signal.h"
+	void button_event(enum gpio_signal signal);
+#endif /* !__ASSEMBLER__ */
+
+#endif /* __CROS_EC_BASE_BOARD_H */
diff --git a/baseboard/nucleo-f412zg/base-gpio.inc b/baseboard/nucleo-f412zg/base-gpio.inc
new file mode 100644
index 0000000000..4ebd99f91f
--- /dev/null
+++ b/baseboard/nucleo-f412zg/base-gpio.inc
@@ -0,0 +1,27 @@
+/*
+ * Copyright 2019 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/*
+ * Note that these pins map to the Nucleo-F412ZG.
+ */
+
+/* Inputs and Interrupts */
+GPIO_INT(SPI1_NSS,        PIN(A, 4),  GPIO_INPUT, spi_event)
+GPIO_INT(BTN1,            PIN(C, 13), GPIO_INT_BOTH, button_event)
+GPIO(WP,                  PIN(B, 8),  GPIO_INPUT) /* Not same as bloonchipper */
+
+/* Outputs */
+GPIO(EC_INT_L,            PIN(A, 1),  GPIO_OUT_HIGH)
+GPIO(LED1,                PIN(B, 0),  GPIO_OUT_LOW) /* Green */
+GPIO(LED2,                PIN(B, 7),  GPIO_OUT_LOW) /* Blue */
+GPIO(LED3,                PIN(B, 14), GPIO_OUT_LOW) /* Red */
+
+UNIMPLEMENTED(ENTERING_RW)
+
+/* USART3: PD8/PD9 (TX/RX) */
+ALTERNATE(PIN_MASK(D, 0x0300), GPIO_ALT_USART,  MODULE_UART, GPIO_PULL_UP)
+/* SPI1 slave from the AP: PA4/5/6/7 (CS/CLK/MISO/MOSI) */
+ALTERNATE(PIN_MASK(A, 0x00f0), GPIO_ALT_SPI, MODULE_SPI,  0)
diff --git a/baseboard/nucleo-f412zg/build.mk b/baseboard/nucleo-f412zg/build.mk
new file mode 100644
index 0000000000..1456331fec
--- /dev/null
+++ b/baseboard/nucleo-f412zg/build.mk
@@ -0,0 +1,14 @@
+# -*- makefile -*-
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Nucleo-F412ZG baseboard specific files build
+#
+
+# the IC is STmicro STM32F412
+CHIP:=stm32
+CHIP_FAMILY:=stm32f4
+CHIP_VARIANT:=stm32f412
+
+baseboard-y=base-board.o
diff --git a/baseboard/nucleo-f412zg/openocd-flash.cfg b/baseboard/nucleo-f412zg/openocd-flash.cfg
new file mode 100644
index 0000000000..3333d1163a
--- /dev/null
+++ b/baseboard/nucleo-f412zg/openocd-flash.cfg
@@ -0,0 +1,14 @@
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+source [find board/st_nucleo_f4.cfg]
+
+gdb_port 0
+tcl_port 0
+telnet_port 0
+init
+reset halt
+flash write_image erase $BUILD_DIR/ec.bin 0x08000000
+reset
+shutdown
diff --git a/baseboard/nucleo-f412zg/openocd.cfg b/baseboard/nucleo-f412zg/openocd.cfg
new file mode 100644
index 0000000000..589d4400f4
--- /dev/null
+++ b/baseboard/nucleo-f412zg/openocd.cfg
@@ -0,0 +1,9 @@
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+
+source [find board/st_nucleo_f4.cfg]
+
+# Enabled EC task context support
+# This is supported by the upstream OpenOCD
+$_TARGETNAME configure -rtos Chromium-EC
diff --git a/board/nucleo-f412zg/README.md b/board/nucleo-f412zg/README.md
new file mode 100644
index 0000000000..fcdd5e40df
--- /dev/null
+++ b/board/nucleo-f412zg/README.md
@@ -0,0 +1,85 @@
+# Nucleo F412ZG
+
+This is a simpler EC example for the ST Nucleo F412ZG
+development board.
+
+# Quick Start
+
+The Nucleo dev boards have lots of developer friendly features,
+like an in-circuit debugger/programmer/UART-bridge, programmable
+LEDs, and a button, to name a few.
+
+The built-in debugger can be connected to using a Micro USB cable.
+It provides three great interfaces to the host.
+1. Mass storage interface for drag-drop programming
+2. Full ST-Link in-circuit debugger
+3. UART bridge for logs/consoles
+
+We will use a few of these interfaces below to program and interact
+with out Nucleo dev board.
+
+## Build
+
+```bash
+make BOARD=nucleo-f412zg -j
+```
+
+## Program
+
+The easiest way to flash the Nucleo board is to Copy-Paste/Drag-Drop
+the firmware image onto the exposed mass storage drive.
+
+Open a file browser and `Copy` the file in `build/nucleo-f412zg/ec.bin`.
+Now, find the removable storage that the Nucleo device has presented,
+and `Paste` the file into the directory.
+
+## Interact
+
+After the Nucelo finishes programming, you can open the EC console.
+On GNU/Linux, this is mapped to `/dev/ttyACM0`.
+
+Install `minicom` and issue the following command:
+
+```bash
+minicom -D/dev/ttyACM0
+```
+
+# Unit Testing
+
+A fun EC feature is that unit tests can be run on-device.
+
+This is made possible by an alternative build rule that generates a
+test image per unit test. These test images use a unit test specific taskset
+and console command to trigger them.
+
+## Create
+
+To enable an existing unit test, add it to the [build.mk](build.mk)'s
+`test-list-y` variable.
+
+See the main [README.md](/README.md) on how to write a new unit test.
+
+## Build
+
+To build all unit test images for this board, run the following command:
+
+```bash
+make BOARD=nucleo-f412zg tests
+```
+
+You can build a specific unit test image by changing `tests` to `test-aes`,
+for the `aes` unit test.
+
+## Flash
+
+Copy/paste the `build/nucleo-f412zg/${TEST}/${TEST}.bin` file to the
+Nucleo's mass storage drive, where `${TEST}` is the name of the unit test,
+like `aes`.
+
+## Run
+
+1. Connect to UART console
+   ```bash
+   minicom -D/dev/ttyACM0
+   ```
+2. Run the `runtest` command
\ No newline at end of file
diff --git a/board/nucleo-f412zg/board.c b/board/nucleo-f412zg/board.c
new file mode 100644
index 0000000000..e06408c404
--- /dev/null
+++ b/board/nucleo-f412zg/board.c
@@ -0,0 +1,64 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "common.h"
+#include "console.h"
+#include "gpio.h"
+#include "hooks.h"
+#include "registers.h"
+#include "spi.h"
+#include "system.h"
+#include "task.h"
+#include "util.h"
+
+/**
+ * Disable restricted commands when the system is locked.
+ *
+ * @see console.h system.c
+ */
+int console_is_restricted(void)
+{
+	return system_is_locked();
+}
+
+static void ap_deferred(void)
+{
+	/*
+	 * in S3:   SLP_S3_L is 0 and SLP_S0_L is X.
+	 * in S0ix: SLP_S3_L is X and SLP_S0_L is 0.
+	 * in S0:   SLP_S3_L is 1 and SLP_S0_L is 1.
+	 * in S5/G3, the FP MCU should not be running.
+	 */
+	int running = gpio_get_level(GPIO_PCH_SLP_S3_L)
+			&& gpio_get_level(GPIO_PCH_SLP_S0_L);
+
+	if (running) { /* S0 */
+		disable_sleep(SLEEP_MASK_AP_RUN);
+		hook_notify(HOOK_CHIPSET_RESUME);
+	} else { /* S0ix/S3 */
+		hook_notify(HOOK_CHIPSET_SUSPEND);
+		enable_sleep(SLEEP_MASK_AP_RUN);
+	}
+}
+DECLARE_DEFERRED(ap_deferred);
+
+/* PCH power state changes */
+static void slp_event(enum gpio_signal signal)
+{
+	hook_call_deferred(&ap_deferred_data, 0);
+}
+
+#include "gpio_list.h"
+
+/* Initialize board. */
+static void board_init(void)
+{
+	/* Enable interrupt on PCH power signals */
+	gpio_enable_interrupt(GPIO_PCH_SLP_S3_L);
+	gpio_enable_interrupt(GPIO_PCH_SLP_S0_L);
+	/* enable the SPI slave interface if the PCH is up */
+	hook_call_deferred(&ap_deferred_data, 0);
+}
+DECLARE_HOOK(HOOK_INIT, board_init, HOOK_PRIO_DEFAULT);
diff --git a/board/nucleo-f412zg/board.h b/board/nucleo-f412zg/board.h
new file mode 100644
index 0000000000..331fa29578
--- /dev/null
+++ b/board/nucleo-f412zg/board.h
@@ -0,0 +1,25 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/* STM32F412 */
+
+#ifndef __BOARD_H
+#define __BOARD_H
+
+/* Baseboard features */
+#include "base-board.h"
+
+#undef CONFIG_SYSTEM_UNLOCKED
+
+/*
+ * These allow console commands to be flagged as restricted.
+ * Restricted commands will only be permitted to run when
+ * console_is_restricted() returns false.
+ * See console_is_restricted's definition in board.c.
+ */
+#define CONFIG_CONSOLE_COMMAND_FLAGS
+#define CONFIG_RESTRICTED_CONSOLE_COMMANDS
+
+#endif /* __BOARD_H */
diff --git a/board/nucleo-f412zg/build.mk b/board/nucleo-f412zg/build.mk
new file mode 100644
index 0000000000..8e58009d96
--- /dev/null
+++ b/board/nucleo-f412zg/build.mk
@@ -0,0 +1,12 @@
+# Copyright 2020 The Chromium OS Authors. All rights reserved.
+# Use of this source code is governed by a BSD-style license that can be
+# found in the LICENSE file.
+#
+# Board specific files build
+
+BASEBOARD:=nucleo-f412zg
+
+board-y=board.o
+
+# Enable on device tests
+test-list-y=aes sha256 sha256_unrolled
diff --git a/board/nucleo-f412zg/dev_key.pem b/board/nucleo-f412zg/dev_key.pem
new file mode 100644
index 0000000000..1eb0d88b78
--- /dev/null
+++ b/board/nucleo-f412zg/dev_key.pem
@@ -0,0 +1,39 @@
+-----BEGIN RSA PRIVATE KEY-----
+MIIG4wIBAAKCAYEAwLY2WYJasnLc/5iNin8L7Sxv/JkAwGWwEc3gJDMbHwgDYmm0
+V0pA1yKIKdcMsCLEh8VmI9JClgOdn9G9H0UXjtfWmszF8a9TtnrDcSJFBV/cxNs5
+CwxhQrcHmjSqpvhiDBFNyPEECPzg/s+Us7HHw9LaR61TBCY8/KDSHZoULx5m2n74
+xW5cJsxCmK/q8vQXYy+dhJzsCkgYOmubFyuHYn2CoNPBGaBLCiysD3ZbyxcJ+gl4
+NFN6MvD/fK0AufailWIskGJvDQmsJn+KBdNERaU31rHf6xqsq8wviYvSDtZk/QaI
+r9rWf7o48mQhDgB3o/3GEpL1ptWetmT1ZquqisCH0vh180jPDCmJl6t9xR2piJr8
+Hudq4STiE1++olFmwx/T6GCfy2fYMH8UD9ZrWvmD46V/2HGOJYfyWig0VyHN+QPr
+ZKtCbjgCyJCzxRQ8NTdmHyqyguwEcsHB20gpOVLknA3QB8VFIWzz4ZdNqksP6nxB
+PDZVKrIQNmUEkJZnAgEDAoIBgQCAeXmRAZHMTJNVEF5cVLKeHZ/9u1XVmSAL3pVt
+d2dqBVeW8SLk3Cs6FwVxOgh1bIMFLkQX4YG5V75qi9NqLg+0j+RnMy6hH40kUdeg
+wYNY6pMt53tcsuuBz1pmzccZ+uwIC4kwoK1bU0Cp37h3y9qCjJGFHjdYGX39wIwT
+vA10vu88VKXY9D1vMtcQdUdMorpCH75YaJ1cMBAm8mdkx6+W/lcV4oC7wDIGyHK0
++ZKHZLFRW6V4N6bMoKpTHgB7+cCQfQaycUvp0eFq2Y1FMiFGcJmg1VXxn0DVtMfp
+6EMZSb6vEsFt5xR7twVKgdKVWMErchvkFR0G1r4p2c83MknQgml34TfmDRIhO9O6
+Vz914sZPK4DiGejYQlyGxm2bcKd9OpBFRZKAdEKYyPbJPTxjwY1ZcmiMaWju3YGa
+MLuT+ixkoV+aeusm/oEfha9h0HF7CuCplFo2onP7L/9myyAkC6GsAyeZICMZV5yn
+xNXR4UHDyMI6TWoo1ui8RY8Fg8sCgcEA6AqRnCJhc1WZL9O+JxmzYVok0sgvzqRw
+N6ZhDMC4vaIVHxzPsVBRXgqA+67mA8d7afNzN6uzO+gnkkKwrdPDpUeLcs1M72wK
+mps1iRFl7jKV/QVlUOTbd1bh0DTWkF3QCOinloueLqh7DAZ8Yewjw+Svg8esQVD6
+6g68PlegGnCLMTPN29G2al+4ucNJ8PflulOdzzodU4dZf/8EnUsXxGaluJrv0vz2
+oRCsClqXeJ0yu1Vuh2/fcSCPz3hjTi9PAoHBANScEOiWG7r5QNZld/buXvqiLJKp
+rzIHWzOWop3utKtFsddNltmv5mgdMAbyfyoz2njfKQTHluCrWeVbjeYMeCy1XixZ
+VSrJKT+0lncXOKYW6hTUVXrbsiVqdXkBQ6jKm35fU+nspdwQ+T9LJYAObQFygFmy
+NsSCddUs87SHet66ADDeDiEhK0laiF+E4sFjrEJTd1GSDd1w/Pn6viPMYT7azGFu
+JM8YGdpY3NuVdXbb+ol5r11SVnxPI0yESrohaQKBwQCasbZoFuuiORDKjSlvZneW
+PBiMhXU0baAlGZYIgHspFri/aIp2NYuUBwCnye6tL6eb96IlHSIn8BphgcsejS0Y
+2lz3M4ifnVxnEiOwtkP0IblTWO417eek5JaKzeRgPoqwmxpkXRQfGvyyrv2WnW0t
+Qx+tL8gri1HxXygpj8ARoFzLd96Si87xlSXRLNv1+pkm4mk00WjiWjuqqgMTh2Ut
+mcPQZ0qMqKRrYHKxkbpQaMx8458E9T+gwF/fpZeJdN8CgcEAjb1gmw69J1DV5EOl
+T0mUpxbIYcZ0zATnd7nBvp8jHNkhOjO55nVERWjKr0xUxs08UJTGAy+56xzmmOez
+7rL6yHjpcuY4xzDGKnhkT2TQbrnxYzg4/JJ2w5xOUKuCcIcSVD+NRp3D6AtQ1NzD
+qrRIq6Gq5nbPLaxOjh33za+nPyaqyz60FhYc25GwP63sgO0dgYz6NmFek6Copqcp
+bTLrfzyIQPQYihARPDs957j4+ef8W6Z06OGO/YoXiFgx0WubAoHAYEw+laK7DHcu
+83aIYtzAMqo15axtIyxfb0RTAKqzBrtlhNO/7TfHTrSuGpIj9DWXbPj8X8UZZkZH
+O8w5NIrQB6fo5OmS1NnZCWDYEd7yGO/8vARvDLriVZ1lykIrP3ZkCEuRo+mVMtcP
+9J3otNKcnnyAlTqZnHgqlW0upMQXiHCWKHHqXUTG0KsGFu6qHPQBqwQ/k5qD+Osv
+tJS8v/ziA33WUHm2OyFgsLNW1tBjkLCDiYJD24/B+3Rc5/fic31r
+-----END RSA PRIVATE KEY-----
diff --git a/board/nucleo-f412zg/ec.tasklist b/board/nucleo-f412zg/ec.tasklist
new file mode 100644
index 0000000000..896eb2fdb3
--- /dev/null
+++ b/board/nucleo-f412zg/ec.tasklist
@@ -0,0 +1,13 @@
+/* Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+/**
+ * See CONFIG_TASK_LIST in config.h for details.
+ */
+#define CONFIG_TASK_LIST \
+	TASK_ALWAYS_RO(RWSIG, rwsig_task, NULL, 1280) \
+	TASK_ALWAYS(HOOKS, hook_task, NULL, 1024) \
+	TASK_ALWAYS(HOSTCMD, host_command_task, NULL, 4096) \
+	TASK_ALWAYS(CONSOLE, console_task, NULL, CONSOLE_TASK_STACK_SIZE)
diff --git a/board/nucleo-f412zg/gpio.inc b/board/nucleo-f412zg/gpio.inc
new file mode 100644
index 0000000000..57f78203ba
--- /dev/null
+++ b/board/nucleo-f412zg/gpio.inc
@@ -0,0 +1,11 @@
+/*
+ * Copyright 2020 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include "base-gpio.inc"
+
+/* Interrupts */
+GPIO_INT(PCH_SLP_S0_L,    PIN(A, 8), GPIO_INT_BOTH, slp_event)
+GPIO_INT(PCH_SLP_S3_L,    PIN(B, 6), GPIO_INT_BOTH, slp_event)
diff --git a/board/nucleo-f412zg/openocd-flash.cfg b/board/nucleo-f412zg/openocd-flash.cfg
new file mode 120000
index 0000000000..bafbe75704
--- /dev/null
+++ b/board/nucleo-f412zg/openocd-flash.cfg
@@ -0,0 +1 @@
+../../baseboard/nucleo-f412zg/openocd-flash.cfg
\ No newline at end of file
diff --git a/board/nucleo-f412zg/openocd.cfg b/board/nucleo-f412zg/openocd.cfg
new file mode 120000
index 0000000000..29e0be4ba2
--- /dev/null
+++ b/board/nucleo-f412zg/openocd.cfg
@@ -0,0 +1 @@
+../../baseboard/nucleo-f412zg/openocd.cfg
\ No newline at end of file