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| author | Sooraj Govindan <sooraj.govindan@intel.com> | 2020-02-13 17:18:11 +0530 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2020-02-19 21:57:58 +0000 |
| commit | a0ce3a44ee73185c03031a2364376dece6e778b6 (patch) | |
| tree | 7ee577004498a658fedef0d3873862964b2016b6 | |
| parent | 2396f0e9bcd6fe2ac3fa60920771882299c2d7e5 (diff) | |
| download | chrome-ec-a0ce3a44ee73185c03031a2364376dece6e778b6.tar.gz | |
power/icelake: JSL: add wait loop for receiving ALL_SYS_PWRGD
In some boot cycles, identified a case where PG_DRAM_OD
not getting SET when EC already transitioned to S0.
PG_DRAM_OD taking around 5+ms to get SET, after SLP_S3_L SET.
In such cases, intel_x86_get_pg_ec_all_sys_pwrgd() returns 0
and PCH_SYS_PWROK remaining as 0.
BUG=b:147257114
BRANCH=None
TEST=make -j BOARD=waddledoo; flash waddledoo, verify that
DUT can boot to S0.
Change-Id: I09207c723d3d006e8a555c3c2d44aa6ed5cc027d
Signed-off-by: Sooraj Govindan <sooraj.govindan@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2054363
Tested-by: Sooraj Govindan <sooraj.govindan@intel.corp-partner.google.com>
Reviewed-by: Aseda Aboagye <aaboagye@chromium.org>
Commit-Queue: Aseda Aboagye <aaboagye@chromium.org>
| -rw-r--r-- | power/icelake.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/power/icelake.c b/power/icelake.c index c020b5541f..62e3ccbc8e 100644 --- a/power/icelake.c +++ b/power/icelake.c @@ -180,6 +180,9 @@ enum power_state power_handle_state(enum power_state state) static int dswpwrok_out = -1; int all_sys_pwrgd_in = intel_x86_get_pg_ec_all_sys_pwrgd(); int all_sys_pwrgd_out; +#ifdef CONFIG_CHIPSET_JASPERLAKE + int timeout_ms = 10; +#endif /* CONFIG_CHIPSET_JASPERLAKE */ /* Pass-through DSW_PWROK to ICL. */ if (dswpwrok_in != dswpwrok_out) { @@ -270,6 +273,14 @@ enum power_state power_handle_state(enum power_state state) #ifdef CONFIG_CHIPSET_JASPERLAKE case POWER_S3S0: GPIO_SET_LEVEL(GPIO_EN_VCCIO_EXT, 1); + /* Now wait for ALL_SYS_PWRGD. */ + while (!intel_x86_get_pg_ec_all_sys_pwrgd() && + (timeout_ms > 0)) { + msleep(1); + timeout_ms--; + }; + if (!timeout_ms) + CPRINTS("ALL_SYS_PWRGD not received."); break; case POWER_S0S3: |