zephyr: mchp: Add shim system

Add shim layer system code

BUG=none
BRANCH=main
TEST=zmake testall

Signed-off-by: martin yan <martin.yan@microchip.corp-partner.google.com>
Change-Id: Ie80fff9e9ff5888690ed39da80a406997246238e
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/3546978
Reviewed-by: Denis Brockus <dbrockus@chromium.org>

2 files changed, 85 insertions, 0 deletions

diff --git a/zephyr/shim/chip/mchp/include/system_chip.h b/zephyr/shim/chip/mchp/include/system_chip.h
new file mode 100644
index 0000000000..a62ea4a525
--- /dev/null
+++ b/zephyr/shim/chip/mchp/include/system_chip.h
@@ -0,0 +1,29 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#ifndef __CROS_EC_SYSTEM_CHIP_H_
+#define __CROS_EC_SYSTEM_CHIP_H_
+
+#define SET_BIT(reg, bit)           ((reg) |= (0x1 << (bit)))
+#define CLEAR_BIT(reg, bit)         ((reg) &= (~(0x1 << (bit))))
+
+#undef IS_BIT_SET
+#define IS_BIT_SET(reg, bit)        (((reg) >> (bit)) & (0x1))
+
+/******************************************************************************/
+/* Optional M4 Registers */
+#define CPU_MPU_CTRL		REG32(0xE000ED94)
+#define CPU_MPU_RNR		REG32(0xE000ED98)
+#define CPU_MPU_RBAR		REG32(0xE000ED9C)
+#define CPU_MPU_RASR		REG32(0xE000EDA0)
+
+void system_download_from_flash(uint32_t srcAddr, uint32_t dstAddr,
+				uint32_t size, uint32_t exeAddr);
+
+/* Begin and end address for little FW; defined in linker script */
+extern unsigned int __flash_lplfw_start;
+extern unsigned int __flash_lplfw_end;
+
+#endif /* __CROS_EC_SYSTEM_CHIP_H_ */
diff --git a/zephyr/shim/chip/mchp/system.c b/zephyr/shim/chip/mchp/system.c
new file mode 100644
index 0000000000..e7241ff2bf
--- /dev/null
+++ b/zephyr/shim/chip/mchp/system.c
@@ -0,0 +1,56 @@
+/* Copyright 2022 The Chromium OS Authors. All rights reserved.
+ * Use of this source code is governed by a BSD-style license that can be
+ * found in the LICENSE file.
+ */
+
+#include <drivers/bbram.h>
+#include <logging/log.h>
+
+#include "system.h"
+#include "system_chip.h"
+
+LOG_MODULE_REGISTER(shim_xec_system, LOG_LEVEL_ERR);
+
+static void chip_bbram_status_check(void)
+{
+	const struct device *bbram_dev;
+	int res;
+
+	bbram_dev = DEVICE_DT_GET(DT_NODELABEL(bbram));
+	if (!device_is_ready(bbram_dev)) {
+		LOG_ERR("Error: device %s is not ready", bbram_dev->name);
+		return;
+	}
+
+	res = bbram_check_invalid(bbram_dev);
+	if (res != 0 && res != -ENOTSUP)
+		LOG_INF("VBAT power drop!");
+}
+
+void system_mpu_config(void)
+{
+	/* Reseve for future use */
+}
+
+static int chip_system_init(const struct device *unused)
+{
+	ARG_UNUSED(unused);
+
+	/*
+	 * Check BBRAM power status.
+	 */
+	chip_bbram_status_check();
+
+	system_mpu_config();
+
+	return 0;
+}
+/*
+ * The priority should be lower than CROS_BBRAM_MCHP_INIT_PRIORITY.
+ */
+#if (CONFIG_CROS_SYSTEM_XEC_PRE_INIT_PRIORITY <= CONFIG_BBRAM_INIT_PRIORITY)
+#error CONFIG_CROS_SYSTEM_XEC_PRE_INIT_PRIORITY must greater than \
+	CONFIG_BBRAM_INIT_PRIORITY
+#endif
+SYS_INIT(chip_system_init, PRE_KERNEL_1,
+	 CONFIG_CROS_SYSTEM_XEC_PRE_INIT_PRIORITY);