diff options
| author | Alec Berg <alecaberg@chromium.org> | 2014-06-11 16:45:35 -0700 |
|---|---|---|
| committer | chrome-internal-fetch <chrome-internal-fetch@google.com> | 2014-06-12 04:31:23 +0000 |
| commit | dcd905802b20e2c32c3baae4693d06013f003732 (patch) | |
| tree | f4031baabbdf3074eb24d1d019b84e213e157279 | |
| parent | bc50751dbe3c9aa86e4ea1a186e6602171349f93 (diff) | |
| download | chrome-ec-dcd905802b20e2c32c3baae4693d06013f003732.tar.gz | |
samus_pd: add PCH inputs to GPIO list
Add PCH inputs to GPIO list but don't enable interrupt.
BUG=none
BRANCH=none
TEST=make -j BOARD=samus_pd
Change-Id: Ife43375f8e8369516d9b363a39f9b3b9ab8a11ef
Signed-off-by: Alec Berg <alecaberg@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203528
Reviewed-by: Vincent Palatin <vpalatin@chromium.org>
| -rw-r--r-- | board/samus_pd/board.c | 8 | ||||
| -rw-r--r-- | board/samus_pd/board.h | 3 |
2 files changed, 11 insertions, 0 deletions
diff --git a/board/samus_pd/board.c b/board/samus_pd/board.c index 8da5297546..d689a42306 100644 --- a/board/samus_pd/board.c +++ b/board/samus_pd/board.c @@ -27,6 +27,11 @@ void bc12_evt(enum gpio_signal signal) ccprintf("PERICOM %d!\n", signal); } +void pch_evt(enum gpio_signal signal) +{ + ccprintf("PCH change %d!\n", signal); +} + void board_config_pre_init(void) { /* enable SYSCFG clock */ @@ -55,6 +60,9 @@ const struct gpio_info gpio_list[] = { {"USB_C1_VBUS_WAKE", GPIO_F, (1<<2), GPIO_INT_BOTH, vbus_evt}, {"USB_C0_BC12_INT_L", GPIO_B, (1<<0), GPIO_INT_FALLING, bc12_evt}, {"USB_C1_BC12_INT_L", GPIO_C, (1<<1), GPIO_INT_FALLING, bc12_evt}, + {"PCH_SLP_S0_L", GPIO_C, (1<<14), GPIO_INT_BOTH, pch_evt}, + {"PCH_SLP_S3_L", GPIO_C, (1<<15), GPIO_INT_BOTH, pch_evt}, + {"PCH_SLP_S5_L", GPIO_D, (1<<7), GPIO_INT_BOTH, pch_evt}, /* PD RX/TX */ {"USB_C0_CC1_PD", GPIO_A, (1<<0), GPIO_ANALOG, NULL}, diff --git a/board/samus_pd/board.h b/board/samus_pd/board.h index 65218b5b57..42cfe6ce07 100644 --- a/board/samus_pd/board.h +++ b/board/samus_pd/board.h @@ -53,6 +53,9 @@ enum gpio_signal { GPIO_USB_C1_VBUS_WAKE, GPIO_USB_C0_BC12_INT_L, GPIO_USB_C1_BC12_INT_L, + GPIO_PCH_SLP_S0_L, + GPIO_PCH_SLP_S3_L, + GPIO_PCH_SLP_S5_L, /* PD RX/TX */ GPIO_USB_C0_CC1_PD, |