samus: Power sequence changes for P2 boards

- Wait for SLP_SUS to deassert before bringing up PP1050 to avoid
leakage when PP1050 is enabled before the PCH is ready.
- CPU PGOOD is now connected to RSMRST_L on PCH.  Configure this
GPIO as an output and hook it into the power sequencing.
- Add a "chipset_force_g3()" function to use for aborting G3->S5
transitions when there is an issue with a rail not coming up.

BUG=chrome-os-partner:29502
BRANCH=samus
TEST=build for samus, tested on reworked p1.9 board

Change-Id: Ib0251943864594ee89a4a9f2c71c45da2c01f44e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/203081
Reviewed-by: Alec Berg <alecaberg@chromium.org>

3 files changed, 38 insertions, 22 deletions

diff --git a/board/samus/board.c b/board/samus/board.c
index d5a9bead21..d0e6ea03a4 100644
--- a/board/samus/board.c
+++ b/board/samus/board.c
@@ -100,7 +100,6 @@ const struct gpio_info gpio_list[] = {
 	{"BOARD_VERSION1",       LM4_GPIO_Q, (1<<5), GPIO_INPUT, NULL},
 	{"BOARD_VERSION2",       LM4_GPIO_Q, (1<<6), GPIO_INPUT, NULL},
 	{"BOARD_VERSION3",       LM4_GPIO_Q, (1<<7), GPIO_INPUT, NULL},
-	{"CPU_PGOOD",            LM4_GPIO_C, (1<<4), GPIO_INPUT, NULL},
 	{"USB1_OC_L",            LM4_GPIO_E, (1<<7), GPIO_INPUT, NULL},
 	{"USB1_STATUS_L",        LM4_GPIO_E, (1<<6), GPIO_INPUT, NULL},
 	{"USB2_OC_L",            LM4_GPIO_E, (1<<0), GPIO_INPUT, NULL},
@@ -126,6 +125,7 @@ const struct gpio_info gpio_list[] = {
 	{"ENTERING_RW",          LM4_GPIO_D, (1<<3), GPIO_OUT_LOW, NULL},
 	{"LIGHTBAR_RESET_L",     LM4_GPIO_J, (1<<2), GPIO_ODR_LOW, NULL},
 	{"PCH_DPWROK",           LM4_GPIO_G, (1<<0), GPIO_OUT_LOW, NULL},
+	{"PCH_RSMRST_L",         LM4_GPIO_C, (1<<4), GPIO_OUT_LOW, NULL},
 	/*
 	 * HDA_SDO is technically an output, but we need to leave it as an
 	 * input until we drive it high.  So can't use open-drain (HI_Z).
diff --git a/board/samus/board.h b/board/samus/board.h
index 48b1a94be1..b9ac5c6cbe 100644
--- a/board/samus/board.h
+++ b/board/samus/board.h
@@ -109,7 +109,6 @@ enum gpio_signal {
 	GPIO_BOARD_VERSION1,       /* Board version stuffing resistor 1 */
 	GPIO_BOARD_VERSION2,       /* Board version stuffing resistor 2 */
 	GPIO_BOARD_VERSION3,       /* Board version stuffing resistor 3 */
-	GPIO_CPU_PGOOD,            /* Power good to the CPU */
 	GPIO_USB1_OC_L,            /* USB port overcurrent warning */
 	GPIO_USB1_STATUS_L,        /* USB charger port 1 status output */
 	GPIO_USB2_OC_L,            /* USB port overcurrent warning */
@@ -136,6 +135,7 @@ enum gpio_signal {
 	GPIO_ENTERING_RW,          /* Indicate when EC is entering RW code */
 	GPIO_LIGHTBAR_RESET_L,     /* Reset lightbar controllers */
 	GPIO_PCH_DPWROK,           /* Indicate when VccDSW is good */
+	GPIO_PCH_RSMRST_L,         /* Reset PCH resume power plane logic */
 
 	GPIO_PCH_HDA_SDO,          /* HDA_SDO signal to PCH; when high, ME
 				    * ignores security descriptor */
diff --git a/board/samus/power_sequence.c b/board/samus/power_sequence.c
index 914bd5268c..4fffe04907 100644
--- a/board/samus/power_sequence.c
+++ b/board/samus/power_sequence.c
@@ -70,6 +70,25 @@ void chipset_force_shutdown(void)
 	 * transitions to G3.
 	 */
 	gpio_set_level(GPIO_PCH_DPWROK, 0);
+	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
+}
+
+static void chipset_force_g3(void)
+{
+	CPRINTS("Forcing G3");
+
+	gpio_set_level(GPIO_PCH_PWROK, 0);
+	gpio_set_level(GPIO_SYS_PWROK, 0);
+	gpio_set_level(GPIO_PP1050_EN, 0);
+	gpio_set_level(GPIO_PP1200_EN, 0);
+	gpio_set_level(GPIO_PP1800_EN, 0);
+	gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
+	gpio_set_level(GPIO_PP5000_USB_EN, 0);
+	gpio_set_level(GPIO_PP5000_EN, 0);
+	gpio_set_level(GPIO_PCH_RSMRST_L, 0);
+	gpio_set_level(GPIO_PCH_DPWROK, 0);
+	gpio_set_level(GPIO_PP3300_DSW_EN, 0);
+	wireless_set_state(WIRELESS_OFF);
 }
 
 void chipset_reset(int cold_reset)
@@ -130,18 +149,7 @@ enum power_state power_chipset_init(void)
 			return POWER_S0;
 		} else {
 			/* Force all signals to their G3 states */
-			CPRINTS("forcing G3");
-			gpio_set_level(GPIO_PCH_PWROK, 0);
-			gpio_set_level(GPIO_SYS_PWROK, 0);
-			gpio_set_level(GPIO_PP1050_EN, 0);
-			gpio_set_level(GPIO_PP1200_EN, 0);
-			gpio_set_level(GPIO_PP1800_EN, 0);
-			gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
-			gpio_set_level(GPIO_PP5000_USB_EN, 0);
-			gpio_set_level(GPIO_PP5000_EN, 0);
-			gpio_set_level(GPIO_PCH_DPWROK, 0);
-			gpio_set_level(GPIO_PP3300_DSW_EN, 0);
-			wireless_set_state(WIRELESS_OFF);
+			chipset_force_g3();
 		}
 	}
 
@@ -217,8 +225,7 @@ enum power_state power_handle_state(enum power_state state)
 		while ((power_get_signals() & IN_PGOOD_PP5000) != 0) {
 			if (task_wait_event(SECOND) == TASK_EVENT_TIMER) {
 				CPRINTS("timeout waiting for PP5000");
-				gpio_set_level(GPIO_PP5000_EN, 0);
-				chipset_force_shutdown();
+				chipset_force_g3();
 				return POWER_G3;
 			}
 		}
@@ -228,20 +235,25 @@ enum power_state power_handle_state(enum power_state state)
 
 		/* Assert DPWROK */
 		gpio_set_level(GPIO_PCH_DPWROK, 1);
+		if (power_wait_signals(IN_PCH_SLP_SUS_DEASSERTED)) {
+			CPRINTS("timeout waiting for SLP_SUS to deassert");
+			chipset_force_g3();
+			return POWER_G3;
+		}
 
 		/* Enable PP1050 rail. */
 		gpio_set_level(GPIO_PP1050_EN, 1);
 
 		/* Wait for 1.05V to come up and CPU to notice */
-		if (power_wait_signals(IN_PGOOD_PP1050 |
-				     IN_PCH_SLP_SUS_DEASSERTED)) {
-			gpio_set_level(GPIO_PP1050_EN, 0);
-			gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
-			gpio_set_level(GPIO_PP5000_EN, 0);
-			chipset_force_shutdown();
+		if (power_wait_signals(IN_PGOOD_PP1050)) {
+			CPRINTS("timeout waiting for PP1050");
+			chipset_force_g3();
 			return POWER_G3;
 		}
 
+		/* Deassert RSMRST# */
+		gpio_set_level(GPIO_PCH_RSMRST_L, 1);
+
 		/* Wait 5ms for SUSCLK to stabilize */
 		msleep(5);
 
@@ -382,10 +394,14 @@ enum power_state power_handle_state(enum power_state state)
 		/* Deassert DPWROK */
 		gpio_set_level(GPIO_PCH_DPWROK, 0);
 
+		/* Assert RSMRST# */
+		gpio_set_level(GPIO_PCH_RSMRST_L, 0);
+
 		/* Turn off power rails enabled in S5 */
 		gpio_set_level(GPIO_PP1050_EN, 0);
 		gpio_set_level(GPIO_PP3300_DSW_GATED_EN, 0);
 		gpio_set_level(GPIO_PP5000_EN, 0);
+
 		/* Disable 3.3V DSW */
 		gpio_set_level(GPIO_PP3300_DSW_EN, 0);
 		return POWER_G3;