diff options
| author | Divya Jyothi <divya.jyothi@intel.com> | 2015-02-04 18:29:58 -0800 |
|---|---|---|
| committer | ChromeOS Commit Bot <chromeos-commit-bot@chromium.org> | 2015-02-09 18:34:05 +0000 |
| commit | 68106334549fbae4d39b81f34c310198f7996ec1 (patch) | |
| tree | 64d235a54e65f4ccef0fe8a1a6091abc785628e1 | |
| parent | ce8266fd558425807226884068931fd66b0ed009 (diff) | |
| download | chrome-ec-68106334549fbae4d39b81f34c310198f7996ec1.tar.gz | |
Strago: Flash Mapping set up for SPI Flash.
- MEC1322 loads code into internal RAM from SPi Flash.
Since Flash can be any size the RO and RW images
placed at the end of 256k sector of flash.
- Vboot Hash calculation supported for RW image in
SPI Flash.
BUG=None
TEST=make -j buildall
BRANCH=strago-mec
Change-Id: I13e1fe0944cf7b4ac0d6dcb0a421b0bc7bca5b81
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/246393
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
| -rw-r--r-- | chip/mec1322/config_chip.h | 19 | ||||
| -rw-r--r-- | common/vboot_hash.c | 27 | ||||
| -rw-r--r-- | include/config.h | 6 |
3 files changed, 46 insertions, 6 deletions
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h index 6de25fac3a..03aedb4e5e 100644 --- a/chip/mec1322/config_chip.h +++ b/chip/mec1322/config_chip.h @@ -73,9 +73,24 @@ /* TODO(crosbug.com/p/23796): why 2 sets of configs with the same numbers? */ #define CONFIG_FW_WP_RO_OFF CONFIG_FW_RO_OFF -#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_RO_SIZE +#define CONFIG_FW_WP_RO_SIZE CONFIG_FW_RO_SIZE -#define CONFIG_FLASH_BANK_SIZE 4 +#define CONFIG_FW_PSTATE_SIZE CONFIG_FW_RO_SIZE +#define CONFIG_FW_PSTATE_OFF (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE) +#define CONFIG_FLASH_BANK_SIZE 0x00000800 /* protect bank size */ + +/****************************************************************************/ + +/****************************************************************************/ +/* Flash Memory Mapping */ + +#define CONFIG_RO_WP_SPI_OFF 0x20000 +#define CONFIG_RO_SPI_OFF 0x20000 +#define CONFIG_RW_SPI_OFF 0 +#define CONFIG_RO_IMAGE_FLASHADDR (CONFIG_FLASH_BASE_SPI + \ + CONFIG_RO_SPI_OFF) +#define CONFIG_RW_IMAGE_FLASHADDR (CONFIG_FLASH_BASE_SPI + \ + CONFIG_RW_SPI_OFF) /****************************************************************************/ /* Customize the build */ diff --git a/common/vboot_hash.c b/common/vboot_hash.c index e7717e96db..10784dff70 100644 --- a/common/vboot_hash.c +++ b/common/vboot_hash.c @@ -14,6 +14,7 @@ #include "task.h" #include "timer.h" #include "util.h" +#include "vboot_hash.h" #include "watchdog.h" /* Console output macros */ @@ -40,7 +41,9 @@ static int want_abort; static int in_progress; static struct sha256_ctx ctx; - +#ifdef CONFIG_FLASH_SPI +static const uint8_t vbootbuf[CHUNK_SIZE]; +#endif /** * Abort hash currently in progress, and invalidate any completed hash. */ @@ -56,6 +59,22 @@ static void vboot_hash_abort(void) } } +static const uint8_t *get_next_chunk_data(uint32_t offset, + uint32_t nbytes) +{ +#ifdef CONFIG_FLASH_SPI + + flash_physical_read((CONFIG_RW_IMAGE_FLASHADDR + offset), + nbytes, (uint8_t *)vbootbuf); + + return vbootbuf; +#else + /* to avoid warning */ + nbytes = nbytes; + return (const uint8_t *)(CONFIG_FLASH_BASE + offset); +#endif +} + /** * Do next chunk of hashing work, if any. */ @@ -72,8 +91,10 @@ static void vboot_hash_next_chunk(void) /* Compute the next chunk of hash */ size = MIN(CHUNK_SIZE, data_size - curr_pos); - SHA256_update(&ctx, (const uint8_t *)(CONFIG_FLASH_BASE + - data_offset + curr_pos), size); + + SHA256_update(&ctx, + get_next_chunk_data(data_offset + curr_pos, size), + size); curr_pos += size; if (curr_pos >= data_size) { diff --git a/include/config.h b/include/config.h index 435a8889d0..90122ef2b2 100644 --- a/include/config.h +++ b/include/config.h @@ -545,7 +545,7 @@ /* Support programming on-chip flash */ #define CONFIG_FLASH - +#undef CONFIG_FLASH_SPI #undef CONFIG_FLASH_BANK_SIZE #undef CONFIG_FLASH_BASE #undef CONFIG_FLASH_ERASED_VALUE32 @@ -1409,4 +1409,8 @@ #error "CONFIG_AUX_TIMER_PERIOD_MS must be at least 2x HOOK_TICK_INTERVAL_MS" #endif +#if defined(CONFIG_FLASH_SPI) && defined(CONFIG_FLASH) +#error "Both CONFIG_FLASH_SPI and CONFIG_FLASH cannot be defined" +#endif + #endif /* __CROS_EC_CONFIG_H */ |