Strago: Enabled CONFIG_FLASH_SPI define

	- Fixed issue in function that returns the SPI base
	  offset

BUG=None
TEST=Tested on Braswell Ref Design
BRANCH=strago-mec

Change-Id: Ie63f560a44ac0ef5768c3c7036bf6c4ba0029d2c
Signed-off-by: Divya Jyothi <divya.jyothi@intel.com>
Reviewed-on: https://chromium-review.googlesource.com/246523
Reviewed-by: Shawn N <shawnn@chromium.org>
Commit-Queue: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>

5 files changed, 9 insertions, 6 deletions

diff --git a/board/mec1322_evb/gpio.inc b/board/mec1322_evb/gpio.inc
index 35baf9c77d..a2b425b915 100644..100755
--- a/board/mec1322_evb/gpio.inc
+++ b/board/mec1322_evb/gpio.inc
@@ -22,7 +22,7 @@ GPIO(SHD_CS0,    PORT(15), 0, GPIO_ODR_HIGH, NULL)
  * emulate anyway, to make it more convenient to debug other code.
  */
 UNIMPLEMENTED(RECOVERY_L)  /* Recovery signal from DOWN button */
-UNIMPLEMENTED(WP)          /* Write protect input */
+UNIMPLEMENTED(WP_L)          /* Write protect input */
 UNIMPLEMENTED(ENTERING_RW) /* EC entering RW code */
 
 ALTERNATE(PORT(16), 0x24,     1, MODULE_UART,    0) /* UART0 */
diff --git a/board/strago/gpio.inc b/board/strago/gpio.inc
index 4219d5cdc8..2ab25a924d 100644..100755
--- a/board/strago/gpio.inc
+++ b/board/strago/gpio.inc
@@ -82,6 +82,7 @@ GPIO(PCH_SLP_S3_L,      PORT(20), 6, GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP,
 GPIO(SUSPWRDNACK_SOC_EC,PORT(21), 0, GPIO_OUT_LOW,                              NULL)                   /* SUSPWRDNACK signal from EC to MOIC device*/
 GPIO(PCH_SLP_SX_L,      PORT(21), 1, GPIO_INT_BOTH_DSLEEP,                      NULL)                   /* Sleep SOIX signal from SOC to EC */
 
+UNIMPLEMENTED(WP_L)
 
 /* Alternate functions GPIO definition */
 ALTERNATE(PORT(16), 0x24,     1, MODULE_UART,          0) 			/* UART0 */
diff --git a/chip/mec1322/config_chip.h b/chip/mec1322/config_chip.h
index a9bac688c8..088c21a878 100755
--- a/chip/mec1322/config_chip.h
+++ b/chip/mec1322/config_chip.h
@@ -111,6 +111,8 @@
 #define CONFIG_FW_WP_RO_OFF         	CONFIG_FW_LOADER_OFF
 #define CONFIG_FW_WP_RO_SIZE        	(CONFIG_FW_LOADER_SIZE + \
 						CONFIG_FW_RO_SIZE)
+#define CONFIG_FW_PSTATE_SIZE   CONFIG_FW_RO_SIZE
+#define CONFIG_FW_PSTATE_OFF    (CONFIG_FW_RO_OFF + CONFIG_FW_RO_SIZE)
 
 /****************************************************************************/
 /* SPI Flash Memory Mapping */
@@ -141,7 +143,7 @@
 #define CONFIG_FPU
 #define CONFIG_SPI
 #define CONFIG_DMA
-
+#define CONFIG_FLASH_SPI
 #undef CONFIG_FLASH
 
 #endif  /* __CROS_EC_CONFIG_CHIP_H */
diff --git a/common/flash_spi.c b/common/flash_spi.c
index 319d25bdf4..902af792ae 100644..100755
--- a/common/flash_spi.c
+++ b/common/flash_spi.c
@@ -14,6 +14,8 @@
 #include "system.h"
 #include "util.h"
 #include "watchdog.h"
+/* Console output macros */
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
 
 /*
   * Buffer allocated to read data from spi Flash
@@ -30,9 +32,9 @@ uintptr_t flash_get_image_base_spi(enum system_image_copy_t copy)
 {
 	switch (copy) {
 	case SYSTEM_IMAGE_RO:
-		return CONFIG_RO_IMAGE_FLASHADDR;
+		return CONFIG_RO_SPI_OFF;
 	case SYSTEM_IMAGE_RW:
-		return CONFIG_RW_IMAGE_FLASHADDR;
+		return CONFIG_RW_SPI_OFF;
 	default:
 		return 0xffffffff;
 	}
@@ -125,7 +127,6 @@ int flash_physical_write(int offset, int size, const char *data)
 
 int flash_physical_read(int offset, int size, char *data)
 {
-
 	offset += CONFIG_FLASH_BASE_SPI;
 
 	/* Fail if offset, size, and data aren't at least word-aligned */
diff --git a/common/system.c b/common/system.c
index 8bc3dd8f80..d04716bf8e 100644..100755
--- a/common/system.c
+++ b/common/system.c
@@ -513,7 +513,6 @@ const char *system_get_version(enum system_image_copy_t copy)
 		system_get_image_base(system_get_image_copy()));
 #endif
 
-
 #ifdef CONFIG_FLASH_SPI
 	flash_physical_read(flash_get_image_base_spi(copy) +
 		version_offset, sizeof(version_data),