diff options
author | Jett Rink <jettrink@chromium.org> | 2018-09-14 08:28:01 -0600 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-17 21:34:54 -0700 |
commit | 02155e0b650dff1969484d250b6f10e1b3018757 (patch) | |
tree | 621991066255215a99b239dc2e3df4fe5fc59180 | |
parent | 1ceee0f64e386d3837ceab42044b838b4f0b2d68 (diff) | |
download | chrome-ec-02155e0b650dff1969484d250b6f10e1b3018757.tar.gz |
octopus: enable PSL for all NPCX variants
All NPCX variants support PSL mode in hardware now; enable this at the
baseboard level.
This is adding support for Bobba; other boards are unaffected
BRANCH=none
BUG=b:115677776
TEST=bobba goes into PSL
Change-Id: I38974371b101c42841e4f11ba72b466415c754d9
Signed-off-by: Jett Rink <jettrink@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/1227050
Commit-Ready: ChromeOS CL Exonerator Bot <chromiumos-cl-exonerator@appspot.gserviceaccount.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
-rw-r--r-- | baseboard/octopus/baseboard.h | 3 | ||||
-rw-r--r-- | baseboard/octopus/variant_ec_npcx796fb.c | 4 | ||||
-rw-r--r-- | board/bobba/gpio.inc | 20 | ||||
-rw-r--r-- | board/fleex/board.h | 3 | ||||
-rw-r--r-- | board/meep/board.h | 3 | ||||
-rw-r--r-- | board/phaser/board.h | 3 | ||||
-rw-r--r-- | board/yorp/board.h | 3 |
7 files changed, 24 insertions, 15 deletions
diff --git a/baseboard/octopus/baseboard.h b/baseboard/octopus/baseboard.h index e8160889eb..9311ab39ba 100644 --- a/baseboard/octopus/baseboard.h +++ b/baseboard/octopus/baseboard.h @@ -39,6 +39,9 @@ #define I2C_PORT_SENSOR NPCX_I2C_PORT7_0 #define I2C_ADDR_EEPROM 0xA0 + /* Enable PSL hibernate mode. */ + #define CONFIG_HIBERNATE_PSL + /* EC variant determines USB-C variant */ #define VARIANT_OCTOPUS_USBC_STANDALONE_TCPCS diff --git a/baseboard/octopus/variant_ec_npcx796fb.c b/baseboard/octopus/variant_ec_npcx796fb.c index 47fb14bfba..8d798fc5a7 100644 --- a/baseboard/octopus/variant_ec_npcx796fb.c +++ b/baseboard/octopus/variant_ec_npcx796fb.c @@ -20,10 +20,8 @@ const enum gpio_signal hibernate_wake_pins[] = { GPIO_LID_OPEN, GPIO_AC_PRESENT, GPIO_POWER_BUTTON_L, -#ifdef CONFIG_HIBERNATE_PSL - /* EC_RST_ODL needs to wake device if PSL hibernate mode is enabled. */ + /* EC_RST_ODL needs to wake device while in PSL hibernate. */ GPIO_EC_RST_ODL, -#endif }; const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins); diff --git a/board/bobba/gpio.inc b/board/bobba/gpio.inc index 8ec5bacf85..70f45ece2b 100644 --- a/board/bobba/gpio.inc +++ b/board/bobba/gpio.inc @@ -72,6 +72,20 @@ GPIO(EN_P3300_TRACKPAD_ODL, PIN(3, 3), GPIO_ODR_HIGH) GPIO(EC_BATT_PRES_L, PIN(E, 5), GPIO_INPUT) /* + * EC_RST_ODL acts as a wake source from PSL hibernate mode. However, it does + * not need to be an interrupt for normal EC operations. Thus, configure it as + * GPIO_INPUT with wake on low-to-high edge using GPIO_HIB_WAKE_HIGH so that PSL + * common code can configure PSL_IN correctly. + * + * Reason for choosing low-to-high edge for waking from hibernate is to avoid + * the double reset - one because of PSL_IN wake and other because of VCC1_RST + * being asserted. Also, it should be fine to have the EC in hibernate when H1 + * or servo wants to hold the EC in reset since VCC1 will be down and so entire + * EC logic (except PSL) as well as AP will be in reset. + */ +GPIO(EC_RST_ODL, PIN(0, 2), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH) + +/* * PCH_PROCHOT_ODL is primarily for monitoring the PROCHOT# signal which is * normally driven by the PMIC. The EC can also drive this signal in the event * that the ambient or charger temperature sensors exceeds their thresholds. @@ -144,3 +158,9 @@ ALTERNATE(PIN_MASK(4, 0x30), 0, MODULE_ADC, 0) /* ADC0-1 */ ALTERNATE(PIN_MASK(4, 0x02), 0, MODULE_ADC, 0) /* ADC4 */ ALTERNATE(PIN_MASK(F, 0x01), 0, MODULE_ADC, 0) /* ADC9 */ ALTERNATE(PIN_MASK(8, 0x01), 0, MODULE_PWM, 0) /* PWM3: KB_BL_PWM */ + +/* Power Switch Logic (PSL) inputs */ +ALTERNATE(PIN_MASK(D, 0x04), 0, MODULE_PMU, 0) /* GPIOD2 = LID_OPEN */ +ALTERNATE(PIN_MASK(0, 0x07), 0, MODULE_PMU, 0) /* GPIO00 = ACOK_OD, + GPIO01 = MECH_PWR_BTN_ODL + GPIO02 = EC_RST_ODL */ diff --git a/board/fleex/board.h b/board/fleex/board.h index 96cee33cff..8ccecb5f25 100644 --- a/board/fleex/board.h +++ b/board/fleex/board.h @@ -16,9 +16,6 @@ /* Optional features */ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */ -/* Enable PSL hibernate mode. */ -#define CONFIG_HIBERNATE_PSL - /* EC console commands */ #define CONFIG_CMD_ACCELS #define CONFIG_CMD_ACCEL_INFO diff --git a/board/meep/board.h b/board/meep/board.h index 2d8f06a45b..f3e14e85a5 100644 --- a/board/meep/board.h +++ b/board/meep/board.h @@ -13,9 +13,6 @@ #define VARIANT_OCTOPUS_CHARGER_ISL9238 #include "baseboard.h" -/* Enable PSL hibernate mode. */ -#define CONFIG_HIBERNATE_PSL - #define CONFIG_VOLUME_BUTTONS #define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL #define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL diff --git a/board/phaser/board.h b/board/phaser/board.h index 816fa72ba6..133226993b 100644 --- a/board/phaser/board.h +++ b/board/phaser/board.h @@ -13,9 +13,6 @@ #define VARIANT_OCTOPUS_CHARGER_ISL9238 #include "baseboard.h" -/* Enable PSL hibernate mode. */ -#define CONFIG_HIBERNATE_PSL - #define CONFIG_VOLUME_BUTTONS #define GPIO_VOLUME_UP_L GPIO_EC_VOLUP_BTN_ODL #define GPIO_VOLUME_DOWN_L GPIO_EC_VOLDN_BTN_ODL diff --git a/board/yorp/board.h b/board/yorp/board.h index ee5cb7bc20..b588ee4898 100644 --- a/board/yorp/board.h +++ b/board/yorp/board.h @@ -13,9 +13,6 @@ #define VARIANT_OCTOPUS_CHARGER_ISL9238 #include "baseboard.h" -/* Enable PSL hibernate mode. */ -#define CONFIG_HIBERNATE_PSL - /* Optional features */ #define CONFIG_SYSTEM_UNLOCKED /* Allow dangerous commands while in dev. */ |