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| author | Craig Hesling <hesling@chromium.org> | 2019-12-09 11:57:06 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2019-12-16 18:09:08 +0000 |
| commit | 5db9f5f19e99b00a0bc284c4989de8cac81bbf47 (patch) | |
| tree | f60f4bcb19e3016c48ea2018fe8ca99d54494e39 | |
| parent | d29c928cda0bf730e6d0a5762205b330dea09639 (diff) | |
| download | chrome-ec-5db9f5f19e99b00a0bc284c4989de8cac81bbf47.tar.gz | |
stm32f4: Fix SBF clear bit
The STM32F412 and STM32F446 reference manuals seem
to indicate that the SBF clear bit is actually bit 3.
BRANCH=hatch
BUG=none
TEST=make buildall -j
Change-Id: Ib98c5831f19355dfe3643c7d0b8258bd449d373b
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1958847
Reviewed-by: Daisuke Nojiri <dnojiri@chromium.org>
| -rw-r--r-- | chip/stm32/registers-stm32f4.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/chip/stm32/registers-stm32f4.h b/chip/stm32/registers-stm32f4.h index 84fcf1dff1..547656ffc5 100644 --- a/chip/stm32/registers-stm32f4.h +++ b/chip/stm32/registers-stm32f4.h @@ -602,7 +602,7 @@ #define STM32_PWR_RESET_CAUSE STM32_PWR_CSR #define RESET_CAUSE_SBF BIT(1) #define STM32_PWR_RESET_CAUSE_CLR STM32_PWR_CR -#define RESET_CAUSE_SBF_CLR BIT(2) +#define RESET_CAUSE_SBF_CLR BIT(3) /* --- Watchdogs --- */ |