diff options
author | Furquan Shaikh <furquan@chromium.org> | 2017-01-20 13:05:19 -0800 |
---|---|---|
committer | chrome-bot <chrome-bot@chromium.org> | 2017-01-23 03:48:09 -0800 |
commit | 38c5661f14f8a4be018e4b6e1641071c5f1fe866 (patch) | |
tree | f8aa3902ccf9956305473bac6b231158a3032c16 | |
parent | 625925d725301069d2d2630370e0b6974d3b9491 (diff) | |
download | chrome-ec-38c5661f14f8a4be018e4b6e1641071c5f1fe866.tar.gz |
eve: Select CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET
Also program EC_PLATFORM_RST as an out signal from the EC.
BUG=chrome-os-partner:61883
BRANCH=None
TEST=Compiles successfully for eve.
Change-Id: I41486e6050727ca822a27054244da3fed5ee3b7a
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/431194
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
-rw-r--r-- | board/eve/board.h | 1 | ||||
-rw-r--r-- | board/eve/gpio.inc | 2 |
2 files changed, 2 insertions, 1 deletions
diff --git a/board/eve/board.h b/board/eve/board.h index 78819a9970..87b527333e 100644 --- a/board/eve/board.h +++ b/board/eve/board.h @@ -54,6 +54,7 @@ /* SOC */ #define CONFIG_CHIPSET_SKYLAKE +#define CONFIG_CHIPSET_HAS_PLATFORM_PMIC_RESET #define CONFIG_CHIPSET_RESET_HOOK #define CONFIG_ESPI #define CONFIG_ESPI_VW_SIGNALS diff --git a/board/eve/gpio.inc b/board/eve/gpio.inc index 76b86a095a..1814b32684 100644 --- a/board/eve/gpio.inc +++ b/board/eve/gpio.inc @@ -35,7 +35,7 @@ GPIO(PCH_ACOK, PIN(5, 0), GPIO_ODR_LOW) /* ACOK to SOC */ GPIO(PCH_WAKE_L, PIN(A, 3), GPIO_ODR_HIGH) /* Wake SOC */ GPIO(PCH_RSMRST_L, PIN(7, 0), GPIO_OUT_LOW) /* RSMRST# to SOC */ GPIO(PCH_PWRBTN_L, PIN(4, 1), GPIO_ODR_HIGH) /* Power Button to SOC */ -GPIO(EC_PLATFORM_RST, PIN(A, 6), GPIO_INPUT) /* EC Reset from H1 */ +GPIO(EC_PLATFORM_RST, PIN(A, 6), GPIO_OUT_LOW) /* EC Reset to LDO_EN */ GPIO(SYS_RESET_L, PIN(6, 1), GPIO_ODR_HIGH) /* Cold Reset to SOC */ GPIO(PMIC_SLP_SUS_L, PIN(8, 5), GPIO_OUT_LOW) /* SLP_SUS# to PMIC */ GPIO(BATTERY_PRESENT_L, PIN(3, 4), GPIO_INPUT) /* Battery Present */ |