diff options
| author | Nick Sanders <nsanders@chromium.org> | 2018-03-06 19:00:22 -0800 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-03-12 15:24:39 -0700 |
| commit | 99bcab486dff32c646abed906cf37dfe68a6ead7 (patch) | |
| tree | 92d3376583c84c96acc20e6d30b9b72f47ee8d51 | |
| parent | a96fbd0c9722abed0891c95bf6accc51ebf4da6a (diff) | |
| download | chrome-ec-99bcab486dff32c646abed906cf37dfe68a6ead7.tar.gz | |
servo_micro: switch parity to 8 bit data
Parity defaulted to 7 bit data, but hammer wants 8 bit.
Change servo_micro to match.
BRANCH=servo-firmware
BUG=b:37513705
TEST=flash_ec -b hammer
Change-Id: I91cc126b03c99107084fb0d1d2e90031b2435fe2
Signed-off-by: Nick Sanders <nsanders@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/952677
Reviewed-by: Nicolas Boichat <drinkcat@chromium.org>
| -rw-r--r-- | chip/stm32/registers.h | 2 | ||||
| -rw-r--r-- | chip/stm32/usart.c | 11 |
2 files changed, 11 insertions, 2 deletions
diff --git a/chip/stm32/registers.h b/chip/stm32/registers.h index 3a549beb5f..251f63f1a6 100644 --- a/chip/stm32/registers.h +++ b/chip/stm32/registers.h @@ -459,6 +459,7 @@ #define STM32_USART_CR1_TXEIE (1 << 7) #define STM32_USART_CR1_PS (1 << 9) #define STM32_USART_CR1_PCE (1 << 10) +#define STM32_USART_CR1_M (1 << 12) #define STM32_USART_CR1_OVER8 (1 << 15) #define STM32_USART_CR2(base) STM32_USART_REG(base, 0x04) #define STM32_USART_CR2_SWAP (1 << 15) @@ -504,6 +505,7 @@ #define STM32_USART_CR1_TXEIE (1 << 7) #define STM32_USART_CR1_PS (1 << 9) #define STM32_USART_CR1_PCE (1 << 10) +#define STM32_USART_CR1_M (1 << 12) #define STM32_USART_CR1_UE (1 << 13) #define STM32_USART_CR1_OVER8 (1 << 15) /* STM32L only */ #define STM32_USART_CR2(base) STM32_USART_REG(base, 0x10) diff --git a/chip/stm32/usart.c b/chip/stm32/usart.c index 893303deaf..90be4f6194 100644 --- a/chip/stm32/usart.c +++ b/chip/stm32/usart.c @@ -127,6 +127,11 @@ int usart_get_parity(struct usart_config const *config) return 2; } +/* + * We only allow 8 bit word. CR1_PCE modifies parity enable, + * CR1_PS modifies even/odd, CR1_M modifies total word length + * to make room for parity. + */ void usart_set_parity(struct usart_config const *config, int parity) { uint32_t ue; @@ -141,7 +146,8 @@ void usart_set_parity(struct usart_config const *config, int parity) if (parity) { /* Set parity control enable. */ - STM32_USART_CR1(base) |= STM32_USART_CR1_PCE; + STM32_USART_CR1(base) |= + (STM32_USART_CR1_PCE | STM32_USART_CR1_M); /* Set parity select even/odd bit. */ if (parity == 2) STM32_USART_CR1(base) &= ~STM32_USART_CR1_PS; @@ -149,7 +155,8 @@ void usart_set_parity(struct usart_config const *config, int parity) STM32_USART_CR1(base) |= STM32_USART_CR1_PS; } else { STM32_USART_CR1(base) &= - ~(STM32_USART_CR1_PCE | STM32_USART_CR1_PS); + ~(STM32_USART_CR1_PCE | STM32_USART_CR1_PS | + STM32_USART_CR1_M); } /* Restore active state. */ |