glados: Make SLP_S0 a non-interrupt input pin

SLP_S0 can reside at an intermediate voltage even with the internal
pull-down. Eliminate interrupt storms by making this pin a
non-interrupt, which also necessitates making the pin a non-power
signal. This change will inhibit us from enabling S0ix later on glados.

BUG=chrome-os-partner:47617
BRANCH=None
TEST=Successfully power sequence on glados.

Change-Id: Ic8644ace136a984be300c6d7ac96be4cd1be40d0
Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/313346
Commit-Ready: Shawn N <shawnn@chromium.org>
Tested-by: Shawn N <shawnn@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alec Berg <alecaberg@chromium.org>

3 files changed, 9 insertions, 9 deletions

diff --git a/board/glados/board.c b/board/glados/board.c
index 490d8ebb52..74682a46fe 100644
--- a/board/glados/board.c
+++ b/board/glados/board.c
@@ -101,7 +101,6 @@ void tablet_mode_interrupt(enum gpio_signal signal)
 /* power signal list.  Must match order of enum power_signal. */
 const struct power_signal_info power_signal_list[] = {
 	{GPIO_RSMRST_L_PGOOD,    1, "RSMRST_N_PWRGD"},
-	{GPIO_PCH_SLP_S0_L,      1, "SLP_S0_DEASSERTED"},
 	{GPIO_PCH_SLP_S3_L,      1, "SLP_S3_DEASSERTED"},
 	{GPIO_PCH_SLP_S4_L,      1, "SLP_S4_DEASSERTED"},
 	{GPIO_PCH_SLP_SUS_L,     1, "SLP_SUS_DEASSERTED"},
diff --git a/board/glados/board.h b/board/glados/board.h
index 1be611b4f3..3f35b5c657 100644
--- a/board/glados/board.h
+++ b/board/glados/board.h
@@ -155,7 +155,6 @@ enum adc_channel {
 /* power signal definitions */
 enum power_signal {
 	X86_RSMRST_L_PWRGD = 0,
-	X86_SLP_S0_DEASSERTED,
 	X86_SLP_S3_DEASSERTED,
 	X86_SLP_S4_DEASSERTED,
 	X86_SLP_SUS_DEASSERTED,
diff --git a/board/glados/gpio.inc b/board/glados/gpio.inc
index 8bbc8d2801..6d97b5a047 100644
--- a/board/glados/gpio.inc
+++ b/board/glados/gpio.inc
@@ -14,13 +14,6 @@ GPIO_INT(POWER_BUTTON_L,    PIN(35), GPIO_INT_BOTH, power_button_interrupt)
 GPIO_INT(RSMRST_L_PGOOD,    PIN(63),  GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PCH_SLP_S4_L,      PIN(200), GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(PCH_SLP_S3_L,      PIN(206), GPIO_INT_BOTH, power_signal_interrupt)
-/*
- * This pulldown should be removed in future hardware followers. The signal
- * is pulled up in the SoC when the primary rails are on and/or ramping.
- * In order to not get interrupt storms there should be external logic
- * which makes this a true binary signal into the EC.
- */
-GPIO_INT(PCH_SLP_S0_L,      PIN(211), GPIO_INT_BOTH | GPIO_PULL_DOWN, power_signal_interrupt)
 GPIO_INT(PCH_SLP_SUS_L,     PIN(12),  GPIO_INT_BOTH, power_signal_interrupt)
 GPIO_INT(VOLUME_UP_L,       PIN(31),  GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
 GPIO_INT(VOLUME_DOWN_L,     PIN(47),  GPIO_INT_BOTH | GPIO_PULL_UP, button_interrupt)
@@ -36,6 +29,15 @@ GPIO_INT(PMIC_DPWROK,       PIN(133), GPIO_INT_BOTH, power_signal_interrupt)
 /* UART input */
 GPIO_INT(UART0_RX,          PIN(162), GPIO_INT_BOTH_DSLEEP | GPIO_PULL_UP, uart_deepsleep_interrupt)
 
+/*
+ * This pulldown should be removed and SLP_S0 should be enabled as a power
+ * signal interrupt in future hardware followers. The signal is pulled up in
+ * the SoC when the primary rails are on and/or ramping.
+ * In order to not get interrupt storms there should be external logic
+ * which makes this a true binary signal into the EC.
+ */
+GPIO(PCH_SLP_S0_L,          PIN(211), GPIO_INPUT | GPIO_PULL_DOWN)
+
 GPIO(PD_RST_L,              PIN(130), GPIO_ODR_HIGH)
 GPIO(USB2_OTG_ID,           PIN(13),  GPIO_ODR_LOW)
 /* I2C pins - these will be reconfigured for alternate function below */