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| author | Caveh Jalali <caveh@chromium.org> | 2021-03-01 19:19:15 -0800 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-04-13 04:48:55 +0000 |
| commit | 5db1d264c15124001bb34e6742e609ea28765d39 (patch) | |
| tree | cd5530f82b64b5b5aa4daf81f38b9ef00c0aab20 /baseboard/brya/baseboard.h | |
| parent | e61ad5e1d2ae5bf951f0c1e7b6486b23b77079cd (diff) | |
| download | chrome-ec-5db1d264c15124001bb34e6742e609ea28765d39.tar.gz | |
brya: Enable EC hibernate using PSL
This adds the wake source pin definitions needed by the NPCX9 chip
support code for brya board ID 1. Note that board ID 1 needs a rework on
VCC1_RST to prevent it from falsely waking the board.
BRANCH=none
BUG=b:183246197
TEST=booted same image on old and new rev. of board
Used "hibernate" on EC console hibernate the system. It woke
up immediately (b/183412004) with cause "hibernate" indicating
this was a PSL wake:
--- UART initialized after reboot ---
[Image: RO, brya_v2.0.8357-19a8f337db 2021-04-08 01:09:30 caveh@caveh]
[Reset cause: power-on hibernate wake-pin]
LID_OPEN was tested as a PSL wake source by artificially disabling
CONFIG_HIBERNATE_PSL_VCC1_RST_WAKEUP to eliminate VCC1 as a false
wake source.
Change-Id: If4cca6d1e20ddc3c422697e6838c9df0ddd8cb15
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2728679
Reviewed-by: Furquan Shaikh <furquan@chromium.org>
Diffstat (limited to 'baseboard/brya/baseboard.h')
| -rw-r--r-- | baseboard/brya/baseboard.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/baseboard/brya/baseboard.h b/baseboard/brya/baseboard.h index 981d33c7a9..4dd67b2976 100644 --- a/baseboard/brya/baseboard.h +++ b/baseboard/brya/baseboard.h @@ -35,6 +35,8 @@ #define CONFIG_VSTORE #define CONFIG_VSTORE_SLOT_COUNT 1 +#define CONFIG_HIBERNATE_PSL + /* Work around double CR50 reset by waiting in initial power on. */ #define CONFIG_BOARD_RESET_AFTER_POWER_ON |