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authorTing Shen <phoenixshen@google.com>2021-03-30 17:39:49 +0800
committerCommit Bot <commit-bot@chromium.org>2021-07-29 09:59:05 +0000
commit11be0bd36e7a91c0469f917f6ec767df14c2c80f (patch)
treeb45d311fc73172f04f824d5b715a5617aa180a36 /baseboard/cherry/baseboard.h
parent06309cebb69bc3d1f4711249463d013a76f9d950 (diff)
downloadchrome-ec-11be0bd36e7a91c0469f917f6ec767df14c2c80f.tar.gz
cherry: enable usb pd
BUG=b:177391887 TEST=verify pd works BRANCH=main Signed-off-by: Ting Shen <phoenixshen@google.com> Change-Id: Ied4516abef3d544b8b4bdf8355f0f9fc305629a3 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2793783 Commit-Queue: Ting Shen <phoenixshen@chromium.org> Tested-by: Ting Shen <phoenixshen@chromium.org> Reviewed-by: Eric Yilun Lin <yllin@google.com>
Diffstat (limited to 'baseboard/cherry/baseboard.h')
-rw-r--r--baseboard/cherry/baseboard.h23
1 files changed, 20 insertions, 3 deletions
diff --git a/baseboard/cherry/baseboard.h b/baseboard/cherry/baseboard.h
index 95cf2fe0bc..e3575c517c 100644
--- a/baseboard/cherry/baseboard.h
+++ b/baseboard/cherry/baseboard.h
@@ -96,6 +96,8 @@
#define I2C_PORT_ACCEL IT83XX_I2C_CH_B
#define I2C_PORT_PPC0 IT83XX_I2C_CH_C
#define I2C_PORT_PPC1 IT83XX_I2C_CH_E
+#define I2C_PORT_USB0 IT83XX_I2C_CH_C
+#define I2C_PORT_USB1 IT83XX_I2C_CH_E
#define I2C_PORT_USB_MUX0 IT83XX_I2C_CH_C
#define I2C_PORT_USB_MUX1 IT83XX_I2C_CH_E
#define I2C_PORT_VIRTUAL_BATTERY I2C_PORT_BATTERY
@@ -105,20 +107,23 @@
#define CONFIG_LED_COMMON
/* PD / USB-C / PPC */
+#define CONFIG_USB_PD_DEBUG_LEVEL 3
#define CONFIG_CMD_PPC_DUMP
#define CONFIG_HOSTCMD_PD_CONTROL
#define CONFIG_IT83XX_TUNE_CC_PHY
#define CONFIG_USBC_PPC
#define CONFIG_USBC_PPC_DEDICATED_INT
#define CONFIG_USBC_PPC_POLARITY
+#define CONFIG_USBC_PPC_RT1718S
#define CONFIG_USBC_PPC_SYV682X
#define CONFIG_USBC_PPC_VCONN
#define CONFIG_USBC_SS_MUX
#define CONFIG_USBC_VCONN
#define CONFIG_USBC_VCONN_SWAP
#define CONFIG_USB_DRP_ACC_TRYSRC
-#define CONFIG_USB_MUX_IT5205 /* C0 */
-#define CONFIG_USB_MUX_PS8743 /* C1 */
+#define CONFIG_USBC_RETIMER_PS8802 /* C0 */
+#define CONFIG_USB_MUX_ANX3443 /* C1 */
+#define CONFIG_USB_MUX_VIRTUAL
#define CONFIG_USB_PD_ALT_MODE
#define CONFIG_USB_PD_ALT_MODE_DFP
#define CONFIG_USB_PD_DECODE_SOP
@@ -127,12 +132,15 @@
#define CONFIG_USB_PD_DP_HPD_GPIO
#define CONFIG_USB_PD_DP_HPD_GPIO_CUSTOM
#define CONFIG_USB_PD_DUAL_ROLE
-#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 2
+#define CONFIG_USB_PD_DUAL_ROLE_AUTO_TOGGLE
+#define CONFIG_USB_PD_ITE_ACTIVE_PORT_COUNT 1
#define CONFIG_USB_PD_LOGGING
#define CONFIG_USB_PD_PORT_MAX_COUNT 2
+#define CONFIG_USB_PD_PPC
#define CONFIG_USB_PD_REV30
#define CONFIG_USB_PD_TCPC_LOW_POWER
#define CONFIG_USB_PD_TCPM_ITE_ON_CHIP
+#define CONFIG_USB_PD_TCPM_RT1718S
#define CONFIG_USB_PD_TCPM_TCPCI
#define CONFIG_USB_PD_TCPMV2
#define CONFIG_USB_PD_TRY_SRC
@@ -217,6 +225,15 @@ enum pwm_channel {
};
void board_reset_pd_mcu(void);
+void rt1718s_tcpc_interrupt(enum gpio_signal signal);
+
+enum rt1718s_gpio_state {
+ RT1718S_GPIO_DISABLED,
+ RT1718S_GPIO_ENABLE_SINK,
+ RT1718S_GPIO_ENABLE_SOURCE,
+};
+
+int rt1718s_gpio_ctrl(enum rt1718s_gpio_state state);
#endif /* !__ASSEMBLER__ */
#endif /* __CROS_EC_BASEBOARD_H */