diff options
| author | Scott Collyer <scollyer@google.com> | 2018-08-01 16:56:41 -0700 |
|---|---|---|
| committer | chrome-bot <chrome-bot@chromium.org> | 2018-09-04 21:03:59 -0700 |
| commit | c8df8cd58bb4d0bdbf3f953e4a4394dec797609f (patch) | |
| tree | 5de74f2c6183defc5db5595add9065afce8223c6 /baseboard/dragonegg | |
| parent | 50c762e0425570fab9b5a4eef13c3c76131bb1ff (diff) | |
| download | chrome-ec-c8df8cd58bb4d0bdbf3f953e4a4394dec797609f.tar.gz | |
DragonEgg: Add support to Type C port 1
Port 1 uses the ITE builtin TCPC, Silergy SYV682A PPC, and the parade
PS8818 redriver.
Port 1 is intended to use the EC ADC to detect VBUS, but port 0 and 2
require different methods. The Silergy can detect VBUS (not safe0V or
safe5v), so currently the PPC is being used to detect VBUS.
BUG=b:111281797
BRANCH=none
TEST=Verified that port 1 can attach as both a sink or source.
Change-Id: Iad0c3d509961c836cd55f77cd5f276c1a3e5aacf
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1159829
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Diffstat (limited to 'baseboard/dragonegg')
| -rw-r--r-- | baseboard/dragonegg/baseboard.c | 22 | ||||
| -rw-r--r-- | baseboard/dragonegg/baseboard.h | 8 |
2 files changed, 28 insertions, 2 deletions
diff --git a/baseboard/dragonegg/baseboard.c b/baseboard/dragonegg/baseboard.c index 678d84d040..14e9dc3923 100644 --- a/baseboard/dragonegg/baseboard.c +++ b/baseboard/dragonegg/baseboard.c @@ -9,6 +9,7 @@ #include "chipset.h" #include "console.h" #include "driver/ppc/sn5s330.h" +#include "driver/ppc/syv682x.h" #include "driver/tcpm/it83xx_pd.h" #include "driver/tcpm/tcpci.h" #include "driver/tcpm/tcpm.h" @@ -25,6 +26,7 @@ #include "util.h" #define USB_PD_PORT_ITE_0 0 +#define USB_PD_PORT_ITE_1 1 #define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args) #define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args) @@ -162,6 +164,12 @@ const struct tcpc_config_t tcpc_config[CONFIG_USB_PD_PORT_COUNT] = { .drv = &it83xx_tcpm_drv, .pol = TCPC_ALERT_ACTIVE_LOW, }, + + [USB_PD_PORT_ITE_1] = { + /* TCPC is embedded within EC so no i2c config needed */ + .drv = &it83xx_tcpm_drv, + .pol = TCPC_ALERT_ACTIVE_LOW, + }, }; /******************************************************************************/ @@ -172,11 +180,23 @@ struct ppc_config_t ppc_chips[CONFIG_USB_PD_PORT_COUNT] = { .i2c_addr = SN5S330_ADDR0, .drv = &sn5s330_drv }, + + [USB_PD_PORT_ITE_1] = { + .i2c_port = I2C_PORT_USBC1C2, + .i2c_addr = SYV682X_ADDR0, + .drv = &syv682x_drv + }, }; unsigned int ppc_cnt = ARRAY_SIZE(ppc_chips); struct usb_mux usb_muxes[CONFIG_USB_PD_PORT_COUNT] = { - { + [USB_PD_PORT_ITE_0] = { + .port_addr = 0, + .driver = &virtual_usb_mux_driver, + .hpd_update = &virtual_hpd_update, + }, + + [USB_PD_PORT_ITE_1] = { .port_addr = 0, .driver = &virtual_usb_mux_driver, .hpd_update = &virtual_hpd_update, diff --git a/baseboard/dragonegg/baseboard.h b/baseboard/dragonegg/baseboard.h index 535d1731c7..03f1d8bb91 100644 --- a/baseboard/dragonegg/baseboard.h +++ b/baseboard/dragonegg/baseboard.h @@ -21,6 +21,7 @@ /* #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE */ /* EC Defines */ +#define CONFIG_ADC #define CONFIG_PWM #define CONFIG_VBOOT_HASH #define CONFIG_VSTORE @@ -66,7 +67,7 @@ * on the MLB for now. In addition, this config option will likely move to * board.h as it likely board dependent and not same across all follower boards. */ -#define CONFIG_USB_PD_PORT_COUNT 1 +#define CONFIG_USB_PD_PORT_COUNT 2 #define CONFIG_USB_PD_MAX_SINGLE_SOURCE_CURRENT TYPEC_RP_3A0 #define CONFIG_USB_PD_DUAL_ROLE #define CONFIG_USB_PD_LOGGING @@ -75,10 +76,15 @@ #define CONFIG_USB_PD_DISCHARGE_PPC #define CONFIG_USB_PD_TRY_SRC #define CONFIG_USB_PD_VBUS_DETECT_PPC +/* + * TODO(b/113541930): ADC measurements are available for port 0 and 1, but not + * port 2. + */ #define CONFIG_USB_PD_VBUS_MEASURE_NOT_PRESENT #define CONFIG_USB_PD_TCPM_TCPCI #define CONFIG_USB_MUX_VIRTUAL #define CONFIG_USBC_PPC_SN5S330 /* C0 PPC */ +#define CONFIG_USBC_PPC_SYV682X /* C1 PPC */ #define CONFIG_USBC_PPC_VCONN #define CONFIG_USBC_SS_MUX #define CONFIG_USBC_VCONN |