DragonEgg: Add power sequencing support

This CL enables power sequencing for DragonEgg.

BRANCH=none
CQ-DEPEND=Iab4423abc9102164d4f43296a279c24355445341
BUG=b:111121615
TEST=make buildall

Change-Id: Id8c48a74b7b83153dc253222edc515c2488e7af5
Signed-off-by: Scott Collyer <scollyer@google.com>
Reviewed-on: https://chromium-review.googlesource.com/1126407
Commit-Ready: Scott Collyer <scollyer@chromium.org>
Tested-by: Scott Collyer <scollyer@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@chromium.org>

2 files changed, 118 insertions, 1 deletions

diff --git a/baseboard/dragonegg/baseboard.c b/baseboard/dragonegg/baseboard.c
index 629da06e42..42335d3902 100644
--- a/baseboard/dragonegg/baseboard.c
+++ b/baseboard/dragonegg/baseboard.c
@@ -4,12 +4,28 @@
  */
 
 /* DragonEgg family-specific configuration */
-
+#include "chipset.h"
+#include "console.h"
+#include "espi.h"
 #include "gpio.h"
+#include "hooks.h"
 #include "i2c.h"
+#include "power.h"
+#include "timer.h"
 #include "util.h"
 
+#define CPRINTS(format, args...) cprints(CC_SYSTEM, format, ## args)
+#define CPRINTF(format, args...) cprintf(CC_SYSTEM, format, ## args)
+
 /******************************************************************************/
+/* Wake up pins */
+const enum gpio_signal hibernate_wake_pins[] = {
+	GPIO_LID_OPEN,
+	GPIO_AC_PRESENT,
+	GPIO_POWER_BUTTON_L,
+};
+const int hibernate_wake_pins_used = ARRAY_SIZE(hibernate_wake_pins);
+
 /* I2C port map configuration */
 /* TODO(b/111125177): Increase these speeds to 400 kHz and verify operation */
 const struct i2c_port_t i2c_ports[] = {
@@ -20,3 +36,81 @@ const struct i2c_port_t i2c_ports[] = {
 	{"power",  IT83XX_I2C_CH_F, 100, GPIO_I2C5_SCL, GPIO_I2C5_SDA}
 };
 const unsigned int i2c_ports_used = ARRAY_SIZE(i2c_ports);
+
+/* power signal list. */
+const struct power_signal_info power_signal_list[] = {
+	[X86_SLP_S0_DEASSERTED] = {GPIO_SLP_S0_L,
+		POWER_SIGNAL_ACTIVE_HIGH | POWER_SIGNAL_DISABLE_AT_BOOT,
+		"SLP_S0_DEASSERTED"},
+#ifdef CONFIG_HOSTCMD_ESPI_VW_SIGNALS
+	[X86_SLP_S3_DEASSERTED] = {VW_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH,
+				   "SLP_S3_DEASSERTED"},
+	[X86_SLP_S4_DEASSERTED] = {VW_SLP_S4_L, POWER_SIGNAL_ACTIVE_HIGH,
+				   "SLP_S4_DEASSERTED"},
+#else
+	[X86_SLP_S3_DEASSERTED] = {GPIO_SLP_S3_L, POWER_SIGNAL_ACTIVE_HIGH,
+				   "SLP_S3_DEASSERTED"},
+	[X86_SLP_S4_DEASSERTED] = {GPIO_SLP_S4_L, POWER_SIGNAL_ACTIVE_HIGH,
+				   "SLP_S4_DEASSERTED"},
+#endif
+	[X86_SLP_SUS_DEASSERTED] = {GPIO_SLP_SUS_L, POWER_SIGNAL_ACTIVE_HIGH,
+				    "SLP_SUS_DEASSERTED"},
+	[X86_RSMRST_L_PGOOD] = {GPIO_PG_EC_RSMRST_ODL, POWER_SIGNAL_ACTIVE_HIGH,
+				"RSMRST_L_PGOOD"},
+	[X86_DSW_DPWROK] = {GPIO_PG_EC_DSW_PWROK, POWER_SIGNAL_ACTIVE_HIGH,
+			    "DSW_DPWROK"},
+};
+BUILD_ASSERT(ARRAY_SIZE(power_signal_list) == POWER_SIGNAL_COUNT);
+
+/******************************************************************************/
+/* Chipset callbacks/hooks */
+
+/* Called on AP S5 -> S3 transition */
+static void baseboard_chipset_startup(void)
+{
+	/* TODD(b/111121615): Need to fill out this hook */
+}
+DECLARE_HOOK(HOOK_CHIPSET_STARTUP, baseboard_chipset_startup,
+	     HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0iX -> S0 transition */
+static void baseboard_chipset_resume(void)
+{
+	/* TODD(b/111121615): Need to fill out this hook */
+}
+DECLARE_HOOK(HOOK_CHIPSET_RESUME, baseboard_chipset_resume, HOOK_PRIO_DEFAULT);
+
+/* Called on AP S0 -> S0iX transition */
+static void baseboard_chipset_suspend(void)
+{
+	/* TODD(b/111121615): Need to fill out this hook */
+}
+DECLARE_HOOK(HOOK_CHIPSET_SUSPEND, baseboard_chipset_suspend,
+	     HOOK_PRIO_DEFAULT);
+
+/* Called on AP S3 -> S5 transition */
+static void baseboard_chipset_shutdown(void)
+{
+	/* TODD(b/111121615): Need to fill out this hook */
+}
+DECLARE_HOOK(HOOK_CHIPSET_SHUTDOWN, baseboard_chipset_shutdown,
+	     HOOK_PRIO_DEFAULT);
+
+void board_hibernate(void)
+{
+	int timeout_ms = 20;
+	/*
+	 * Disable the TCPC power rail and the PP5000 rail before going into
+	 * hibernate. Note, these 2 rails are powered up as the default state in
+	 * gpio.inc.
+	 */
+	gpio_set_level(GPIO_EN_PP5000, 0);
+	/* Wait for PP5000 to drop before disabling PP3300_TCPC */
+	while (gpio_get_level(GPIO_PP5000_PG_OD) && timeout_ms > 0) {
+		msleep(1);
+		timeout_ms--;
+	}
+	if (!timeout_ms)
+		CPRINTS("PP5000_PG didn't go low after 20 msec");
+	gpio_set_level(GPIO_EN_PP3300_TCPC, 0);
+}
diff --git a/baseboard/dragonegg/baseboard.h b/baseboard/dragonegg/baseboard.h
index 142f363f0e..d2879607e1 100644
--- a/baseboard/dragonegg/baseboard.h
+++ b/baseboard/dragonegg/baseboard.h
@@ -8,6 +8,15 @@
 #ifndef __CROS_EC_BASEBOARD_H
 #define __CROS_EC_BASEBOARD_H
 
+#define CONFIG_CHIPSET_ICELAKE
+#define CONFIG_CHIPSET_RESET_HOOK
+#define CONFIG_EXTPOWER_GPIO
+#define CONFIG_POWER_BUTTON
+#define CONFIG_POWER_BUTTON_X86
+/* TODO(b/111155507): Don't enable SOiX for now */
+/* #define CONFIG_POWER_S0IX */
+/* #define CONFIG_POWER_TRACK_HOST_SLEEP_STATE */
+
 /* I2C Bus Configuration */
 #define I2C_PORT_BATTERY	IT83XX_I2C_CH_F	/* Shared bus */
 #define I2C_PORT_CHARGER	IT83XX_I2C_CH_F	/* Shared bus */
@@ -17,4 +26,18 @@
 #define I2C_PORT_EEPROM		IT83XX_I2C_CH_A
 #define I2C_ADDR_EEPROM		0xA0
 
+#ifndef __ASSEMBLER__
+
+enum power_signal {
+	X86_SLP_S0_DEASSERTED,
+	X86_SLP_S3_DEASSERTED,
+	X86_SLP_S4_DEASSERTED,
+	X86_SLP_SUS_DEASSERTED,
+	X86_RSMRST_L_PGOOD,
+	X86_DSW_DPWROK,
+	/* Number of X86 signals */
+	POWER_SIGNAL_COUNT
+};
+#endif /* !__ASSEMBLER__ */
+
 #endif /* __CROS_EC_BASEBOARD_H */