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| author | Rob Barnes <robbarnes@google.com> | 2021-03-11 17:04:58 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-12 02:16:18 +0000 |
| commit | b2c96a8fff263cc26bca24afc310c3de248fe53b (patch) | |
| tree | 13f8683e2ac406e14947cea6aaf9b0bc6c3fc3d2 /baseboard/guybrush/base_gpio.inc | |
| parent | 01e7c7cc367f1e17804640f7820f071738b2f83a (diff) | |
| download | chrome-ec-b2c96a8fff263cc26bca24afc310c3de248fe53b.tar.gz | |
kconfig: Alias EN_PWR_A to EN_PWR_S5
EN_PWR_A should alias to EN_PWR_S5. EN_PWR_Z1 is PSL_OUT.
BUG=b:182512084
TEST=Build
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Iabec65bb573d200a12e727d281f8c97cf1ee0ec4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2753816
Reviewed-by: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'baseboard/guybrush/base_gpio.inc')
| -rw-r--r-- | baseboard/guybrush/base_gpio.inc | 1 |
1 files changed, 0 insertions, 1 deletions
diff --git a/baseboard/guybrush/base_gpio.inc b/baseboard/guybrush/base_gpio.inc index 16c3e6e97c..9f704a51bd 100644 --- a/baseboard/guybrush/base_gpio.inc +++ b/baseboard/guybrush/base_gpio.inc @@ -25,7 +25,6 @@ GPIO_INT(PG_GROUPC_S0_OD, PIN(A, 3), GPIO_INT_BOTH, baseboard_en_pwr_pcore_s0 GPIO_INT(PG_LPDDR4X_S3_OD, PIN(9, 5), GPIO_INT_BOTH, baseboard_en_pwr_pcore_s0) /* Power Group LPDDR4 S3 */ GPIO(EN_PWR_S5, PIN(B, 7), GPIO_OUT_LOW) /* Enable S5 Power */ GPIO(EN_PWR_S0_R, PIN(F, 1), GPIO_OUT_LOW) -GPIO(EN_PWR_Z1, PIN(8, 5), GPIO_OUT_LOW) /* Enable Z1 Power */ GPIO(EN_PWR_PCORE_S0_R, PIN(E, 1), GPIO_OUT_LOW) ALTERNATE(/*MECH_PWR_BTN_ODL*/ PIN_MASK(D, BIT(2)), 0, MODULE_PMU, 0) /* PSL - Mechanical Power Button */ ALTERNATE(/*LID_OPEN*/ PIN_MASK(0, BIT(2)), 0, MODULE_PMU, 0) /* PSL - Lid Open */ |