diff options
| author | Rob Barnes <robbarnes@google.com> | 2021-03-17 07:07:03 -0600 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-03-17 16:23:02 +0000 |
| commit | 57629d8a2335d5d6e8fd817abe5b711eb42843e4 (patch) | |
| tree | a2823826415da7a858a9105599233f983d723a2c /baseboard/guybrush/base_gpio.inc | |
| parent | 9882a691495ed26385149b3cc839d5513e83ee2f (diff) | |
| download | chrome-ec-57629d8a2335d5d6e8fd817abe5b711eb42843e4.tar.gz | |
guybrush: Remove SOC eSPI GPIOs
Configuring the eSPI signals to default may be causing a conflict with
the npcx eSPI driver.
BUG=b:182989724
TEST=Build
BRANCH=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: I44390540b28661eb6add7a925f7490594a5e3764
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2766524
Commit-Queue: Diana Z <dzigterman@chromium.org>
Reviewed-by: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'baseboard/guybrush/base_gpio.inc')
| -rw-r--r-- | baseboard/guybrush/base_gpio.inc | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/baseboard/guybrush/base_gpio.inc b/baseboard/guybrush/base_gpio.inc index 2424515dfe..6581bee357 100644 --- a/baseboard/guybrush/base_gpio.inc +++ b/baseboard/guybrush/base_gpio.inc @@ -116,7 +116,12 @@ ALTERNATE(/*KSO_03-09*/ PIN_MASK(1, GENMASK(6, 0)), 0, MODULE_KEYBOARD_SCAN, ALTERNATE(/*KSO_10-13*/ PIN_MASK(0, GENMASK(7, 4)), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) ALTERNATE(/*KSO_14*/ PIN_MASK(8, BIT(2)), 0, MODULE_KEYBOARD_SCAN, GPIO_ODR_HIGH) -/* SOC eSPI Bus */ +#if 0 +/* + * SOC eSPI Bus + * These signals do not need to be explicitly configured. + * Leaving here so all signals are documented. + */ GPIO(ESPI_SOC_CLK, PIN(5, 5), GPIO_DEFAULT) GPIO(ESPI_SOC_CS_EC_L, PIN(5, 3), GPIO_DEFAULT) GPIO(ESPI_SOC_D0_EC, PIN(4, 6), GPIO_DEFAULT) @@ -125,6 +130,7 @@ GPIO(ESPI_SOC_D2_EC, PIN(5, 1), GPIO_DEFAULT) GPIO(ESPI_SOC_D3_EC, PIN(5, 2), GPIO_DEFAULT) GPIO(EC_ESPI_RST_L, PIN(5, 4), GPIO_DEFAULT) GPIO(ESPI_EC_ALERT_SOC_L, PIN(5, 7), GPIO_DEFAULT) +#endif /* TCPC C0 */ IOEX(USB_C0_PPC_EN_L, EXPIN(USBC_PORT_C0, 1, 0), GPIO_OUT_HIGH) |