diff options
| author | Rob Barnes <robbarnes@google.com> | 2021-01-08 10:53:31 -0700 |
|---|---|---|
| committer | Commit Bot <commit-bot@chromium.org> | 2021-01-15 03:02:54 +0000 |
| commit | eaf3ff76c4d5c1e504394282432be5cd4006138a (patch) | |
| tree | 119a03f252d0063b9dbff97cbe43a4e724ebc097 /baseboard/guybrush/base_gpio.inc | |
| parent | 9513a57c87a12f2533efcbe26cc338c209a81b42 (diff) | |
| download | chrome-ec-eaf3ff76c4d5c1e504394282432be5cd4006138a.tar.gz | |
guybrush: AND PG_LPDDR4X_S3 and PG_GROUPC_S0 signals
Latest schematic removes discrete AND gate and moves logic to EC.
PG_LPDDR4X_S3 and PG_GROUPC_S0 are anded to drive EN_PWR_PCORE_S0.
BUG=b:177071076
BRANCH=None
TEST=None
Signed-off-by: Rob Barnes <robbarnes@google.com>
Change-Id: Ic4e50015b495faad4a23e09faa5cd520eb158fe4
Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/2618386
Reviewed-by: Diana Z <dzigterman@chromium.org>
Commit-Queue: Diana Z <dzigterman@chromium.org>
Diffstat (limited to 'baseboard/guybrush/base_gpio.inc')
| -rw-r--r-- | baseboard/guybrush/base_gpio.inc | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/baseboard/guybrush/base_gpio.inc b/baseboard/guybrush/base_gpio.inc index f6a9d48e1c..17ba1e1a31 100644 --- a/baseboard/guybrush/base_gpio.inc +++ b/baseboard/guybrush/base_gpio.inc @@ -21,8 +21,8 @@ GPIO_INT(PG_PWR_S5, PIN(C, 0), GPIO_INT_BOTH, power_signal_interrupt) /* S5 P GPIO_INT(PG_PCORE_S0_R_OD, PIN(B, 6), GPIO_INT_BOTH, power_signal_interrupt) /* S0 Power OK */ GPIO_INT(ACOK_OD, PIN(0, 0), GPIO_INT_BOTH | GPIO_HIB_WAKE_HIGH, extpower_interrupt) /* AC Power Present */ GPIO_INT(EC_PCORE_INT_ODL, PIN(F, 0), GPIO_INT_BOTH | GPIO_PULL_UP, power_signal_interrupt) /* Power Core Interrupt */ -GPIO_INT(PG_GROUPC_S0_OD, PIN(A, 3), GPIO_INT_BOTH, power_signal_interrupt) /* Power Group C S0 */ -GPIO_INT(PG_LPDDR4X_S3_OD, PIN(9, 5), GPIO_INT_BOTH, power_signal_interrupt) /* Power Group LPDDR4 S3 */ +GPIO_INT(PG_GROUPC_S0_OD, PIN(A, 3), GPIO_INT_BOTH, baseboard_en_pwr_pcore_s0) /* Power Group C S0 */ +GPIO_INT(PG_LPDDR4X_S3_OD, PIN(9, 5), GPIO_INT_BOTH, baseboard_en_pwr_pcore_s0) /* Power Group LPDDR4 S3 */ GPIO(EN_PWR_S5, PIN(B, 7), GPIO_OUT_LOW) /* Enable S5 Power */ GPIO(EN_PWR_S0_R, PIN(F, 1), GPIO_OUT_LOW) GPIO(EN_PWR_Z1, PIN(8, 5), GPIO_OUT_LOW) /* Enable Z1 Power */ |